CN111243548B - Array substrate, liquid crystal display panel and public voltage adjusting method thereof - Google Patents
Array substrate, liquid crystal display panel and public voltage adjusting method thereof Download PDFInfo
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- CN111243548B CN111243548B CN202010209243.1A CN202010209243A CN111243548B CN 111243548 B CN111243548 B CN 111243548B CN 202010209243 A CN202010209243 A CN 202010209243A CN 111243548 B CN111243548 B CN 111243548B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3696—Generation of voltages supplied to electrode drivers
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0202—Addressing of scan or signal lines
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
Abstract
The application discloses a liquid crystal display panel and a public voltage adjusting method thereof.A array substrate comprises a plurality of areas which are arranged in an array manner, and each area comprises a plurality of pixel areas; a first field effect transistor, a second field effect transistor and a third field effect transistor are arranged in each pixel region; the control end of the first field effect transistor is electrically connected with the scanning line, the input end of the first field effect transistor is electrically connected with the data line, the output end of the first field effect transistor is electrically connected with the common end of the second field effect transistor and the common end of the second field effect transistor, and the width of the active layer in the first field effect transistor in different regions is not completely the same; the beneficial effects are that: the display panel is divided into a plurality of areas, and the widths of the active layers of the first field effect transistors in different areas are set to be different according to different driving modes, so that local flicker of the display panel is reduced, and the display uniformity of the whole display panel is better.
Description
Technical Field
The application relates to the technical field of communication, in particular to the technical field of equipment, and specifically relates to an array substrate, a liquid crystal display panel and a public voltage adjusting method thereof.
Background
Liquid Crystal Displays (LCDs) are widely used in large-sized Liquid crystal display panels due to their advantages of high contrast and wide viewing angle. However, the FFS mode still has some problems that are not solved, one of them is Flicker (Flicker), and especially the Flicker degree at different points in the panel is different, which causes the Flicker difference in the whole liquid crystal display panel and causes the Flicker non-uniformity. The flicker unevenness is mainly caused by the difference between the positive frame brightness and the negative frame brightness, namely, when the grid voltage signal of the field effect transistor is changed from high voltage to low voltage and the field effect transistor is changed from a conducting state to a cutting-off state, the data voltage charged by the pixel electrode reduces the TFT parasitic capacitance recoil voltage DeltaVp, and the expression of the recoil voltage DeltaVp is as follows:
△Vp=Cgs*（Vgh-Vgl）/（Cgs+Cst+Clc）
wherein Cgs is a parasitic capacitance between a gate and a source in the field effect transistor, Cst is a storage capacitance, and Clc is a liquid crystal capacitance. The liquid crystal display is driven by Alternating Current (AC), and a data signal (data signal) is changed between positive drive (positive drive) and negative drive (negative drive). If the positive data voltage is supplied during the positive polarity period, the negative data voltage is supplied during the negative polarity period, and the positive data voltage and the negative data voltage have the same gray scale. The array substrate comprises a plurality of criss-cross scanning lines and data lines, each group of data lines and scanning lines are used for controlling one display unit, and each display unit comprises: a field effect transistor, a liquid crystal capacitor and a storage capacitor. The grid electrode of the field effect transistor is connected with the scanning line, the drain electrode of the field effect transistor is connected with the data line, the source electrode of the field effect transistor is connected with the common end of the liquid crystal capacitor and the storage capacitor, and the other end of the storage capacitor is electrically connected with the common electrode.
When the liquid crystal display panel works, the scanning signals on the scanning lines control the on/off state of the field effect transistors, and the data signals on the data lines are written into the liquid crystal capacitors and the storage capacitors through the field effect transistors. Because each scanning line is a wire with certain impedance, a plurality of liquid crystal capacitors and storage capacitors and a plurality of field effect transistors generate parasitic capacitance, thereby influencing the transmission process of scanning signals on the scanning lines. The scanning signal waveform is deformed under the influence of the impedance effect and the capacitance effect, so that the variation of the pixel voltage stored in each liquid crystal capacitor and the storage capacitor generates difference.
Therefore, in the existing liquid crystal display panel technology, there are still problems that the feedthrough voltage and the leakage current in the liquid crystal display panel cause local flicker of the picture of the display panel, the uniformity is not high, and the display quality of the display panel is affected, and improvement is urgently needed.
Disclosure of Invention
The embodiment of the application provides an array substrate, a liquid crystal display panel and a public voltage adjusting method thereof, and aims to solve the problems that in the prior art, the feed-through voltage and the leakage current in the liquid crystal display panel cause local flicker of a picture of the display panel, the uniformity is not high, and the display quality of the display panel is influenced.
The embodiment of the application provides an array substrate, which comprises a plurality of regions arranged in an array manner, wherein each region comprises a plurality of pixel regions; a first field effect transistor, a second field effect transistor and a third field effect transistor are arranged in each pixel region; the control end of the first field effect transistor is electrically connected with the scanning line, the input end of the first field effect transistor is electrically connected with the data line, the output end of the first field effect transistor is electrically connected with the common end of the second field effect transistor and the common end of the second field effect transistor, and the width of the active layer in the first field effect transistor in different regions is not completely the same.
In some embodiments provided herein, the plurality of regions is three regions or nine regions.
In some embodiments provided herein, the three regions are distributed along the X-axis direction or along the Y-axis direction; the nine areas are distributed along the X-axis direction and the Y-axis direction simultaneously.
In some embodiments provided herein, a width of the active layer of the first field effect transistor in a region near a center of the array substrate is smaller than a width of the active layer of the first field effect transistor in a region near a periphery of the array substrate.
In some embodiments provided in the present application, the driving method of the array substrate includes: drive without demultiplexer interleave, drive without demultiplexer fill, drive with demultiplexer interleave, drive with demultiplexer fill.
The present application further provides a liquid crystal display panel, the liquid crystal display panel is divided into a plurality of regions, and each region includes: the liquid crystal display panel comprises a color film substrate, an array substrate and a liquid crystal layer arranged between the color film substrate and the array substrate; the array substrate in each region is provided with a plurality of film layers including field effect transistor layers, wherein the widths of the active layers of the first field effect transistors in each region are not completely the same, namely the overlapping areas of the active layers in each region and the gates in the field effect transistors are not completely the same.
The application also provides a method for adjusting the common voltage of the liquid crystal display panel, which comprises the following steps:
s10, dividing the area of the liquid crystal display panel into m × n areas;
s20, sampling and simulating the common voltage values of the divided regions, and simulating to obtain an optimal first common voltage value Vcom1 in each region;
s30, determining the parasitic capacitance value of the central point in the whole liquid crystal display panel as a rated parasitic capacitance value Cgs, carrying out subtraction operation on the parasitic capacitance value Cgs1 in each region obtained by simulation and the rated parasitic capacitance value Cgs to obtain the difference value delta Cgs of the parasitic capacitance values in each region, and carrying out corresponding compensation;
s40, sampling and simulating the compensated liquid crystal display panel again, and simulating along each region to obtain an optimal second common voltage value Vcom2 in each region;
s50, determining a common voltage value at a center point in the entire liquid crystal display panel as a nominal common voltage value Vcom, and performing subtraction operation on the second common voltage value Vcom2 in each region obtained through simulation and the nominal common voltage value Vcom to obtain a difference Δ Vcom of the common voltage values in each region;
s60, if the difference between the second common voltage value Vcom2 and the rated common voltage value Vcom in each region is not within a preset range, recalculating the difference between the parasitic capacitance value and the rated parasitic capacitance value in each region;
s70, determining a compensation value of a parasitic capacitance value in each region if a difference between the second common voltage value Vcom2 and the nominal common voltage value Vcom in each region is within a preset range;
and S80, converting the compensation value of the parasitic capacitance value in each region into a width value of an active layer in the field effect transistor in each region.
In some embodiments provided herein, the m × n regions are: 1 × 3 regions, 3 × 1 regions or 3 × 3 regions.
In some embodiments provided herein, the regions are distributed along an X-axis direction, along a Y-axis direction, or along both the X-axis and the Y-axis directions.
In some embodiments provided herein, the regions are distributed along an X-axis direction, along a Y-axis direction, or along both the X-axis and the Y-axis directions.
In some embodiments provided herein, the sampling simulation manner described in step S20 is sampling simulation.
Compared with the prior art, the array substrate, the liquid crystal display panel and the adjusting method of the public voltage thereof have the advantages that:
1. according to the array substrate and the liquid crystal display panel, the display panel is divided into a plurality of areas, and the widths of the active layers of the first field effect transistors in different areas are set to be different according to different driving modes, so that the local flicker of the display panel is reduced, and the display uniformity of the whole display panel is better;
2. the method for adjusting the common voltage of the liquid crystal display panel can simulate the display panel in different regions, measure the value of the value to be compensated of the width of the active layer of the first field effect transistor in different regions, improve the local flicker of the display panel and improve the display quality of the display panel.
Drawings
The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.
Fig. 1 is a schematic view of a first structure of a liquid crystal display panel according to an embodiment of the present disclosure.
Fig. 2 is a second structural schematic diagram of the liquid crystal display panel according to the embodiment of the present application.
Fig. 3 is a schematic diagram of a third structure of a liquid crystal display panel according to an embodiment of the present application.
Fig. 4 is a schematic structural diagram of a liquid crystal display panel driving circuit according to an embodiment of the present application.
Fig. 5 is a schematic diagram of compensation of the liquid crystal display panel without the demultiplexer in the interlace driving according to the embodiment of the present application.
Fig. 6 is a schematic diagram of compensation of the liquid crystal display panel provided by the embodiment of the present application when the demultiplexer-free pair is driven.
Fig. 7 is a schematic diagram of compensation in the case of cross-driving the demultiplexer of the lcd panel according to the embodiment of the present application.
Fig. 8 is a schematic diagram of compensation of the demultiplexer pair driving of the lcd panel according to the embodiment of the present application.
Fig. 9 is a waveform diagram of a common voltage of the array substrate when a gate voltage of the first field effect transistor in each region changes from a high voltage to a low voltage according to an embodiment of the present disclosure.
Fig. 10 is a flowchart illustrating a method for adjusting a common voltage of a liquid crystal display panel according to an embodiment of the present disclosure.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it is to be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present application and for simplicity in description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated in a particular manner, and are not to be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise direct contact of the first and second features, or may comprise contact of the first and second features not directly but through another feature in between. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
The following disclosure provides many different embodiments or examples for implementing different features of the application. In order to simplify the disclosure of the present application, specific example components and arrangements are described below. Of course, they are merely examples and are not intended to limit the present application. Moreover, the present application may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, examples of various specific processes and materials are provided herein, but one of ordinary skill in the art may recognize applications of other processes and/or use of other materials.
Specifically, referring to fig. 1 to 10, an embodiment of the present invention provides an array substrate, a liquid crystal display panel and a method for adjusting a common voltage thereof.
The embodiment of the application provides an array substrate, which comprises a plurality of regions arranged in an array manner, wherein each region comprises a plurality of pixel regions; a first field effect transistor, a second field effect transistor and a third field effect transistor are arranged in each pixel region; the control end of the first field effect transistor is electrically connected with the scanning line, the input end of the first field effect transistor is electrically connected with the data line, the output end of the first field effect transistor is electrically connected with the common end of the second field effect transistor and the common end of the second field effect transistor, and the width of the active layer in the first field effect transistor in different regions is not completely the same.
Referring to fig. 1 to 3, in some embodiments provided in the present application, the plurality of regions are three regions or nine regions.
In some embodiments provided herein, the three regions are distributed along the X-axis direction or the Y-axis direction, and in detail, referring to fig. 1, the three regions are arranged along the Y-axis direction, and are divided into: a first region 11, a second region 12 and a third region 13, see fig. 2 in detail, which are arranged along the X-axis direction and are divided into a first region 21, a second region 22 and a third region 23; the nine areas are distributed along the X-axis direction and the Y-axis direction at the same time, and are divided into the following parts in detail as shown in FIG. 3: a first region 31, a second region 32, a third region 33, a fourth region 34, a fifth region 35, a sixth region 36, a seventh region 38, and a ninth region 39.
In some embodiments of the present application, a width of the active layer of the first field effect transistor in a region near a center of the array substrate is smaller than a width of the active layer of the first field effect transistor in a region near a periphery of the array substrate.
Further, each region includes a plurality of scanning lines 41 and data lines 42 intersecting horizontally and vertically, and pixel units 43 composed of the scanning lines 41 and the data lines 42; each of the pixel units 43 further includes: a first field effect transistor 431, a second field effect transistor 432, and a third field effect transistor 433; the second field effect transistor 432 and the third field effect transistor 433 are respectively a liquid crystal capacitor and a storage capacitor; the first field effect transistor is a switching transistor, and the fourth field effect transistor 434 is a parasitic capacitor.
Further, the first field effect transistor, the second field effect transistor, the third field effect transistor, and the fourth field effect transistor may be thin film transistors.
In some embodiments of the present application, the driving method of the array substrate includes: drive without demultiplexer interleave, drive without demultiplexer fill, drive with demultiplexer interleave, drive with demultiplexer fill. Referring to fig. 5 to 8, it is known that, when the array substrate is driven by a demultiplexer-free staggered driving method, a demultiplexer-free charging driving method, a demultiplexer staggered driving method, or a demultiplexer charging driving method, the relationship between the common voltage value Vcom of the array substrate before and after compensation and the compensation value has a certain effect on the display quality of the display panel, that is, increasing the width of the active layer of the first field effect transistor in the corresponding region can reduce the capacitance of the parasitic capacitor, and as the feed-through voltage (Δ Vp) = (VGH-VGL) × Cgs/(Cgs + Clc + Cst), the final value of the feed-through voltage Δ Vp is kept unchanged, thereby ensuring the uniformity of the display brightness of the display panel and improving the local flicker phenomenon. Referring to fig. 9, a modified common voltage value Vcom of the array substrate is shown.
Further, the present application also provides a liquid crystal display panel, the liquid crystal display panel is divided into a plurality of regions, each region includes: the liquid crystal display panel comprises a color film substrate, an array substrate and a liquid crystal layer arranged between the color film substrate and the array substrate; the array substrate in each region is provided with a plurality of film layers including field effect transistor layers, wherein the widths of the active layers of the first field effect transistors in each region are not completely the same, namely the overlapping areas of the active layers in each region and the gates in the field effect transistors are not completely the same.
Referring to fig. 10, a method for adjusting a common voltage of a liquid crystal display panel provided by the present application includes the following steps: s10, dividing the area of the liquid crystal display panel into m × n areas; s20, sampling and simulating the common voltage values of the divided regions, and simulating to obtain an optimal first common voltage value Vcom1 in each region; s30, determining the parasitic capacitance value of the central point in the whole liquid crystal display panel as a rated parasitic capacitance value Cgs, carrying out subtraction operation on the parasitic capacitance value Cgs1 in each region obtained by simulation and the rated parasitic capacitance value Cgs to obtain the difference value delta Cgs of the parasitic capacitance values in each region, and carrying out corresponding compensation; s40, sampling and simulating the compensated liquid crystal display panel again, and simulating along each region to obtain an optimal second common voltage value Vcom2 in each region; s50, determining a common voltage value at a center point in the entire liquid crystal display panel as a nominal common voltage value Vcom, and performing subtraction operation on the second common voltage value Vcom2 in each region obtained through simulation and the nominal common voltage value Vcom to obtain a difference Δ Vcom of the common voltage values in each region; s60, if the difference between the second common voltage value Vcom2 and the rated common voltage value Vcom in each region is not within a preset range, recalculating the difference between the parasitic capacitance value and the rated parasitic capacitance value in each region; s70, determining a compensation value of a parasitic capacitance value in each region if a difference between the second common voltage value Vcom2 and the nominal common voltage value Vcom in each region is within a preset range; and S80, converting the compensation value of the parasitic capacitance value in each region into a width value of an active layer in the field effect transistor in each region.
In some embodiments provided herein, the m × n regions are: 1 × 3 regions, 3 × 1 regions or 3 × 3 regions.
In some embodiments provided herein, the regions are distributed along an X-axis direction, along a Y-axis direction, or along both the X-axis and the Y-axis directions.
In some embodiments provided herein, the regions are distributed along an X-axis direction, along a Y-axis direction, or along both the X-axis and the Y-axis directions.
In some embodiments provided herein, the sampling simulation manner described in step S20 is sampling simulation.
Therefore, compared with the prior art, the array substrate, the liquid crystal display panel and the adjusting method of the common voltage thereof have the advantages that: firstly, the array substrate and the liquid crystal display panel provided by the application divide the display panel into a plurality of areas, and the widths of the active layers of the first field effect transistors in different areas are set to be different according to different driving modes so as to reduce local flicker of the display panel and enable the display uniformity of the whole display panel to be better; secondly, the method for adjusting the common voltage of the liquid crystal display panel can simulate the display panel in different regions, and measure the value of the value to be compensated of the width of the active layer of the first field effect transistor in different regions, so that the local flicker of the display panel is improved, and the display quality of the display panel is improved.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
The array substrate, the liquid crystal display panel and the method for adjusting the common voltage thereof provided by the embodiments of the present application are introduced in detail above, and a specific example is applied in the present application to explain the principle and the implementation manner of the present application, and the description of the above embodiments is only used to help understanding the technical scheme and the core idea of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.
Claims (9)
1. The array substrate is characterized by comprising a plurality of regions which are arranged in an array mode, wherein each region comprises a plurality of pixel regions; a first field effect transistor, a second field effect transistor and a third field effect transistor are arranged in each pixel region; the control end of the first field effect transistor is electrically connected with the scanning line, the input end of the first field effect transistor is electrically connected with the data line, the output end of the first field effect transistor is electrically connected with the common end of the second field effect transistor and the common end of the second field effect transistor, and the width of the active layer in the first field effect transistor in different regions is not completely the same;
the driving method of the array substrate comprises the following steps: drive without demultiplexer interleave, drive without demultiplexer fill, drive with demultiplexer interleave, drive with demultiplexer fill.
2. The array substrate of claim 1, wherein the plurality of regions is three regions or nine regions.
3. The array substrate of claim 2, wherein the three regions are distributed along an X-axis direction or a Y-axis direction; the nine areas are distributed along the X-axis direction and the Y-axis direction simultaneously.
4. The array substrate of claim 1, wherein the width of the active layer of the first field effect transistor in a region near the center of the array substrate is smaller than the width of the active layer of the first field effect transistor in a region near the periphery of the array substrate.
5. A liquid crystal display panel, wherein the liquid crystal display panel is divided into a plurality of regions, each region comprising: the liquid crystal display panel comprises a color film substrate, an array substrate and a liquid crystal layer arranged between the color film substrate and the array substrate; a plurality of film layers including field effect transistor layers are arranged in the array substrate in each region, wherein the widths of the active layers of the first field effect transistors in each region are not completely the same, namely the overlapping areas of the active layers in each region and the gates in the field effect transistors are not completely the same;
the driving method of the array substrate comprises the following steps: drive without demultiplexer interleave, drive without demultiplexer fill, drive with demultiplexer interleave, drive with demultiplexer fill.
6. A method for adjusting the common voltage of a liquid crystal display panel is characterized by comprising the following steps:
s10, dividing the area of the liquid crystal display panel into m × n areas;
s20, sampling and simulating the common voltage values of the divided regions, and simulating to obtain an optimal first common voltage value Vcom1 in each region;
s30, determining the parasitic capacitance value of the central point in the whole liquid crystal display panel as a rated parasitic capacitance value Cgs, carrying out subtraction operation on the parasitic capacitance value Cgs1 in each region obtained by simulation and the rated parasitic capacitance value Cgs to obtain the difference value delta Cgs of the parasitic capacitance values in each region, and carrying out corresponding compensation;
s40, sampling and simulating the compensated liquid crystal display panel again, and simulating along each region to obtain an optimal second common voltage value Vcom2 in each region;
s50, determining a common voltage value at a center point in the entire liquid crystal display panel as a nominal common voltage value Vcom, and performing subtraction operation on the second common voltage value Vcom2 in each region obtained through simulation and the nominal common voltage value Vcom to obtain a difference Δ Vcom of the common voltage values in each region;
s60, if the difference between the second common voltage value Vcom2 and the rated common voltage value Vcom in each region is not within a preset range, recalculating the difference between the parasitic capacitance value and the rated parasitic capacitance value in each region;
s70, determining a compensation value of a parasitic capacitance value in each region if a difference between the second common voltage value Vcom2 and the nominal common voltage value Vcom in each region is within a preset range;
and S80, converting the compensation value of the parasitic capacitance value in each region into a width value of an active layer in the field effect transistor in each region.
7. The method according to claim 6, wherein the m × n regions are: 1 × 3 regions, 3 × 1 regions or 3 × 3 regions.
8. The method of claim 6, wherein the regions are distributed along an X-axis direction, along a Y-axis direction, or along both the X-axis and the Y-axis directions.
9. The method for adjusting the common voltage of the LCD panel according to claim 6, wherein the sampling simulation in step S20 is sampling simulation.
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