CN111242834B - Fusion defogging circuit based on data multiplexing guide filtering and contrast stretching - Google Patents
Fusion defogging circuit based on data multiplexing guide filtering and contrast stretching Download PDFInfo
- Publication number
- CN111242834B CN111242834B CN202010031281.2A CN202010031281A CN111242834B CN 111242834 B CN111242834 B CN 111242834B CN 202010031281 A CN202010031281 A CN 202010031281A CN 111242834 B CN111242834 B CN 111242834B
- Authority
- CN
- China
- Prior art keywords
- module
- picture data
- filtering
- data
- column
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000001914 filtration Methods 0.000 title claims abstract description 71
- 230000004927 fusion Effects 0.000 title claims abstract description 26
- 238000012545 processing Methods 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims description 22
- 238000010606 normalization Methods 0.000 claims description 10
- 238000003491 array Methods 0.000 claims description 6
- 238000007499 fusion processing Methods 0.000 claims description 3
- 238000012216 screening Methods 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 5
- 238000004364 calculation method Methods 0.000 description 12
- 238000010586 diagram Methods 0.000 description 4
- 238000012935 Averaging Methods 0.000 description 2
- 101100204393 Arabidopsis thaliana SUMO2 gene Proteins 0.000 description 1
- 101150112492 SUM-1 gene Proteins 0.000 description 1
- 101150096255 SUMO1 gene Proteins 0.000 description 1
- 101100311460 Schizosaccharomyces pombe (strain 972 / ATCC 24843) sum2 gene Proteins 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 125000001475 halogen functional group Chemical group 0.000 description 1
- 238000012880 independent component analysis Methods 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 230000002123 temporal effect Effects 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
- 230000003442 weekly effect Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T1/00—General purpose image data processing
- G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T1/00—General purpose image data processing
- G06T1/60—Memory management
-
- G06T5/73—
-
- G06T5/90—
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T2207/00—Indexing scheme for image analysis or image enhancement
- G06T2207/10—Image acquisition modality
- G06T2207/10016—Video; Image sequence
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T2207/00—Indexing scheme for image analysis or image enhancement
- G06T2207/20—Special algorithmic details
- G06T2207/20024—Filtering details
- G06T2207/20032—Median filtering
Abstract
The invention discloses a fusion defogging circuit based on data multiplexing guide filtering and contrast stretching, which comprises: the device comprises an input RAM module, an output RAM module, a buffer, a shift register module, a guide filtering module, a boosting filtering module, a linear stretching module and an image fusion module; the input RAM module stores picture data and transmits the picture data to the buffer, the guide filtering module and the linear stretching module; the guide filtering module is used for guide filtering and obtaining smooth picture data, the buffer is used for transmitting the picture data to the boost filtering module, and the boost filtering module is used for performing pressure filtering processing and obtaining sharpened picture data; the linear stretching module calculates the image data after contrast stretching, the image fusion module fuses the image data after contrast stretching and the sharpened image data to obtain the image data after defogging and sends the image data back to the output RAM module. The invention can realize high-speed real-time defogging of any image, improve defogging speed and effect and reduce resource occupation.
Description
Technical Field
The invention belongs to the technical field of video image defogging processing, and particularly relates to a video image processing defogging circuit applied to intelligent driving, video monitoring and medical scenes.
Background
In the field of video images, fog can cause the image processing effect to be greatly reduced, and the requirements of some key scenes cannot be met; in the current very popular automatic driving field, pictures and videos captured by an automobile electronic system are important basis for automobile self-decision, and if the videos captured by the automobile cannot be defogged in real time in a foggy day, the decision will be problematic, even more, accidents can be caused, and personal safety of drivers and passengers is seriously threatened. Meanwhile, in the medical field, medical equipment such as an endoscope and the like is inevitably influenced by the fog, and the operation of a doctor is difficult. Image defogging has a great influence on the development of various fields, so that designing a real-time defogging system is a very slow matter.
In recent years, through observation and statistics of images and making various assumptions or prior rules, the research of a single image defogging method has made a certain progress. For example, tan et al utilize the fact that fogless images have a higher contrast than foggy images to achieve single image defogging by maximizing the local contrast; fattal et al assume that the transmittance and the object surface shadow are locally uncorrelated, and utilize an independent component analysis method and a Markov random field model to achieve image defogging. He and the like improve a transmissivity graph by using a soft matting technology to realize restoration of an image based on dark channel prior knowledge and an atmosphere degradation model. Through theoretical analysis, he et al use soft matting results in very high temporal and spatial complexity of the whole algorithm. The median filtering adopted by Tarel et al causes the restored image to generate halo effect at the edges where the depth of field changes abruptly. Ma et al propose a new idea of fused image selection. In the summary of defogging algorithm proposed by singh et al, the defogging algorithm proposed by Ma et al only stays in software modeling aspect, and no method is applied to an actual scene, and in the defogging algorithm, a large number of multiplication-division methods and data redundancy parts exist in the calculation of the first and second input images, so that a very large space is provided for optimization by a hardware method. And although the works of Liuhuajun and Weekly have only realized the hardware implementation of the limited contrast self-adaptive histogram equalization algorithm with poor defogging effect, they prove the possibility of real-time and hardware implementation of the defogging algorithm. The current defogging algorithm is based on a software model of an x86 architecture CPU, the performance of the x86 architecture CPU is strong and comprehensive, the energy consumption is very high, the characteristics are not required by the scenes, and therefore a low-power consumption real-time defogging accelerator is urgently required to be designed aiming at the scenes.
Disclosure of Invention
The invention aims to overcome the defects in the prior art, and provides a fusion defogging circuit based on data multiplexing oriented filtering and contrast stretching, so that high-speed real-time defogging of any image can be realized, the defogging speed and effect are improved, and the resource occupation is reduced.
The invention adopts the following technical scheme for solving the technical problems:
the invention relates to a fusion defogging circuit based on data multiplexing guide filtering and contrast stretching, which is characterized by comprising the following components in parts by weight: the device comprises an input RAM module, a defogging module and an output RAM module; wherein, the defogging module comprises: the device comprises a buffer, a shift register array, a guide filtering module, a boosting filtering module, a linear stretching module and an image fusion module; the shift register array is composed of K-1 shift registers, and each shift register is combined in a series connection mode, wherein K is the size of a filtering window;
the input RAM module comprises three channels, and transmits the stored image data with the size of M multiplied by N to the buffer through a first channel, the guide filtering module through a second channel and the linear stretching module through a third channel respectively; wherein M and N are positive integers;
the guiding filtering module performs guiding filtering processing on the received picture data to obtain smooth picture data I, transmits the smooth picture data I to the boosting filtering module, and simultaneously gives an enabling signal to the buffer;
after receiving the enabling signal of the guide filtering module, the buffer transmits the received picture data to the boosting filtering module;
the boost filtering module carries out boost filtering processing on the received smooth picture data I' and the picture data transmitted by the buffer to obtain sharpened picture data Q and then transmits the sharpened picture data Q to the output RAM module;
the linear stretching module performs gray level fusion on RGB three-channel values of the received image data to obtain a gray level image; screening the gray values in the gray-scale image to obtain the maximum gray value and the minimum gray value, calculating to obtain contrast-stretched image data, transmitting the contrast-stretched image data to the image fusion module, and simultaneously transmitting an enabling signal to the image fusion module;
and the image fusion module receives the picture data after the contrast stretching and the corresponding enabling signal, reads the sharpened picture data Q from the output RAM module, and carries out shift addition fusion processing on the sharpened picture data Q and the picture data after the contrast stretching to obtain the defogged picture data which are sent back to the output RAM module.
The fusion defogging circuit based on data multiplexing guided filtering and contrast stretching is also characterized in that the guided filtering module comprises: the device comprises three shift register arrays, two first-in first-out queues (FIFO), the shift register arrays, a square module, a variance normalization unit, four mean value modules, three adders and three multipliers;
the first shift register array and the first-in first-out queue FIFO respectively receive and store the picture data periodically;
the square module and the first average module respectively receive and process a row of picture data transmitted by the shift register array periodically to obtain a square value and a first average value correspondingly; storing the first average value by a second first-in first-out queue (FIFO);
the second mean value module processes the square value to obtain a second mean value;
the first multiplier calculates the first mean value to obtain a first multiplication result;
the first adder processes the first multiplication result and the second mean value to obtain a first addition result and transmits the first addition result to the variance normalization unit; calculating by the variance normalization unit to obtain a coefficient a, and storing the coefficient a in a second shift register array;
the second adder calculates the coefficient a and the integer '1' to obtain a second addition result;
the second multiplier calculates the second addition result and the first average value to obtain a coefficient b, and then the coefficient b is stored in a third shift register array;
the third mean value module processes the coefficient b to obtain a mean value
The fourth mean module processes the coefficient a to obtain a mean value
A third multiplier for the average value
Calculating the image data to obtain a third multiplication result;
the third adder is used for the average value
And calculating the third multiplication result to obtain smooth picture data I.
The mean module in the guided filtering module comprises: the system comprises an addition tree, a row counter, a column counter, a coefficient lookup table, a data multiplexing unit, a result storage unit, a column and storage array, an array controller, two adders and a multiplier;
making the size of the mean filtering window K multiplied by K;
the addition tree reads K pixel values from the shift register array in sequence, adds the K pixel values to obtain a current column and Si, and then transmits the current column and Si to a fourth adder, a column and a storage array respectively;
after the column and storage array receives a write address signal sent by the array controller, the current column and Si are stored in corresponding storage units;
the fourth adder calculates the current column SUM Si and the last addition result SUM _ i-1 to obtain a current addition result SUM _ i, and sends the current addition result SUM _ i to the data multiplexing unit or the result storage unit under the control of the summation controller; let SUM _ i-1 be "0" when i = 1; if the number of rows read by the addition tree is less than K, the summation controller generates a low level signal, so that the current addition result SUM _ i is transmitted to the data multiplexing unit; if the number of rows read by the addition tree is more than or equal to K, the summation controller generates a high level signal, so that the current addition result SUM _ i is transmitted to the result storage unit;
the fourth adder receives a last addition result SUM _ i-1 of the result storage unit or the data multiplexing unit under the control of the SUM controller; if the number of rows read by the addition tree is less than K, the summation controller generates a low level signal, so that the data multiplexing unit transfers the stored last addition result SUM _ i-1 to the fourth adder; if the number of rows read by the addition tree is greater than or equal to K, the summation controller generates a high level signal, so that the result storage unit transfers the stored last addition result SUM _ i-1 to the fourth adder;
after the row and storage array receives a read address signal sent by the array controller, a fifth adder reads a current row and Si from the row and storage array and calculates the current row and Si with a current addition result SUM _ i in the result storage unit to obtain a current fifth addition result SUM5_ i;
the row counter is used for counting the data reading times in the addition tree shift register array, and when the row count value reaches M-1, the row counter is cleared; the column counter increments by "1";
when the column count value reaches N-1, clearing the column counter; the mean module finishes M multiplied by N data processing;
the decoder decodes the addresses corresponding to the row number and the column number transmitted from the row counter and the column counter and transmits the decoded addresses to the coefficient lookup table; and obtaining the coefficients at the corresponding positions by the coefficient lookup table, and then transmitting the coefficients to a fourth multiplier for calculating with the current fifth addition result SUM5_ i to obtain an average value.
Compared with the prior art, the invention has the beneficial effects that:
1. according to the invention, a contrast linear stretching mode is adopted in the linear stretching module, compared with the traditional linear stretching serialization, the maximum value and the minimum value of each channel are respectively screened out for the R, G and B channels according to the sequence, and then the linear stretching value of the pixel value is calculated by traversing each channel, so that a large amount of time is consumed.
2. The invention adopts a mode of dividing a box type filtering and averaging module in a guiding filtering module, pulls a shift register to an input end to be used as common, replaces a multiplier with an LUT (look up table), reduces the delay of averaging, improves the efficiency of squaring, and reduces the resource consumption of a traditional average calculating unit based on an adder by using a data multiplexing average calculating unit.
3. The invention uses the coefficient box type filtering module considering the edge condition in the guiding filtering module, so that the coefficient calculation is more accurate, the registers inserted in the path are reduced, and the calculation path is optimized.
Drawings
FIG. 1 is a block diagram of the integrated defogging circuit of the present invention;
FIG. 2 is a schematic diagram of a guided filtering module system according to the present invention;
FIG. 3 is a schematic diagram of a box filter module according to the present invention;
FIG. 4 is a schematic view of the overall frame of the linear stretching module of the present invention;
FIG. 5 is a comparative illustration of a linear stretching structure of the present invention;
FIG. 6 is a graph showing the comparison of linear stretching time according to the present invention.
Detailed Description
In this embodiment, a fused defogging circuit based on data multiplexing guided filtering and contrast stretching, as shown in fig. 1, includes: the system comprises an input RAM module, a defogging module and an output RAM module; wherein, defogging module includes: the device comprises a buffer, a shift register array, a guide filtering module, a boosting filtering module, a linear stretching module and an image fusion module; the shift register array is composed of K-1 shift registers, and each shift register is combined in a series connection mode, wherein K is the size of a filtering window;
the input RAM module comprises three channels, and the stored image data with the size of M multiplied by N is respectively transmitted to the buffer through the first channel, the guide filtering module through the second channel and the linear stretching module through the third channel; wherein M and N are positive integers; m =480, n =270 in this example, i.e. the size of the image is 480 × 270, the unit being a pixel;
the method comprises the steps that after a guiding filtering module carries out guiding filtering processing on received picture data, smooth picture data I are obtained and then are transmitted to a boosting filtering module, and meanwhile an enabling signal is transmitted to a buffer;
after receiving the enabling signal of the guide filtering module, the buffer transmits the received picture data to the boosting filtering module;
the boost filtering module performs boost filtering processing on the received smooth picture data I' and the picture data transmitted by the buffer to obtain sharpened picture data Q and then transmits the sharpened picture data Q to the output RAM module;
the linear stretching module carries out gray level fusion on RGB three-channel values of the received picture data to obtain a gray level picture; then, the gray values in the gray image are screened to obtain the maximum gray value and the minimum gray value, in this example, as shown in fig. 4, the gray channels are screened to select the maximum value and the minimum value, and then the maximum value and the minimum value are utilized
Subtracting the minimum value from the gray value to obtain the difference between the maximum value and the minimum value so as to obtain the image data after the contrast stretching, transmitting the image data after the contrast stretching obtained by calculation to the image fusion module, and simultaneously transmitting an enabling signal to the image fusion module; in the linear pullIn the overall block diagram of the extension module, R is respectively shifted to the left by 5 bits, 3 bits and 1 bit, and the value shifted to the left by 5 bits and the value shifted to the left by 3 bits are added and then subtracted by one bit; shifting G left by 6, 3 and 2 bits, adding the left shifted values and subtracting one; shifting B by 4 bits to the left to obtain a value minus one; finally, the values of R, G and B after the shift calculation are added to obtain a gray value;
as shown in fig. 5, in the conventional linear stretching serialization and parallelization, the maximum value and the minimum value of each channel are respectively screened out for the three channels R, G, and B according to the sequence, as shown in fig. 6, the conventional linear stretching structure is compared with the improved linear stretching structure, the conventional linear stretching serialization needs to traverse each channel to calculate the linear stretching value of each pixel value, that is, traverse 6 times successively, which consumes a lot of time, while the improved linear stretching shortens the linear stretching time, and the gray level calculation and the gray level channel adopt parallel calculation, so the time is reduced to a greater extent;
the image fusion module receives the image data after the contrast stretching and the corresponding enable signal, reads the sharpened image data Q from the output RAM module, in this example, in the fusion process, the output value Q of high boost is multiplied by the set parameter 0.4, the image data after the contrast stretching is multiplied by the set parameter 0.6, and the two products are added to obtain a fusion final value P, namely P = Q · 0.4+ l · 0.6, and the fusion final value P is transmitted to the output RAM. And shifting, adding and fusing the image data after the image data is stretched according to the contrast ratio to obtain defogged image data and sending the defogged image data back to the output RAM module.
In a specific implementation, the guided filtering module includes: the device comprises three shift register arrays, two first-in first-out queues (FIFO), the shift register arrays, a square module, a variance normalization unit, four mean value modules, three adders and three multipliers;
in the present example, as shown in fig. 2, the respective shift registers are named L0 to Li and are connected in series to be arranged in a shift register array; each shift register in the shift register array is combined together in a serial connection mode, the previous shift register is used as the input of the next shift register, the first shift register receives picture data from an input RAM module, the picture data are placed in a first storage unit and are sequentially shifted to the right under the action of shift pulses to be output to the next shift register, and after output enabling is received, the picture data in each shift register in the shift register array are parallelly sent to the guide filtering module;
the first shift register array and the first-in first-out queue FIFO respectively receive and store the image data periodically;
in the present example, as shown in fig. 2, the picture data in the first shift register array are respectively squared first and then averaged and then squared first;
the square module and the first average module respectively receive and process a row of picture data transmitted by the shift register array periodically to obtain a square value and a first average value correspondingly; storing the first average value by a second first-in first-out queue (FIFO);
the second mean value module processes the square value to obtain a second mean value;
the first multiplier calculates the first mean value to obtain a first multiplication result;
the first adder processes the first multiplication result and the second mean value to obtain a first addition result and transmits the first addition result to the variance normalization unit; in the present embodiment, the variance normalization unit is
The unit is used for calculating a coefficient a by the variance normalization unit and storing the coefficient a to the second shift register array;
the second adder calculates the coefficient a and the integer "1" to obtain a second addition result;
the second multiplier calculates the second addition result and the first average value to obtain a coefficient b, and then the coefficient b is stored in a third shift register array;
the third mean module processes the coefficient b to obtain a mean value
The fourth mean module processes the coefficient a to obtain a mean value
Third multiplier pair average
Calculating the sum of the current image and the image data to obtain a third multiplication result;
third adder pair average
And the third multiplication result is calculated to obtain smooth picture data I by the process of
In this embodiment, the mean module in the guided filtering module includes: the system comprises an addition tree, a row counter, a column counter, a coefficient lookup table, a data multiplexing unit, a result storage unit, a column and storage array, an array controller, two adders and a multiplier;
making the size of the mean filtering window K multiplied by K;
in a specific implementation, as shown in fig. 3, when the filtering enable is low, the data inside the shift register array is cleared, the row count and the column count are kept to be 0, the output of the coefficient lookup table is in an indeterminate state, and the output of the coefficient output module is in an indeterminate state; after the filtering start signal is pulled up, data starts to enter the shift register array, modules except the shift register array still do not work at the moment, the size of a filtering window is K multiplied by K, K pixels are output from the shift register array each time and are sent to the addition tree module, the value of K is set to be 8 in the example, and each 8 pixels are in a row;
the addition tree sequentially reads out K pixel values from the shift register array, adds the K pixel values to obtain a current column and Si, and then respectively transmits the current column and Si to a fourth adder, a column and a storage array; after receiving a write address signal sent by an array controller, the column and storage array stores the current column and Si in corresponding storage units; in this example, the K pixel values are added to obtain S0, and S1, S2, and S3.. Once again, the K pixel values are sequentially obtained according to the shift register, and then the K pixel values are respectively sent to the adder and the column and storage array to store the data,
a fourth adder calculates the current column, si, and the last addition result SUM _ i-1 to obtain a current addition result SUM _ i, in this example, i pixels of the obtained S0 and S1.. Multidot.si-1 and the added value SUM1 are respectively stored in a result and data multiplexing block, and when the next Si appears, the next SUM2= S1+. Multidot... Multidot.si-0 is calculated, and so on to obtain each addition result SUM; and sending the data to a data multiplexing unit or a result storage unit under the control of a summation controller; let SUM _ i-1 be "0" when i = 1; if the number of rows read by the addition tree is less than K, the summation controller generates a low level signal, so that the current addition result SUM _ i is transmitted to the data multiplexing unit; if the number of rows read by the addition tree is more than or equal to K, the summation controller generates a high level signal, so that the current addition result SUM _ i is transmitted to the result storage unit;
the fourth adder receives the last addition result SUM _ i-1 of the result storage unit or the data multiplexing unit under the control of the SUM controller; if the row number read by the addition tree is less than K, the summation controller generates a low level signal, so that the data multiplexing unit transmits the stored last addition result SUM _ i-1 to the fourth adder; if the number of lines read by the addition tree is more than or equal to K, the summation controller generates a high level signal, so that the result storage unit transmits the stored last addition result SUM _ i-1 to the fourth adder;
after the column and storage array receives a read address signal sent by the array controller, a fifth adder reads a current column and Si from the column and storage array and calculates with a current addition result SUM _ i in a result storage unit to obtain a current fifth addition result SUM5_ i;
the row counter is used for counting the times of reading the data in the shift register array by the addition tree, and when the row count value reaches M-1, the row counter is cleared; the column counter increments by "1";
when the column count value reaches N-1, clearing the column counter; the mean module finishes M multiplied by N data processing;
the decoder decodes the addresses corresponding to the row number and the column number transmitted from the row counter and the column counter and transmits the decoded addresses to the coefficient lookup table; and obtaining the coefficient at the corresponding position by the coefficient lookup table, and then transmitting the coefficient to a fourth multiplier for calculating with the current fifth addition result SUM5_ i to obtain an average value.
In this example, as shown in fig. 3, for example, when the (0, 0) pixel is located at the (5, 5) position of the filtering window, the row counter and the column counter start to operate, and at this time, the coefficient coding lookup table starts to output the current coefficient coding value, and the coefficient output module outputs the corresponding coefficient value according to the received coefficient coding value, the coefficient coding value is 0 and the coefficient value is 1/25, that is, 0.04, and when the coefficient calculation is completed, the coefficient value is sent to the multiplier to be multiplied by the obtained average value, so as to obtain the average value corresponding to the (0, 0) pixel. At this time, the row counter is M-2, the column counter is 0, the (M-2, 0) pixel is located at the (5, 5) position of the filter window, the coefficient code value is 2 and the coefficient value is 1/35, namely 0.028564453125, when the coefficient calculation is completed, the coefficient value is sent to the multiplier to be multiplied by the obtained mean value, and the mean value corresponding to the (M-2, 0) pixel is obtained. According to the calculation method, the average value filtering can be carried out on the whole image, and after the calculation is finished, the module can output a calculation finishing signal.
Claims (3)
1. A fusion defogging circuit based on data multiplexing guiding filtering and contrast stretching is characterized by comprising: the device comprises an input RAM module, a defogging module and an output RAM module; wherein, the defogging module includes: the device comprises a buffer, a shift register array, a guide filtering module, a boosting filtering module, a linear stretching module and an image fusion module; the shift register array is composed of K-1 shift registers, and each shift register is combined in a series connection mode, wherein K is the size of a filtering window;
the input RAM module comprises three channels, and transmits the stored image data with the size of M multiplied by N to the buffer through a first channel, the guide filtering module through a second channel and the linear stretching module through a third channel respectively; wherein M and N are positive integers;
the guiding filtering module performs guiding filtering processing on the received picture data to obtain smooth picture data I, transmits the smooth picture data I to the boosting filtering module, and simultaneously gives an enabling signal to the buffer;
after receiving the enabling signal of the guide filtering module, the buffer transmits the received picture data to the boosting filtering module;
the boost filtering module carries out boost filtering processing on the received smooth picture data I' and the picture data transmitted by the buffer to obtain sharpened picture data Q and then transmits the sharpened picture data Q to the output RAM module;
the linear stretching module performs gray level fusion on RGB three-channel values of the received image data to obtain a gray level image; screening the gray values in the gray-scale image to obtain the maximum gray value and the minimum gray value, calculating to obtain contrast-stretched image data, transmitting the contrast-stretched image data to the image fusion module, and simultaneously transmitting an enabling signal to the image fusion module;
and the image fusion module receives the picture data after the contrast stretching and the corresponding enabling signal, reads the sharpened picture data Q from the output RAM module, and carries out shift addition fusion processing on the sharpened picture data Q and the picture data after the contrast stretching to obtain the defogged picture data and sends the defogged picture data back to the output RAM module.
2. The fused defogging circuit based on data multiplexing guided filtering and contrast stretching according to claim 1, wherein said guided filtering module comprises: the device comprises three shift register arrays, two first-in first-out queues (FIFO), the shift register arrays, a square module, a variance normalization unit, four mean value modules, three adders and three multipliers;
the first shift register array and the first-in first-out queue FIFO respectively receive and store the picture data periodically;
the square module and the first average module respectively receive and process a row of picture data transmitted by the shift register array periodically to obtain a square value and a first average value correspondingly; storing the first mean value by a second first-in first-out queue (FIFO);
a second mean value module processes the square value to obtain a second mean value;
the first multiplier calculates the first mean value to obtain a first multiplication result;
the first adder processes the first multiplication result and the second mean value to obtain a first addition result and transmits the first addition result to the variance normalization unit; calculating by the variance normalization unit to obtain a coefficient a, and storing the coefficient a in a second shift register array;
the second adder calculates the coefficient a and the integer '1' to obtain a second addition result;
the second multiplier calculates the second addition result and the first mean value to obtain a coefficient b, and then stores the coefficient b in a third shift register array;
the third average value module processes the coefficient b to obtain an average value
；
The fourth mean module processes the coefficient a to obtain a mean value
；
Third multiplier pair said average value
Calculating the image data to obtain a third multiplication result;
the third adder adds the average value
And the third multiplication result is calculated, so that smooth picture data I are obtained.
3. The fused defogging circuit according to claim 2, wherein said mean module of said guided filtering modules comprises: the system comprises an addition tree, a row counter, a column counter, a coefficient lookup table, a data multiplexing unit, a result storage unit, a column and storage array, an array controller, two adders and a multiplier;
making the size of the mean filtering window K multiplied by K;
the addition tree sequentially reads K pixel values from the shift register array, adds the K pixel values to obtain a current column and Si, and then respectively transmits the current column and Si to a fourth adder, a column and a storage array;
after the column and storage array receives a write address signal sent by the array controller, the current column and Si are stored in corresponding storage units;
the fourth adder calculates the current column SUM Si and the last addition result SUM _ i-1 to obtain a current addition result SUM _ i, and sends the current addition result SUM _ i to the data multiplexing unit or the result storage unit under the control of the summation controller; let SUM _ i-1 be "0" when i = 1; if the number of rows read by the addition tree is less than K, generating a low level signal by a summation controller, and transmitting the current addition result SUM _ i to the data multiplexing unit; if the number of rows read by the addition tree is more than or equal to K, the summation controller generates a high level signal, so that the current addition result SUM _ i is transmitted to the result storage unit;
the fourth adder receives a last addition result SUM _ i-1 of the result storage unit or the data multiplexing unit under the control of the SUM controller; if the number of rows read by the addition tree is less than K, the summation controller generates a low level signal, so that the data multiplexing unit transfers the stored last addition result SUM _ i-1 to the fourth adder; if the number of rows read by the addition tree is greater than or equal to K, the summation controller generates a high level signal, so that the result storage unit transfers the stored last addition result SUM _ i-1 to the fourth adder;
after the column and storage array receives a read address signal sent by the array controller, a fifth adder reads a current column and Si from the column and storage array and calculates the current column and Si with a current addition result SUM _ i in the result storage unit to obtain a current fifth addition result SUM5_ i;
the row counter is used for counting the data reading times in the addition tree shift register array, and when the row count value reaches M-1, the row counter is cleared; the column counter increments "1";
when the column count value reaches N-1, clearing the column counter; the mean module finishes M multiplied by N data processing;
the decoder decodes the addresses corresponding to the row number and the column number transmitted from the row counter and the column counter and transmits the decoded addresses to the coefficient lookup table; and obtaining the coefficients at the corresponding positions by the coefficient lookup table, and then transmitting the coefficients to a fourth multiplier for calculating with the current fifth addition result SUM5_ i to obtain an average value.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010031281.2A CN111242834B (en) | 2020-01-13 | 2020-01-13 | Fusion defogging circuit based on data multiplexing guide filtering and contrast stretching |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010031281.2A CN111242834B (en) | 2020-01-13 | 2020-01-13 | Fusion defogging circuit based on data multiplexing guide filtering and contrast stretching |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111242834A CN111242834A (en) | 2020-06-05 |
| CN111242834B true CN111242834B (en) | 2023-03-14 |
Family
ID=70864038
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010031281.2A Active CN111242834B (en) | 2020-01-13 | 2020-01-13 | Fusion defogging circuit based on data multiplexing guide filtering and contrast stretching |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111242834B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104252698A (en) * | 2014-06-25 | 2014-12-31 | 西南科技大学 | Semi-inverse method-based rapid single image dehazing algorithm |
| CN107274362A (en) * | 2017-06-01 | 2017-10-20 | 西安电子科技大学 | Hardware realizes the optimization system and method for Steerable filter |
| CN110503615A (en) * | 2019-08-27 | 2019-11-26 | 合肥工业大学 | A kind of fusion defogging method based on variable step size Steerable filter and contrast stretching |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102968769B (en) * | 2012-11-27 | 2015-07-22 | 宁波盈芯信息科技有限公司 | Image consistency enhancing device |
-
2020
- 2020-01-13 CN CN202010031281.2A patent/CN111242834B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104252698A (en) * | 2014-06-25 | 2014-12-31 | 西南科技大学 | Semi-inverse method-based rapid single image dehazing algorithm |
| CN107274362A (en) * | 2017-06-01 | 2017-10-20 | 西安电子科技大学 | Hardware realizes the optimization system and method for Steerable filter |
| CN110503615A (en) * | 2019-08-27 | 2019-11-26 | 合肥工业大学 | A kind of fusion defogging method based on variable step size Steerable filter and contrast stretching |
Non-Patent Citations (1)
| Title |
|---|
| 基于导向滤波的暗通道去雾算法研究;陈尔言等;《科技展望》;20160210(第04期);全文 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111242834A (en) | 2020-06-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110544213B (en) | Image defogging method based on global and local feature fusion | |
| Zhang et al. | Hardware implementation for real-time haze removal | |
| US8295596B1 (en) | Adaptive histogram-based video contrast enhancement | |
| CN107274362B (en) | Optimization system and method for realizing oriented filtering by hardware | |
| CN111986084A (en) | Multi-camera low-illumination image quality enhancement method based on multi-task fusion | |
| CN112164011A (en) | Motion image deblurring method based on self-adaptive residual error and recursive cross attention | |
| CN109871790B (en) | Video decoloring method based on hybrid neural network model | |
| CN111242834B (en) | Fusion defogging circuit based on data multiplexing guide filtering and contrast stretching | |
| WO2007060498A1 (en) | Method and system for filtering image data | |
| CN111681192B (en) | Bit depth enhancement method for generating countermeasure network based on residual image condition | |
| CN115442613A (en) | Interframe information-based noise removal method using GAN | |
| CN113256506A (en) | Processing video frames via convolutional neural network using previous frame statistics | |
| CN115760640A (en) | Coal mine low-illumination image enhancement method based on noise-containing Retinex model | |
| CN115589455A (en) | Night video image enhancement system based on FPGA + ARM | |
| CN115511709A (en) | Self-adaptive super-resolution image sampling system | |
| CN115190294A (en) | Method and hardware system for realizing pixel value prediction | |
| CN110517183B (en) | High-speed low-power-consumption image processor based on retina mechanism | |
| CN106952243A (en) | UUV Layer Near The Sea Surface infrared image self adaptation merger histogram stretches Enhancement Method | |
| CN107071326A (en) | Method for processing video frequency and device | |
| CN114140450B (en) | Fusion defogging circuit based on parallel gray linear stretching and difference guiding filtering | |
| CN117011120A (en) | Self-adaptive guiding filtering defogging circuit based on edge marks | |
| CN117710246A (en) | Image defogging method and device | |
| CN115456903B (en) | Deep learning-based full-color night vision enhancement method and system | |
| Shibasaki et al. | Towards High-Quality Real-Time Video Denoising with Pseudo Temporal Fusion Network | |
| Xie et al. | High definition wide dynamic video surveillance system based on FPGA |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |