CN111240576A

CN111240576A - Computer system, memory management method, and non-transitory computer readable medium

Info

Publication number: CN111240576A
Application number: CN201811432424.XA
Authority: CN
Inventors: 陈羿逞; 赖彦辅; 王坤伟
Original assignee: Realtek Semiconductor Corp
Current assignee: Realtek Semiconductor Corp
Priority date: 2018-11-28
Filing date: 2018-11-28
Publication date: 2020-06-05

Abstract

The invention relates to a computer system, a memory management method and a non-transitory computer readable medium. The computer system operates on a system platform and comprises a plurality of memories and a controller circuit. The plurality of memories comprise a first memory and a second memory, wherein the first memory comprises a first storage space and a second storage space, and the total storage space of the second memory is the same as the first storage space. The memories are coupled in parallel to the controller circuit, and the controller circuit is configured to allocate at least a first data area to the first storage space and the second memory, and allocate a second data area to the second storage space based on a kernel of the system platform. A data access frequency of the second data area is lower than a data access frequency of the at least one first data area.

Description

Computer system, memory management method, and non-transitory computer readable medium

Technical Field

The present disclosure relates to a computer system and a memory management method, and more particularly, to a computer system, a memory management method and a non-transitory computer readable medium applied to an asymmetric memory space.

Background

Electronic devices for video and audio applications often use a memory to store image processing data. However, when there is an asymmetric storage space in the memory, the transmission bandwidth of the system is also limited. Thus, the performance of the electronic device is degraded and the user experience is reduced.

Disclosure of Invention

To solve the above problems, some embodiments of the present invention provide a computer system, which operates on a system platform and includes a plurality of memories and a controller circuit. The plurality of memories comprise a first memory and a second memory, wherein the first memory comprises a first storage space and a second storage space, and the total storage space of the second memory is the same as the first storage space. The memories are coupled in parallel to the controller circuit, and the controller circuit is configured to allocate at least a first data area to the first storage space and the second memory and allocate a second data area to the second storage space based on a kernel of the system platform. A data access frequency of the second data area is lower than a data access frequency of the at least one first data area.

Some embodiments of the present disclosure provide a memory management method, comprising: configuring at least one first data area to a first storage space of a first memory and a second memory based on a kernel of a system platform, wherein the total storage space of the second memory is the same as the first storage space; and configuring a second data area to a second storage space of the first memory based on the core, wherein a data access frequency of the second data area is lower than a data access frequency of the at least one first data area.

Some embodiments of the present disclosure provide a non-transitory computer readable medium having a computer program, wherein the computer program, when executed by a processor, causes the processor to perform operations, and the operations comprise: configuring at least one first data area to a first storage space of a first memory and a second memory based on a kernel of a system platform, wherein the total storage space of the second memory is the same as the first storage space; and configuring a second data area to a second storage space of the first memory based on the core, wherein a data access frequency of the second data area is lower than a data access frequency of the at least one first data area.

In summary, the computer system, the memory management method and the non-transitory computer readable medium according to the embodiments of the present disclosure can consider both the performance of the transmission bandwidth and the effective utilization of the storage space to reduce the influence of the asymmetric storage space.

Drawings

The attached drawings of the scheme are as follows:

FIG. 1 is a schematic diagram of a computer system according to some embodiments of the disclosure;

FIG. 2 is a flow chart of a method of memory management according to some embodiments of the disclosure; and

FIG. 3 is a diagram illustrating an arrangement of the memory of FIG. 1 according to some embodiments of the disclosure.

Detailed Description

All terms used herein have their ordinary meaning. The above definitions of words and phrases are generally used in dictionary, and any use of the word and phrase herein is meant to be included within the context of this disclosure by way of example only and should not be taken as limiting the scope or meaning of the present disclosure. Likewise, the present disclosure is not limited to the various embodiments shown in this specification.

It will be understood that the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections. These elements, components, regions, layers and/or regions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. As used herein, "and/or" includes any and all combinations of one or more of the associated items.

As used herein, coupled or connected means that two or more elements are in direct or indirect physical or electrical contact with each other, and that two or more elements are in operation or act with each other.

As used herein, the term "circuit system" generally refers to a single system comprising one or more circuits (circuits). The term "circuit" broadly refers to an object that is connected in some manner by one or more transistors and/or one or more active and passive elements to process signals.

Referring to fig. 1, fig. 1 is a schematic diagram of a computer system 100 according to some embodiments of the disclosure. In some embodiments, the computer system 100 may be an embedded system. For example, the computer system 100 can be applied to a circuit system (e.g., a display card) for video and audio related applications, but the disclosure is not limited thereto.

In some embodiments, the computer system 100 may be coupled to one or more components or functional units (e.g., processors, registers, etc.) within a system platform 100A, and configure the relevant components of the computer system 100 according to the relevant rules of the Kernel (Kernel) of the system platform 100A.

In some embodiments, the computer system 100 includes a controller circuit 120 and a plurality of

memories

140 and 142. A plurality of

memories

140 and 142 are coupled in parallel to the controller circuit 120. The controller circuit 120 is used for controlling the access operations of the

memories

140 and 142. In some embodiments, the

memories

140 and 142 are dynamic random access memories. In some embodiments, the

memories

140 and 142 are Double Data Rate (DDR) memories or static random access memories. In some embodiments, the controller circuit 120 may be a digital signal processing circuit, a processor, a control chip, or the like.

As shown in fig. 1, the memory 140 includes a storage space R11 and a storage space R12, and the total storage space R2 of the memory 142 is the same as the storage space R11. In other words, the data capacities of the memory 140 and the memory 142 are asymmetrical to each other. In this example, the data capacity of memory 142 is less than the data capacity of memory 140. For example, the total storage space of the memory 140 (i.e., the sum of the storage spaces R11 and R12) is 1 Gigabyte (GB), and the total storage space R2 of the memory 142 is 512 Megabytes (MB), wherein the storage spaces R11 and R12 are each 512 MB.

In some embodiments, the transmission bandwidth between the controller circuit 120 and each of the

memories

140 and 142 is the same. For example, the transmission bandwidth of the controller circuit 120 to each of the

memories

140 and 142 may be 16 bits. In some embodiments, the transmission bandwidth supported by the system platform 100A of the computer system 100 may be 32 bits. Under this condition, the controller circuit 120 can simultaneously access the data in the storage space R11 and the total storage space R2. Thus, the computer system 100 can simultaneously access data in the two

memories

140 and 142 to achieve higher operation performance.

In some related technologies, if data in an asymmetric memory region (e.g., the storage space R12) is to be accessed, the transmission bandwidth of the system as a whole is reduced to half (e.g., to 16 bits). In these cases, the system may increase additional data latency and reduce overall operating performance due to reduced transmission bandwidth.

In contrast to the related art, in some embodiments, the controller circuit 120 may perform related operations in the memory management method 200 of fig. 2 described below to configure the

memories

140 and 142 based on the management rules of the system platform 100A. Thus, the influence of the asymmetric data space on the computer system 100 can be reduced, thereby improving the overall operation performance.

Referring to fig. 2 and 3 together, fig. 2 is a flowchart illustrating a memory management method 200 according to some embodiments of the disclosure, and fig. 3 is a schematic diagram illustrating an arrangement of the

memories

140 and 142 in fig. 1 according to some embodiments of the disclosure. For ease of understanding, the following description will refer collectively to computer system 100 of FIG. 1.

In operation S210, at least one data area 310 is allocated to the storage space R11 and the memory 142 based on a kernel of the system platform 100A.

In operation S220, the data area 320 is configured to the storage space R12 based on a core of the system platform 100A, wherein a data access frequency of the data area 320 is lower than a data access frequency of the at least one data area 310.

In some embodiments, the system platform 100A is a Linux operating system. In these embodiments, as shown in fig. 3, based on the memory management rule of the Linux system kernel, the at least one data area 310 may include at least one of a Normal (Normal) data area Normal, a high-end (HighMem) data area HighMem, and/or a removable (Movable) data area movables. The Normal data area Normal can be used for storing data such as drivers related to the system kernel. The high-end data area highMem and the Movable data area Movable can be used for storing general data by a user. Under this condition, as shown in FIG. 3, the controller circuit 120 can allocate the Normal data area Normal, the high-side data area highMem and the removable data area Movable to the storage space R11 and the total storage space R2 (i.e. the memory 142) based on the memory management rule. In some embodiments, the controller circuit 120 may map at least one data region 310 to corresponding addresses of the

memories

140 and 142.

For example, as shown in FIG. 3, the transmission bandwidth of the memory region from address 0x0 to address 0x40000000 is 32 bits, and the memory region corresponds to the storage space R11 and the total storage space R2 of FIG. 1. The transmission bandwidth of the memory region from address 0x40000000 to address 0x60000000 is 16 bits, and the memory region corresponds to the storage space R12 of fig. 1. In some embodiments, controller circuit 120 configures Normal data area Normal, high data area HighMem, and removable data area Movable into a memory area with a transmission bandwidth of 32 bits.

Furthermore, in some embodiments, the controller circuit 120 may map the data area 320 to a corresponding address of the memory 140. Thus, the controller circuit 120 can allocate the data area 320 in the memory area with the transmission bandwidth of 16 bits. In some embodiments, the data access frequency of the data area 320 is lower than the data access frequency of the at least one data area 310. In some embodiments, the data area 320 is accessed for a shorter time each time than the at least one data area 310 is accessed for each time.

In some embodiments, the data area 320 is used for storing data of related applications with low memory bandwidth requirements. In some embodiments, the data area 320 is not used for storing the related data processed by the video decoder, such as video data, audio data, user interface, and the like. In some embodiments, the data area 320 is not used to store hardware-generated data for high-frame-per-second (FPS) image data. In some embodiments, the high FPS may be at least 60 FPS.

For example, as shown in FIG. 3, in an embodiment where system platform 100A is a Linux operating system, data area 320 may include a memory compressed (zRAM) data area zRAM. The memory compressed data area zRAM is used for storing compressed data, wherein the data are data which are not accessed for a long time. With the above arrangement, at least one data area 310 with higher data access frequency is allocated to a memory area with higher transmission bandwidth, and a data area 320 with relatively lower data access frequency is allocated to a memory area with lower transmission bandwidth. Compared with the related art, the performance of the memory region with lower transmission bandwidth can be reduced.

With reference to fig. 2, in operation S230, when a usage space of the at least one data area 310 is insufficient, the at least one data area 310 is extended to the memory 142.

In some embodiments, the controller circuit 120 may further extend the at least one data region 310 to the storage space R12 when the data amount of the data region 320 does not exhaust the storage space R12 and the usage space of the at least one data region 310 is insufficient.

For example, based on the memory management rule of the kernel of the Linux system, the memory allocation is backed (fallback) from the region with higher address to the region with lower address. For example, as shown in the reverse order S3-2, when the data capacity of the removable data area Movable is full, the controller circuit 120 requests the upper data area HighMem with the lower address to provide the available storage space. If the data capacity is still insufficient, controller circuit 120 further requests Normal, which is lower in address, to provide usable storage space, as shown in reverse sequence S3-1.

If the data capacity is still insufficient, as shown in the reverse sequence S3-3, the controller circuit 120 will instead require the memory 142 to provide usable storage space. In this case, if the storage space R12 is not occupied by the data amount of the memory compressed data zone zRAM, a part of the storage space R12 can be allocated to at least one data zone 310. Equivalently, the controller circuit 120 extends the space of the at least one data area 310 to the storage space R12.

With this arrangement, it is ensured that the storage space of the

memories

140 and 142 can be fully utilized, and at the same time, the transmission bandwidth can be efficiently used to ensure the overall system performance.

In some embodiments, the at least one data area 310 may be a plurality of storage blocks (not shown) in the memory 140, and the data area 320 may be a plurality of storage blocks (not shown) in the memory 142. In some embodiments, the storage blocks may be memory blocks, pages, and the like.

The above description of the Linux operating system and various types of data areas is used for illustration, and the disclosure is not limited thereto. Various applicable operating systems and various types of data areas are all covered by the present disclosure.

The steps of the memory management method 200 are merely exemplary and are not limited to the above-described exemplary sequential execution. Various operations under the memory management method 200 may be added, substituted, omitted, or performed in a different order, as appropriate, without departing from the manner of operation and scope of various embodiments of the disclosure.

In various embodiments, the implementation of the controller circuit 120 or the memory management method 200 may be software, hardware, and/or firmware. For example, each circuit or unit in the controller circuit 120 may be integrated into a single integrated circuit. In some embodiments, the memory management method 200 can be implemented by software or computer programs having corresponding instructions and stored in a non-transitory computer readable medium for a processor to perform the above-mentioned operations. Alternatively, the controller circuit 120 may be implemented by a digital signal processing circuit that performs the memory management method 200. In other embodiments, each circuit or unit in the controller circuit 120 may also be implemented by software, hardware and firmware. In various embodiments, the specific implementation of the controller circuit 120 and/or the memory management method 200 may be selected according to actual requirements.

In some embodiments, the aforementioned non-transitory computer readable medium may comprise an electronic, magnetic, optical, infrared, and/or semiconductor system (or apparatus or device). For example, it may be a semiconductor or solid state memory, magnetic tape, a removable computer diskette, a Random Access Memory (RAM), a read-only memory (ROM), a rigid magnetic disk and/or an optical magnetic disk. In one or more embodiments using optical disks, the non-transitory computer-readable medium includes compact disk read only memories (CD-ROMs), compact disk rewritables (CD-Rs/Ws), and/or Digital Video Disks (DVDs).

Although the present disclosure has been described with reference to particular embodiments, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the disclosure, and therefore, the scope of the disclosure should be limited only by the terms of the appended claims.

[ notation ] to show

100: computer system

140. 142: memory device

R11, R12: storage space

200: memory management method

S230: operation of

HighMem: high-end data area

zRAM: compressed data area of memory

0x 40000000: address of

S3-3: reverse order

310. 320, and (3) respectively: the data area 120: controller circuit

100A: system platform

R2: total storage space

S210 and S220: operation of

Normal: general data area

Mocable: movable data area

0x 0: address of

0x 60000000: addresses S3-1, S3-2: the sequence is reversed.

Claims

1. A computer system operating on a system platform, the computer system comprising:

a plurality of memories including a first memory and a second memory, wherein the first memory includes a first storage space and a second storage space, and the total storage space of the second memory is the same as the first storage space; and

a controller circuit, wherein the memories are coupled to the controller circuit in parallel, and the controller circuit is configured to allocate at least a first data area to the first storage space and the second memory and a second data area to the second storage space based on a kernel of the system platform,

wherein a data access frequency of the second data area is lower than a data access frequency of the at least one first data area.

2. The computer system as recited in claim 1, wherein the controller circuit is further configured to extend the at least one first data area to the second storage space when a data capacity of the at least one first data area is insufficient.

3. The computer system as recited in claim 2, wherein the controller circuit is further configured to request the second memory to provide a usable storage space to the at least one first data area to extend the at least one first data area to the second storage space when the data capacity of the at least one first data area is insufficient.

4. The computer system according to claim 1, wherein the at least one first data area comprises at least one of a normal data area, a high-end data area or a removable data area when the system platform is a Linux operating system.

5. The computer system as claimed in claim 1, wherein the second data area comprises a memory compressed data area when the system platform is a Linux operating system.

6. A memory management method, comprising:

configuring at least one first data area to a first storage space of a first memory and a second memory based on a kernel of a system platform, wherein the total storage space of the second memory is the same as the first storage space; and

and allocating a second data area to a second storage space of the first memory based on the core, wherein a data access frequency of the second data area is lower than a data access frequency of the at least one first data area.

7. The memory management method of claim 6, further comprising:

when the data capacity of the at least one first data area is insufficient, the at least one first data area is extended to the second storage space.

8. The method of claim 7, wherein extending the at least one first data region to the second storage space comprises:

when the data capacity of the at least one first data area is insufficient, the second memory is required to provide a usable storage space to the at least one first data area so as to extend the at least one first data area to the second storage space.

9. The memory management method according to claim 6, wherein the second data area comprises a compressed data area of memory when the system platform is a Linux operating system.

10. A non-transitory computer readable medium having a computer program, wherein the computer program, when executed by a processor, causes the processor to perform operations comprising: