CN111240124A - SWAP gate based on graphene surface plasmon polaritons - Google Patents

SWAP gate based on graphene surface plasmon polaritons Download PDF

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CN111240124A
CN111240124A CN202010057246.8A CN202010057246A CN111240124A CN 111240124 A CN111240124 A CN 111240124A CN 202010057246 A CN202010057246 A CN 202010057246A CN 111240124 A CN111240124 A CN 111240124A
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waveguide
middle layer
arc
straight
annular
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CN111240124B (en
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陈伟伟
丁健
汪鹏君
李燕
李军
虞若兰
杨建义
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Ningbo University
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F3/00—Optical logic elements; Optical bistable devices
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B6/122—Basic optical elements, e.g. light-guiding paths
    • G02B6/1226—Basic optical elements, e.g. light-guiding paths involving surface plasmon interaction
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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Abstract

The invention discloses a graphene-based SWAP gate for surface plasmons, which comprises a substrate, a buffer layer, a first straight waveguide, a second straight waveguide, a third straight waveguide, a first arc waveguide, a second arc waveguide, a third arc waveguide, a fourth arc waveguide, a first micro-ring resonant cavity, a second micro-ring resonant cavity, a third micro-ring resonant cavity and a fourth micro-ring resonant cavity, wherein the four micro-ring resonant cavities form a cascade structure, the structure is simple and compact, and the first straight waveguide, the second straight waveguide, the third straight waveguide, the first micro-ring resonant cavity, the second micro-ring resonant cavity, the third micro-ring resonant cavity, the fourth micro-ring resonant cavity, the first arc waveguide, the second arc waveguide, the third arc waveguide and the fourth arc waveguide are mutually matched in structure, so that the propagation condition of graphene surface plasmons is met; the advantage is that through graphite alkene surface plasmon realization SWAP gate function, the size is less, and compact structure nature is strong, does benefit to the piece and integrates.

Description

SWAP gate based on graphene surface plasmon polaritons
Technical Field
The invention relates to a SWAP gate, in particular to a SWAP gate based on graphene surface plasmon polariton.
Background
With the continuous development of information science and technology, the integration level of computer chips is rapidly increased at a speed of doubling a year and a half. However, as the line width of integrated circuits continues to decrease to some extent, there arises a problem that moore's law goes away. Moreover, conventional boolean computers composed of Field Effect Transistors (FETs) are based on irreversible logic operations. Landauer has described that for conventional irreversible logic computation, each bit of information loss factor results in ktln2Joule heating energy (where k is the Boltzmann constant and t is the absolute temperature). Although the power generated by the loss of one bit of information is small, with the increasing integration of the chip, the power generated by the chip when processing a large amount of data is quite large, thereby causing a serious heat dissipation problem.
It is in consideration of the above two problems that the quantum reversible logic research based on quantum computation attracts more and more students. The quantum reversible logic scheme can realize a one-to-one mapping function, and the input signals are identified from the corresponding output signals, which means that a unique output signal can be judged from each input signal, and each output signal can also track a unique input signal. This one-to-one mapping function makes it possible to recover the input from the output without consuming energy and without information loss. Therefore, quantum reversible logic does not erase any information while avoiding heat dissipation, which is very important for future high-speed information processing.
In recent years, a large number of quantum reversible logic circuits have been proposed. The SWAP gate is used as a common reversible logic gate and has wide application prospect in chip design. At present, the experimental device consisting of three Mach-Zehnder interferometers, a certain number of beam splitters, polarization rotators and detectors has realized the function of a SWAP gate, but the device has a complex structure and a large volume, is difficult to integrate on a chip, and is limited in use.
Disclosure of Invention
The invention aims to solve the technical problem of providing the SWAP gate which is smaller in size, high in structure compactness and beneficial to on-chip integration and is based on the graphene surface plasmon polariton.
The technical scheme adopted by the invention for solving the technical problems is as follows: a SWAP gate based on graphene surface plasmons comprises a substrate, a buffer layer, a first straight waveguide, a second straight waveguide, a third straight waveguide, a first arc-shaped waveguide, a second arc-shaped waveguide, a third arc-shaped waveguide, a fourth arc-shaped waveguide, a first micro-ring resonant cavity, a second micro-ring resonant cavity, a third micro-ring resonant cavity and a fourth micro-ring resonant cavity; the substrate and the buffer layer are both in a cuboid structure, the size of the long edge of the base body is equal to that of the long edge of the buffer layer, the size of the wide edge of the substrate is equal to that of the wide edge of the buffer layer, and the buffer layer is paved on the substrate to completely cover the upper surface of the substrate; the long side direction of the buffer layer is taken as the left-right direction, and the wide side direction is taken as the front-back direction; the first straight waveguide, the second straight waveguide and the third straight waveguide are respectively tiled on the upper surface of the buffer layer, the first straight waveguide, the second straight waveguide and the third straight waveguide are respectively parallel to the long side of the buffer layer, the second straight waveguide is positioned on the front side of the first straight waveguide, the widths of the first straight waveguide, the second straight waveguide and the third straight waveguide are all 30nm, the length of the first straight waveguide is 100nm, the length of the second straight waveguide is 850nm, the length of the third straight waveguide is 850nm, the first micro-ring resonator, the second micro-ring resonator, the third micro-ring resonator and the fourth micro-ring resonator are respectively tiled on the upper surface of the buffer layer, and the first micro-ring resonator is positioned on the front side of the second straight waveguide, if the first micro-ring resonator is shifted backward by 20nm, the second straight waveguide will be tangent to the outer wall of the first micro-ring resonator, the second micro-ring resonator and the third micro-ring resonator are respectively located between the second straight waveguide and the third straight waveguide, and the second micro-ring resonator is located at the front side of the third micro-ring resonator, if the second micro-ring resonator is shifted forward by 2nm, the second straight waveguide will be tangent to the outer wall of the second micro-ring resonator, if the second micro-ring resonator is shifted backward by 4nm, the outer wall of the second micro-ring resonator will be tangent to the outer wall of the third micro-ring resonator, if the third micro-ring resonator is shifted backward by 2nm, the third straight waveguide will be tangent to the outer wall of the third micro-ring resonator, and the fourth micro-ring resonator is located at the rear side of the third straight waveguide, if the fourth micro-ring resonant cavity translates forward by 20nm, the third straight waveguide is tangent to the outer wall of the fourth micro-ring resonant cavity, the distance between the centers of the first micro-ring resonant cavity and the fourth micro-ring resonant cavity is 708nm, and the distance between the centers of the second micro-ring resonant cavity and the third micro-ring resonant cavity is 204 nm; the connecting line of the circle center of the first micro-ring resonant cavity and the circle center of the fourth micro-ring resonant cavity, and the connecting line of the circle center of the second micro-ring resonant cavity and the circle center of the third micro-ring resonant cavity are respectively parallel to the wide side of the buffer layer, the inner ring radius of the first micro-ring resonant cavity, the second micro-ring resonant cavity, the third micro-ring resonant cavity and the fourth micro-ring resonant cavity is 70nm, and the outer ring radius is 100 nm; the inner diameters of the first arc-shaped waveguide, the second arc-shaped waveguide, the third arc-shaped waveguide and the fourth arc-shaped waveguide are all 94.5nm, and the outer diameters are all 124.5 nm; the left end of the second straight waveguide is connected with the right end of the first arc waveguide, the rear end of the first arc waveguide is connected with the front end of the second arc waveguide, the left end of the second arc waveguide is connected with the right end of the first straight waveguide, the left end of the third arc waveguide is connected with the right end of the first straight waveguide, the rear end of the third arc waveguide is connected with the front end of the fourth arc waveguide, the right end of the fourth arc waveguide is connected with the left end of the third straight waveguide, the left end of the first straight waveguide is the input end of the SWAP gate, the right end of the second straight waveguide is the first output end of the SWAP gate, and the right end of the third straight waveguide is the second output end of the SWAP gate.
The first straight waveguide is formed by connecting a first bottom layer straight waveguide, a first middle layer straight waveguide, a second middle layer straight waveguide, a third middle layer straight waveguide, a fourth middle layer straight waveguide, a fifth middle layer straight waveguide and a first upper layer straight waveguide through a CMOS compatible process, the first bottom layer straight waveguide is made of silicon dioxide, the first bottom layer straight waveguide is 20nm thick and 30nm wide, the first middle layer straight waveguide and the second middle layer straight waveguide are made of silicon dioxide, the first middle layer straight waveguide and the second middle layer straight waveguide are both 18nm thick and 1nm wide, the third middle layer straight waveguide is made of graphene thick and 30nm wide, and the fourth middle layer straight waveguide and the fifth middle layer straight waveguide are both made of silicon dioxide, the thickness of the fourth middle layer straight waveguide and the width of the fifth middle layer straight waveguide are both 18nm and 1nm, the material of the first upper layer straight waveguide is silicon dioxide, the thickness of the first upper layer straight waveguide is 20nm and the width of the first upper layer straight waveguide is 30nm, the first bottom layer straight waveguide is positioned at the bottommost layer, the first middle layer straight waveguide and the second middle layer straight waveguide are parallelly arranged on the first bottom layer straight waveguide at intervals, the distance between the first middle layer straight waveguide and the second middle layer straight waveguide is 28nm, the third middle layer straight waveguide is arranged on the first middle layer straight waveguide and the second middle layer straight waveguide, the fourth middle layer straight waveguide and the fifth middle layer straight waveguide are parallelly arranged on the third middle layer straight waveguide at intervals, and the distance between the fourth middle layer straight waveguide and the fifth middle layer straight waveguide is 28nm, the first upper layer straight waveguide is arranged on the fourth middle layer straight waveguide and the fifth middle layer straight waveguide; the second straight waveguide is formed by connecting a second bottom layer straight waveguide, a sixth middle layer straight waveguide, a seventh middle layer straight waveguide, an eighth middle layer straight waveguide, a ninth middle layer straight waveguide, a tenth middle layer straight waveguide and a second upper layer straight waveguide through a CMOS compatible process, the second bottom layer straight waveguide is made of silicon dioxide, the second bottom layer straight waveguide is 20nm in thickness and 30nm in width, the sixth middle layer straight waveguide and the seventh middle layer straight waveguide are made of silicon dioxide, the sixth middle layer straight waveguide and the seventh middle layer straight waveguide are both 18nm in thickness and 1nm in width, the eighth middle layer straight waveguide is made of graphene, the eighth middle layer straight waveguide is 1nm in thickness and 30nm in width, and the ninth middle layer straight waveguide and the tenth middle layer straight waveguide are both made of silicon dioxide, the ninth middle layer straight waveguide and the tenth middle layer straight waveguide are 18nm in thickness and 1nm in width, the second upper layer straight waveguide is made of silicon dioxide, the second upper layer straight waveguide is 20nm in thickness and 30nm in width, the second bottom layer straight waveguide is positioned at the bottommost layer, the sixth middle layer straight waveguide and the seventh middle layer straight waveguide are parallelly arranged on the second bottom layer straight waveguide at intervals, the distance between the sixth middle layer straight waveguide and the seventh middle layer straight waveguide is 28nm, the eighth middle layer straight waveguide is arranged on the sixth middle layer straight waveguide and the seventh middle layer straight waveguide, the ninth middle layer straight waveguide and the tenth middle layer straight waveguide are parallelly arranged on the eighth middle layer straight waveguide at intervals, and the distance between the ninth middle layer straight waveguide and the tenth middle layer straight waveguide is 28nm, the second upper layer straight waveguide is arranged on the ninth middle layer straight waveguide and the tenth middle layer straight waveguide; the third straight waveguide is formed by connecting a third bottom layer straight waveguide, an eleventh middle layer straight waveguide, a twelfth middle layer straight waveguide, a thirteenth middle layer straight waveguide, a fourteenth middle layer straight waveguide, a fifteenth middle layer straight waveguide and a third upper layer straight waveguide through a CMOS compatible process, the third bottom layer straight waveguide is made of silicon dioxide, the third bottom layer straight waveguide is 20nm in thickness and 30nm in width, the eleventh middle layer straight waveguide and the twelfth middle layer straight waveguide are made of silicon dioxide, the eleventh middle layer straight waveguide and the twelfth middle layer straight waveguide are both 18nm in thickness and 1nm in width, the thirteenth middle layer straight waveguide is made of graphene, the thirteenth middle layer straight waveguide is 1nm in thickness and 30nm in width, and the fourteenth middle layer straight waveguide and the fifteenth middle layer straight waveguide are both made of silicon dioxide, the fourteenth middle layer straight waveguide and the fifteenth middle layer straight waveguide are 18nm in thickness and 1nm in width, the third upper layer straight waveguide is made of silicon dioxide, the third upper layer straight waveguide is 20nm in thickness and 30nm in width, the third bottom layer straight waveguide is positioned at the bottommost layer, the eleventh middle layer straight waveguide and the twelfth middle layer straight waveguide are parallelly arranged on the third bottom layer straight waveguide at intervals, the distance between the eleventh middle layer straight waveguide and the twelfth middle layer straight waveguide is 28nm, the thirteenth middle layer straight waveguide is arranged on the eleventh middle layer straight waveguide and the twelfth middle layer straight waveguide, the fourteenth middle layer straight waveguide and the fifteenth middle layer straight waveguide are parallelly arranged on the thirteenth middle layer straight waveguide at intervals, and the distance between the fourteenth straight waveguide and the fifteenth middle layer straight waveguide is 28nm, the third upper layer straight waveguide is arranged on the fourteenth middle layer straight waveguide and the fifteenth middle layer straight waveguide; the first arc waveguide is formed by connecting a first bottom layer arc waveguide, a first middle layer arc waveguide, a second middle layer arc waveguide, a third middle layer arc waveguide, a fourth middle layer arc waveguide, a fifth middle layer arc waveguide and a first upper layer arc waveguide through a CMOS compatible process, the radians of the first bottom layer arc waveguide, the first middle layer arc waveguide, the second middle layer arc waveguide, the third middle layer arc waveguide, the fourth middle layer arc waveguide, the fifth middle layer arc waveguide and the first upper layer arc waveguide are all 90 degrees, the first bottom layer arc waveguide is made of silicon dioxide, the thickness of the first bottom layer arc waveguide is 20nm, the inner diameter of the first bottom layer arc waveguide is 94.5nm, the outer diameter of the first bottom layer arc waveguide is 124.5nm, and the first middle layer arc waveguide and the second middle layer arc waveguide are both made of silicon dioxide, the thickness of the first middle layer arc waveguide and the second middle layer arc waveguide are both 18nm, the inner diameter of the first middle layer arc waveguide is 123.5nm, the outer diameter of the first middle layer arc waveguide is 124.5nm, the inner diameter of the second middle layer arc waveguide is 94.5nm, the outer diameter of the second middle layer arc waveguide is 95.5nm, the material of the third middle layer arc waveguide is graphene, the thickness of the third middle layer arc waveguide is 1nm, the inner diameter of the third middle layer arc waveguide is 94.5nm, the outer diameter of the third middle layer arc waveguide is 124.5nm, the material of the fourth middle layer arc waveguide and the material of the fifth middle layer arc waveguide are both silica, the thickness of the fourth middle layer arc waveguide and the thickness of the fifth middle layer arc waveguide are both 18nm, the inner diameter of the third middle layer arc waveguide is 123.5nm, the outer diameter of the third middle layer arc waveguide is 124.5nm, the inner diameter of the fourth middle layer arc waveguide is 94.5nm, the outer diameter of the fourth middle layer arc waveguide is 95.5nm, and the material of the first upper layer arc, the thickness of the first upper layer arc waveguide is 20nm, the inner diameter of the first upper layer arc waveguide is 94.5nm, the outer diameter of the first upper layer arc waveguide is 124.5nm, the circle centers of the first bottom layer arc waveguide, the first middle layer arc waveguide, the second middle layer arc waveguide, the third middle layer arc waveguide, the fourth middle layer arc waveguide, the fifth middle layer arc waveguide and the first upper layer arc waveguide are positioned on the same straight line, the first bottom layer arc waveguide is positioned on the bottommost layer, the first middle layer arc waveguide and the second middle layer arc waveguide are arranged on the first bottom layer arc waveguide in parallel at intervals, the first middle layer arc waveguide is concentrically arranged on the inner side of the second middle layer arc waveguide, and the third middle layer arc waveguide is arranged on the first middle layer arc waveguide and the second middle layer arc waveguide, the fourth middle layer arc waveguide and the fifth middle layer arc waveguide are arranged on the third middle layer arc waveguide at intervals in parallel, the fourth middle layer arc waveguide is concentrically arranged on the inner side of the fifth middle layer arc waveguide, and the first upper layer arc waveguide is arranged on the fourth middle layer arc waveguide and the fifth middle layer arc waveguide; the second arc waveguide is formed by connecting a second bottom layer arc waveguide, a sixth middle layer arc waveguide, a seventh middle layer arc waveguide, an eighth middle layer arc waveguide, a ninth middle layer arc waveguide, a tenth middle layer arc waveguide and a second upper layer arc waveguide through a CMOS compatible process, the radians of the second bottom layer arc waveguide, the sixth middle layer arc waveguide, the seventh middle layer arc waveguide, the eighth middle layer arc waveguide, the ninth middle layer arc waveguide, the tenth middle layer arc waveguide and the second upper layer arc waveguide are all 90 degrees, the second bottom layer arc waveguide is made of silicon dioxide, the thickness of the second bottom layer arc waveguide is 20n, the inner diameter of the second bottom layer arc waveguide is 94.5nm, the outer diameter of the second bottom layer arc waveguide is 124.5nm, and the materials of the sixth middle layer arc waveguide and the seventh middle layer arc waveguide are both silicon dioxide, the thickness of the sixth middle layer arc waveguide and the thickness of the seventh middle layer arc waveguide are both 18nm, the inner diameter of the sixth middle layer arc waveguide is 123.5nm, the outer diameter of the sixth middle layer arc waveguide is 124.5nm, the inner diameter of the seventh middle layer arc waveguide is 94.5nm, the outer diameter of the seventh middle layer arc waveguide is 95.5nm, the material of the eighth middle layer arc waveguide is graphene, the thickness of the eighth middle layer arc waveguide is 1nm, the inner diameter of the eighth middle layer arc waveguide is 94.5nm, the outer diameter of the eighth middle layer arc waveguide is 124.5nm, the material of the ninth middle layer arc waveguide and the tenth middle layer arc waveguide are both silica, the thickness of the ninth middle layer arc waveguide and the tenth middle layer arc waveguide are both 18nm, the inner diameter of the eighth middle layer arc waveguide is 123.5nm, the outer diameter of the eighth middle layer arc waveguide is 124.5nm, the inner diameter of the ninth middle layer arc waveguide is 94.5nm, the outer diameter of the ninth middle layer arc waveguide is 95.5nm, and the material of the second upper layer arc waveguide is, the thickness of the second upper layer arc waveguide is 20nm, the inner diameter of the second upper layer arc waveguide is 94.5nm, the outer diameter of the second upper layer arc waveguide is 124.5nm, the circle centers of the second bottom layer arc waveguide, the sixth middle layer arc waveguide, the seventh middle layer arc waveguide, the eighth middle layer arc waveguide, the ninth middle layer arc waveguide, the tenth middle layer arc waveguide and the second upper layer arc waveguide are positioned on the same straight line, the second bottom layer arc waveguide is positioned on the bottommost layer, the sixth middle layer arc waveguide and the seventh middle layer arc waveguide are arranged on the second bottom layer arc waveguide in parallel at intervals, the sixth middle layer arc waveguide is concentrically arranged on the inner side of the seventh middle layer arc waveguide, and the eighth middle layer arc waveguide is arranged on the sixth middle layer arc waveguide and the seventh middle layer arc waveguide, the ninth middle layer arc waveguide and the tenth middle layer arc waveguide are arranged on the eighth middle layer arc waveguide at intervals in parallel, the ninth middle layer arc waveguide is concentrically arranged on the inner side of the tenth middle layer arc waveguide, and the second upper layer arc waveguide is arranged on the ninth middle layer arc waveguide and the tenth middle layer arc waveguide; the third arc waveguide is formed by connecting a third bottom layer arc waveguide, an eleventh middle layer arc waveguide, a twelfth middle layer arc waveguide, a thirteenth middle layer arc waveguide, a fourteenth middle layer arc waveguide, a fifteenth middle layer arc waveguide and a third upper layer arc waveguide through a CMOS compatible process, the radians of the third bottom layer arc waveguide, the eleventh middle layer arc waveguide, the twelfth middle layer arc waveguide, the thirteenth middle layer arc waveguide, the fourteenth middle layer arc waveguide, the fifteenth middle layer arc waveguide and the third upper layer arc waveguide are all 90 degrees, the third bottom layer arc waveguide is made of silicon dioxide, the thickness of the third bottom layer arc waveguide is 20n, the inner diameter of the third bottom layer arc waveguide is 94.5nm, the outer diameter of the third bottom layer arc waveguide is 124.5nm, the eleventh middle layer arc waveguide and the twelfth middle layer arc waveguide are made of silicon dioxide, the thickness of the eleventh middle layer arc waveguide and the thickness of the twelfth middle layer arc waveguide are both 18nm, the inner diameter of the eleventh middle layer arc waveguide is 123.5nm, the outer diameter of the eleventh middle layer arc waveguide is 124.5nm, the inner diameter of the twelfth middle layer arc waveguide is 94.5nm, the outer diameter of the twelfth middle layer arc waveguide is 95.5nm, the material of the thirteenth middle layer arc waveguide is graphene, the thickness of the thirteenth middle layer arc waveguide is 1nm, the inner diameter of the thirteenth middle layer arc waveguide is 94.5nm, the outer diameter of the thirteenth middle layer arc waveguide is 124.5nm, the material of the fourteenth middle layer arc waveguide and the material of the fifteenth middle layer arc waveguide are both silicon dioxide, the thickness of the fourteenth middle layer arc waveguide and the thickness of the fifteenth middle layer arc waveguide are both 18nm, the inner diameter of the thirteenth middle layer arc waveguide is 123.5nm, the outer diameter of the fourteenth middle layer arc waveguide is 124.5nm, the inner diameter of the fourteenth middle layer arc waveguide is 94.5nm, the outer diameter of the third upper layer arc waveguide is 95.5nm, the material of the third upper layer arc waveguide is silicon dioxide, the thickness of the third upper layer arc waveguide is 20nm, the inner diameter of the third upper layer arc waveguide is 94.5nm, the outer diameter of the third upper layer arc waveguide is 124.5nm, the centers of the third bottom layer arc waveguide, the eleventh middle layer arc waveguide, the twelfth middle layer arc waveguide, the thirteenth middle layer arc waveguide, the fourteenth middle layer arc waveguide, the fifteenth middle layer arc waveguide and the third upper layer arc waveguide are positioned on the same straight line, the third bottom layer arc waveguide is positioned on the bottommost layer, the eleventh middle layer arc waveguide and the twelfth middle layer arc waveguide are parallelly arranged on the third bottom layer arc waveguide at intervals, and the eleventh middle layer arc waveguide is concentrically arranged on the inner side of the twelfth middle layer arc waveguide, the thirteenth middle layer arc waveguide is arranged on the eleventh middle layer arc waveguide and the twelfth middle layer arc waveguide, the fourteenth middle layer arc waveguide and the fifteenth middle layer arc waveguide are arranged on the thirteenth middle layer arc waveguide at intervals in parallel, the fourteenth middle layer arc waveguide is concentrically arranged on the inner side of the fifteenth middle layer arc waveguide, and the third upper layer arc waveguide is arranged on the fourteenth middle layer arc waveguide and the fifteenth middle layer arc waveguide; the fourth arc waveguide is formed by connecting a fourth bottom layer arc waveguide, a sixteenth middle layer arc waveguide, a seventeenth middle layer arc waveguide, an eighteenth middle layer arc waveguide, a nineteenth middle layer arc waveguide, a twentieth middle layer arc waveguide and a fourth upper layer arc waveguide through a CMOS compatible process, the radians of the fourth bottom layer arc waveguide, the sixteenth middle layer arc waveguide, the seventeenth middle layer arc waveguide, the eighteenth middle layer arc waveguide, the nineteenth middle layer arc waveguide, the twentieth middle layer arc waveguide and the fourth upper layer arc waveguide are all 90 degrees, the fourth bottom layer arc waveguide is made of silicon dioxide, the fourth bottom layer arc waveguide is 20n thick, the fourth bottom layer arc waveguide is 94.5nm in inner diameter and 124.5nm in outer diameter, the sixteenth middle layer arc waveguide and the seventeenth middle layer arc waveguide are made of silicon dioxide, the thickness of the sixteenth middle layer arc-shaped waveguide and the seventeenth middle layer arc-shaped waveguide are both 18nm, the inner diameter of the sixteenth middle layer arc-shaped waveguide is 124.5nm, the outer diameter of the sixteenth middle layer arc-shaped waveguide is 125.5nm, the inner diameter of the seventeenth middle layer arc-shaped waveguide is 94.5nm, the outer diameter of the seventeenth middle layer arc-shaped waveguide is 95.5nm, the eighteenth middle layer arc-shaped waveguide is made of graphene, the thickness of the eighteenth middle layer arc-shaped waveguide is 1nm, the inner diameter of the eighteenth middle layer arc-shaped waveguide is 94.5nm, the outer diameter of the eighteenth middle layer arc-shaped waveguide is 124.5nm, the nineteenth middle layer arc-shaped waveguide and the twenty middle layer arc-shaped waveguide are both made of silicon dioxide, the thickness of the nineteenth middle layer arc-shaped waveguide and the twenty middle layer arc-shaped waveguide is both 18nm, the inner diameter of the eighteenth middle layer arc-shaped waveguide is 123.5nm, the outer, the outer diameter of the fourth upper layer arc waveguide is 95.5nm, the material of the fourth upper layer arc waveguide is silicon dioxide, the thickness of the fourth upper layer arc waveguide is 20nm, the inner diameter of the fourth upper layer arc waveguide is 94.5nm, the outer diameter of the fourth upper layer arc waveguide is 124.5nm, the centers of the fourth bottom layer arc waveguide, the sixteenth middle layer arc waveguide, the seventeenth middle layer arc waveguide, the eighteenth middle layer arc waveguide, the nineteenth middle layer arc waveguide, the twentieth middle layer arc waveguide and the fourth upper layer arc waveguide are positioned on the same straight line, the fourth bottom layer arc waveguide is positioned on the bottommost layer, the sixteenth middle layer arc waveguide and the seventeenth middle layer arc waveguide are arranged on the fourth bottom layer arc waveguide at intervals in parallel, and the sixteenth middle layer arc waveguide is concentrically arranged on the inner side of the seventeenth arc waveguide, the eighteenth middle layer arc waveguide is arranged on the sixteenth middle layer arc waveguide and the seventeenth middle layer arc waveguide, the nineteenth middle layer arc waveguide and the twentieth middle layer arc waveguide are arranged on the eighteenth middle layer arc waveguide at intervals in parallel, the nineteenth middle layer arc waveguide is concentrically arranged on the inner side of the twentieth middle layer arc waveguide, and the fourth upper layer arc waveguide is arranged on the nineteenth middle layer arc waveguide and the twentieth middle layer arc waveguide; the first micro-ring resonant cavity is formed by connecting a first bottom layer annular waveguide, a first middle layer annular waveguide, a second middle layer annular waveguide, a third middle layer annular waveguide, a fourth middle layer annular waveguide, a fifth middle layer annular waveguide and a first upper layer annular waveguide through a CMOS (complementary metal oxide semiconductor) compatible process, the radians of the first bottom layer annular waveguide, the first middle layer annular waveguide, the second middle layer annular waveguide, the third middle layer annular waveguide, the fourth middle layer annular waveguide, the fifth middle layer annular waveguide and the first upper layer annular waveguide are all 90 degrees, the first bottom layer annular waveguide is made of silicon dioxide, the thickness of the first bottom layer annular waveguide is 20n, the inner diameter of the first bottom layer annular waveguide is 70nm, the outer diameter of the first bottom layer annular waveguide is 100nm, and the materials of the first middle layer annular waveguide and the second middle layer annular waveguide are both made of silicon dioxide, the thickness of the first middle layer annular waveguide and the thickness of the second middle layer annular waveguide are both 18nm, the inner diameter of the first middle layer annular waveguide is 99nm, the outer diameter of the first middle layer annular waveguide is 100nm, the inner diameter of the second middle layer annular waveguide is 70nm, the outer diameter of the second middle layer annular waveguide is 71nm, the material of the third middle layer annular waveguide is graphene, the thickness of the third middle layer annular waveguide is 1nm, the inner diameter of the third middle layer annular waveguide is 70nm, the outer diameter of the third middle layer annular waveguide is 100nm, the material of the fourth middle layer annular waveguide and the material of the fifth middle layer annular waveguide are both silicon dioxide, the thickness of the fourth middle layer annular waveguide and the thickness of the fifth middle layer annular waveguide are both 18nm, the inner diameter of the third middle layer annular waveguide is 99nm, the outer diameter of the third middle layer annular waveguide is 100nm, the inner diameter of the fourth middle layer annular waveguide is 70nm, the outer diameter of the fourth middle layer annular waveguide is 71nm, and the material of the, the thickness of the first upper layer annular waveguide is 20nm, the inner diameter of the first upper layer annular waveguide is 70nm, the outer diameter of the first upper layer annular waveguide is 100nm, the circle centers of the first bottom layer annular waveguide, the first middle layer annular waveguide, the second middle layer annular waveguide, the third middle layer annular waveguide, the fourth middle layer annular waveguide, the fifth middle layer annular waveguide and the first upper layer annular waveguide are positioned on the same straight line, the first bottom layer annular waveguide is positioned at the bottommost layer, the first middle layer annular waveguide and the second middle layer annular waveguide are arranged on the first bottom layer annular waveguide at intervals, the first middle layer annular waveguide is concentrically arranged at the inner side of the second middle layer annular waveguide, and the third middle layer annular waveguide is arranged on the first middle layer annular waveguide and the second middle layer annular waveguide, the fourth middle-layer annular waveguide and the fifth middle-layer annular waveguide are arranged on the third middle-layer annular waveguide at intervals, the fourth middle-layer annular waveguide is concentrically arranged on the inner side of the fifth middle-layer annular waveguide, and the first upper-layer annular waveguide is arranged on the fourth middle-layer annular waveguide and the fifth middle-layer annular waveguide; the second micro-ring resonant cavity is formed by connecting a second bottom layer annular waveguide, a sixth middle layer annular waveguide, a seventh middle layer annular waveguide, an eighth middle layer annular waveguide, a ninth middle layer annular waveguide, a tenth middle layer annular waveguide and a second upper layer annular waveguide through a CMOS compatible process, the radians of the second bottom layer annular waveguide, the sixth middle layer annular waveguide, the seventh middle layer annular waveguide, the eighth middle layer annular waveguide, the ninth middle layer annular waveguide, the tenth middle layer annular waveguide and the second upper layer annular waveguide are all 90 degrees, the second bottom layer annular waveguide is made of silicon dioxide, the thickness of the second bottom layer annular waveguide is 20n, the inner diameter of the second bottom layer annular waveguide is 70nm, the outer diameter of the second bottom layer annular waveguide is 100nm, and the materials of the sixth middle layer annular waveguide and the seventh middle layer annular waveguide are both silicon dioxide, the thickness of the sixth middle layer annular waveguide and the thickness of the seventh middle layer annular waveguide are both 18nm, the inner diameter of the sixth middle layer annular waveguide is 99nm, the outer diameter of the sixth middle layer annular waveguide is 100nm, the inner diameter of the seventh middle layer annular waveguide is 70nm, the outer diameter of the seventh middle layer annular waveguide is 71nm, the material of the eighth middle layer annular waveguide is graphene, the thickness of the eighth middle layer annular waveguide is 1nm, the inner diameter of the eighth middle layer annular waveguide is 70nm, the outer diameter of the eighth middle layer annular waveguide is 100nm, the material of the ninth middle layer annular waveguide and the material of the tenth middle layer annular waveguide are both silicon dioxide, the thickness of the ninth middle layer annular waveguide and the thickness of the tenth middle layer annular waveguide are both 18nm, the inner diameter of the ninth middle layer annular waveguide is 99nm, the outer diameter of the tenth middle layer annular waveguide is 70nm, the outer diameter of the tenth middle layer annular waveguide is 71nm, and the material of the second upper layer annular waveguide is silicon dioxide, the thickness of the second upper layer annular waveguide is 20nm, the inner diameter of the second upper layer annular waveguide is 70nm, the outer diameter of the second upper layer annular waveguide is 100nm, the circle centers of the second bottom layer annular waveguide, the sixth middle layer annular waveguide, the seventh middle layer annular waveguide, the eighth middle layer annular waveguide, the ninth middle layer annular waveguide, the tenth middle layer annular waveguide and the second upper layer annular waveguide are positioned on the same straight line, the second bottom layer annular waveguide is positioned at the bottommost layer, the sixth middle layer annular waveguide and the seventh middle layer annular waveguide are arranged on the second bottom layer annular waveguide at intervals, the sixth middle layer annular waveguide is concentrically arranged at the inner side of the seventh middle layer annular waveguide, the eighth middle layer annular waveguide is arranged on the sixth middle layer annular waveguide and the seventh middle layer annular waveguide, the ninth middle-layer annular waveguide and the tenth middle-layer annular waveguide are arranged on the eighth middle-layer annular waveguide at intervals, the ninth middle-layer annular waveguide is concentrically arranged on the inner side of the tenth middle-layer annular waveguide, and the second upper-layer annular waveguide is arranged on the ninth middle-layer annular waveguide and the tenth middle-layer annular waveguide; the third micro-ring resonant cavity is formed by connecting a third bottom layer annular waveguide, an eleventh middle layer annular waveguide, a twelfth middle layer annular waveguide, a thirteenth middle layer annular waveguide, a fourteenth middle layer annular waveguide, a fifteenth middle layer annular waveguide and a third upper layer annular waveguide through a CMOS compatible process, the radians of the third bottom layer annular waveguide, the eleventh middle layer annular waveguide, the twelfth middle layer annular waveguide, the thirteenth middle layer annular waveguide, the fourteenth middle layer annular waveguide, the fifteenth middle layer annular waveguide and the third upper layer annular waveguide are all 90 degrees, the third bottom layer annular waveguide is made of silicon dioxide, the thickness of the third bottom layer annular waveguide is 20n, the inner diameter of the third bottom layer annular waveguide is 70nm, the outer diameter of the third bottom layer annular waveguide is 100nm, and the eleventh middle layer annular waveguide and the twelfth middle layer annular waveguide are both made of silicon dioxide, the thickness of the eleventh middle layer annular waveguide and the thickness of the twelfth middle layer annular waveguide are both 18nm, the inner diameter of the eleventh middle layer annular waveguide is 99nm, the outer diameter of the eleventh middle layer annular waveguide is 100nm, the inner diameter of the twelfth middle layer annular waveguide is 70nm, the outer diameter of the twelfth middle layer annular waveguide is 71nm, the material of the thirteenth middle layer annular waveguide is graphene, the thickness of the thirteenth middle layer annular waveguide is 1nm, the inner diameter of the thirteenth middle layer annular waveguide is 70nm, the outer diameter of the thirteenth middle layer annular waveguide is 100nm, the material of the fourteenth middle layer annular waveguide and the fifteenth middle layer annular waveguide is silicon dioxide, the thickness of the fourteenth middle layer annular waveguide and the thickness of the fifteenth middle layer annular waveguide are both 18nm, the inner diameter of the fourteenth middle layer annular waveguide is 99nm, the outer diameter of the fourteenth middle layer annular waveguide is 100nm, and the inner diameter of the fifteenth middle layer annular waveguide is 70nm, the outer diameter of the third upper layer annular waveguide is 71nm, the material of the third upper layer annular waveguide is silicon dioxide, the thickness of the third upper layer annular waveguide is 20nm, the inner diameter of the third upper layer annular waveguide is 70nm, the outer diameter of the third upper layer annular waveguide is 100nm, the circle centers of the third bottom layer annular waveguide, the eleventh middle layer annular waveguide, the twelfth middle layer annular waveguide, the thirteenth middle layer annular waveguide, the fourteenth middle layer annular waveguide, the fifteenth middle layer annular waveguide and the third upper layer annular waveguide are positioned on the same straight line, the third bottom layer annular waveguide is positioned at the bottommost layer, the eleventh middle layer annular waveguide and the twelfth middle layer annular waveguide are arranged on the third bottom layer annular waveguide at intervals, and the eleventh middle layer annular waveguide is concentrically arranged at the inner side of the twelfth middle layer annular waveguide, the thirteenth middle ring waveguide is disposed on the eleventh middle ring waveguide and the twelfth middle ring waveguide, the fourteenth middle ring waveguide and the fifteenth middle ring waveguide are disposed on the thirteenth middle ring waveguide at intervals, the fourteenth middle ring waveguide is concentrically disposed on the inner side of the fifteenth middle ring waveguide, and the third upper ring waveguide is disposed on the fourteenth middle ring waveguide and the fifteenth middle ring waveguide; the fourth micro-ring resonant cavity is formed by connecting a fourth bottom layer annular waveguide, a sixteenth middle layer annular waveguide, a seventeenth middle layer annular waveguide, an eighteenth middle layer annular waveguide, a nineteenth middle layer annular waveguide, a twentieth middle layer annular waveguide and a fourth upper layer annular waveguide through a CMOS compatible process, the radians of the fourth bottom layer annular waveguide, the sixteenth middle layer annular waveguide, the seventeenth middle layer annular waveguide, the eighteenth middle layer annular waveguide, the nineteenth middle layer annular waveguide, the twentieth middle layer annular waveguide and the fourth upper layer annular waveguide are all 90 degrees, the fourth bottom layer annular waveguide is made of silicon dioxide, the thickness of the fourth bottom layer annular waveguide is 20n, the inner diameter of the fourth bottom layer annular waveguide is 70nm, the outer diameter of the fourth bottom layer annular waveguide is 100nm, the sixteenth middle layer annular waveguide and the seventeenth annular waveguide are made of silicon dioxide, the thickness of the sixteenth middle layer annular waveguide and the seventeenth middle layer annular waveguide is 18nm, the inner diameter of the sixteenth middle layer annular waveguide is 99nm, the outer diameter of the sixteenth middle layer annular waveguide is 100nm, the inner diameter of the seventeenth middle layer annular waveguide is 70nm, the outer diameter of the seventeenth middle layer annular waveguide is 71nm, the eighteenth middle layer annular waveguide is made of graphene, the thickness of the eighteenth middle layer annular waveguide is 1nm, the inner diameter of the eighteenth middle layer annular waveguide is 70nm, the outer diameter of the eighteenth middle layer annular waveguide is 100nm, the nineteenth middle layer annular waveguide and the twenty middle layer annular waveguide are made of silicon dioxide, the thickness of the nineteenth middle layer annular waveguide and the twenty middle layer annular waveguide is 18nm, the inner diameter of the nineteenth middle layer annular waveguide is 99nm, the outer diameter of the nineteenth middle layer annular waveguide is 100nm, and the inner diameter of the twenty middle layer annular waveguide is 70nm, the outer diameter of the fourth upper layer annular waveguide is 71nm, the material of the fourth upper layer annular waveguide is silicon dioxide, the thickness of the fourth upper layer annular waveguide is 20nm, the inner diameter of the fourth upper layer annular waveguide is 70nm, the outer diameter of the fourth upper layer annular waveguide is 100nm, the circle centers of the fourth bottom layer annular waveguide, the sixteenth middle layer annular waveguide, the seventeenth middle layer annular waveguide, the eighteenth middle layer annular waveguide, the nineteenth middle layer annular waveguide, the twentieth middle layer annular waveguide and the fourth upper layer annular waveguide are positioned on the same straight line, the fourth bottom layer annular waveguide is positioned at the bottommost layer, the sixteenth middle layer annular waveguide and the seventeenth middle layer annular waveguide are arranged on the fourth bottom layer annular waveguide at intervals, and the sixteenth middle layer annular waveguide is concentrically arranged at the inner side of the seventeenth middle layer annular waveguide, the eighteenth middle layer annular waveguide is arranged on the sixteenth middle layer annular waveguide and the seventeenth middle layer annular waveguide, the nineteenth middle layer annular waveguide and the twentieth middle layer annular waveguide are arranged on the eighteenth middle layer annular waveguide at intervals, the nineteenth middle layer annular waveguide is concentrically arranged on the inner side of the twentieth middle layer annular waveguide, and the fourth upper layer annular waveguide is arranged on the nineteenth middle layer annular waveguide and the twentieth middle layer annular waveguide.
The substrate is made of silicon, the thickness of the substrate is 20nm, the buffer layer is made of silicon dioxide, and the thickness of the buffer layer is 20 nm.
Compared with the prior art, the invention has the advantages that the SWAP gate is formed by the first straight waveguide, the second straight waveguide, the third straight waveguide, the first micro-ring resonant cavity, the second micro-ring resonant cavity, the third micro-ring resonant cavity, the fourth micro-ring resonant cavity, the first arc-shaped waveguide, the second arc-shaped waveguide, the third arc-shaped waveguide and the fourth arc-shaped waveguide, the first micro-ring resonant cavity, the second micro-ring resonant cavity, the third micro-ring resonant cavity and the fourth micro-ring resonant cavity form a cascade structure, the structure is simple and compact, reference is provided for further designing more complex logic devices, and the first straight waveguide, the second straight waveguide, the third straight waveguide, the first micro-ring resonant cavity, the second micro-ring resonant cavity, the third micro-ring resonant cavity, the fourth micro-ring resonant cavity, the first arc-shaped waveguide, the second arc-shaped waveguide, the third arc-shaped waveguide and the fourth arc-shaped waveguide are matched with each other in structure, the propagation condition of the graphene surface plasmon is met, the SWAP gate function is realized through the graphene surface plasmon polaritons, and the size is greatly reduced, so that the SWAP gate based on the graphene surface plasmon polaritons is small in size, strong in structure compactness and beneficial to on-chip integration.
Drawings
Fig. 1 is a perspective view of a graphene surface plasmon polariton-based SWAP gate of the present invention;
FIG. 2 is a cross-sectional view of a graphene surface plasmon based SWAP gate of the present invention at a first straight waveguide along a vertical direction;
fig. 3(a) shows transmission lines of a first output terminal and a second output terminal of the graphene surface plasmon polariton-based SWAP gate of the present invention when an operand is '00';
fig. 3(b) shows transmission lines of the first output terminal and the second output terminal of the graphene surface plasmon polariton-based SWAP gate of the present invention when the operand is '01';
fig. 3(c) shows transmission lines of the first output terminal and the second output terminal of the graphene surface plasmon polariton-based SWAP gate of the present invention when the operand is '10';
fig. 3(d) shows transmission lines of the first output terminal and the second output terminal of the graphene surface plasmon polariton-based SWAP gate of the present invention when the operation number is '11'.
Detailed Description
The invention is described in further detail below with reference to the accompanying examples.
Example (b): as shown in fig. 1 and 2, a SWAP gate based on graphene surface plasmons includes a substrate 1, a buffer layer 2, a first straight waveguide, a second straight waveguide, a third straight waveguide, a first arc-shaped waveguide, a second arc-shaped waveguide, a third arc-shaped waveguide, a fourth arc-shaped waveguide, a first micro-ring resonant cavity, a second micro-ring resonant cavity, a third micro-ring resonant cavity, and a fourth micro-ring resonant cavity; the substrate 1 and the buffer layer 2 are both of cuboid structures, the size of the long edge of the base body is equal to that of the long edge of the buffer layer 2, the size of the wide edge of the substrate 1 is equal to that of the wide edge of the buffer layer 2, and the buffer layer 2 is tiled on the substrate 1 to completely cover the upper surface of the substrate 1; the long side direction of the buffer layer 2 is taken as the left-right direction, and the wide side direction is taken as the front-back direction;
a first straight waveguide, a second straight waveguide and a third straight waveguide are respectively tiled on the upper surface of the buffer layer 2, the first straight waveguide, the second straight waveguide and the third straight waveguide are respectively parallel to the long edge of the buffer layer 2, the second straight waveguide is positioned on the front side of the first straight waveguide, the widths of the first straight waveguide, the second straight waveguide and the third straight waveguide are all 30nm, the length of the first straight waveguide is 100nm, the length of the second straight waveguide is 850nm, the length of the third straight waveguide is 850nm, a first micro-ring resonant cavity, a second micro-ring resonant cavity, a third micro-ring resonant cavity and a fourth micro-ring resonant cavity are respectively tiled on the upper surface of the buffer layer 2, the first micro-ring resonant cavity is positioned on the front side of the second straight waveguide, if the first micro-ring resonant cavity is translated backwards by 20nm, the second straight waveguide is tangent to the outer wall of the first micro-ring resonant cavity, the second micro-ring resonant cavity and the third micro-ring resonant cavity are respectively positioned between the second straight waveguide and the third straight waveguide, the second micro-ring resonant cavity is positioned on the front side of the third micro-ring resonant cavity, if the second micro-ring resonant cavity translates forwards for 2nm, the second straight waveguide is tangent to the outer wall of the second micro-ring resonant cavity, if the second micro-ring resonant cavity translates backwards for 4nm, the outer wall of the second micro-ring resonant cavity is tangent to the outer wall of the third micro-ring resonant cavity, if the third micro-ring resonant cavity translates backwards for 2nm, the third straight waveguide is tangent to the outer wall of the third micro-ring resonant cavity, the fourth micro-ring resonant cavity is positioned on the rear side of the third straight waveguide, if the fourth micro-ring resonant cavity translates forwards for 20nm, the third straight waveguide is tangent to the outer wall of the fourth micro-ring resonant cavity, the distance between the centers of the first micro-ring resonant cavity and the fourth micro-ring resonant cavity is 708nm, and the distance between the centers of the second micro-ring resonant cavity and the third micro-ring resonant cavity is 204; the connecting line of the circle center of the first micro-ring resonant cavity and the circle center of the fourth micro-ring resonant cavity, and the connecting line of the circle center of the second micro-ring resonant cavity and the circle center of the third micro-ring resonant cavity are respectively parallel to the wide edge of the buffer layer 2, the inner ring radius of the first micro-ring resonant cavity, the inner ring radius of the second micro-ring resonant cavity, the inner ring radius of the third micro-ring resonant cavity and the outer ring radius of the fourth micro-ring resonant cavity are all 70nm, and the outer ring radius; the inner diameters of the first arc-shaped waveguide, the second arc-shaped waveguide, the third arc-shaped waveguide and the fourth arc-shaped waveguide are all 94.5nm, and the outer diameters of the first arc-shaped waveguide, the second arc-shaped waveguide, the third arc-shaped waveguide and the fourth arc-shaped waveguide are all 124.5 nm; the left end of the second straight waveguide is connected with the right end of the first arc waveguide, the rear end of the first arc waveguide is connected with the front end of the second arc waveguide, the left end of the second arc waveguide is connected with the right end of the first straight waveguide, the left end of the third arc waveguide is connected with the right end of the first straight waveguide, the rear end of the third arc waveguide is connected with the front end of the fourth arc waveguide, the right end of the fourth arc waveguide is connected with the left end of the third straight waveguide, the left end of the first straight waveguide is an input end of the SWAP gate, the right end of the second straight waveguide is a first output end of the SWAP gate, and the right end of the third straight waveguide is a second output end of the SWAP gate.
In this embodiment, the first straight waveguide is formed by connecting a first bottom layer straight waveguide 3, a first middle layer straight waveguide 4, a second middle layer straight waveguide 5, a third middle layer straight waveguide 6, a fourth middle layer straight waveguide 7, a fifth middle layer straight waveguide 8 and a first upper layer straight waveguide 9 through a CMOS compatible process, the first bottom layer straight waveguide 3 is made of silica, the first bottom layer straight waveguide 3 is 20nm thick and 30nm wide, the first middle layer straight waveguide 4 and the second middle layer straight waveguide 5 are made of silica, the first middle layer straight waveguide 4 and the second middle layer straight waveguide 5 are both 18nm thick and 1nm wide, the third middle layer straight waveguide 6 is made of graphene, the third middle layer straight waveguide 6 is 1nm thick and 30nm wide, the fourth middle layer straight waveguide 7 and the fifth middle layer straight waveguide 8 are both made of silica, the fourth middle layer straight waveguide 7 and the fifth middle layer straight waveguide 8 are both 18nm thick, the widths of the first upper layer straight waveguides 9 are all 1nm, the first upper layer straight waveguides 9 are made of silicon dioxide, the thicknesses of the first upper layer straight waveguides 9 are 20nm and 30nm, the first bottom layer straight waveguides 3 are located at the bottommost layer, the first middle layer straight waveguides 4 and the second middle layer straight waveguides 5 are arranged on the first bottom layer straight waveguides 3 at intervals in parallel, the distance between the first middle layer straight waveguides 4 and the second middle layer straight waveguides 5 is 28nm, the third middle layer straight waveguides 6 are arranged on the first middle layer straight waveguides 4 and the second middle layer straight waveguides 5, the fourth middle layer straight waveguides 7 and the fifth middle layer straight waveguides 8 are arranged on the third middle layer straight waveguides 6 at intervals in parallel, the distance between the fourth middle layer straight waveguides 7 and the fifth middle layer straight waveguides 8 is 28nm, and the first upper layer straight waveguides 9 are arranged on the fourth middle layer straight waveguides 7 and the fifth middle layer straight waveguides 8;
the second straight waveguide is formed by connecting a second bottom layer straight waveguide 10, a sixth middle layer straight waveguide 11, a seventh middle layer straight waveguide 12, an eighth middle layer straight waveguide 13, a ninth middle layer straight waveguide 14, a tenth middle layer straight waveguide 15 and a second upper layer straight waveguide 16 through a CMOS compatible process, the second bottom layer straight waveguide 10 is made of silicon dioxide, the second bottom layer straight waveguide 10 is 20nm in thickness and 30nm in width, the sixth middle layer straight waveguide 11 and the seventh middle layer straight waveguide 12 are both made of silicon dioxide, the sixth middle layer straight waveguide 11 and the seventh middle layer straight waveguide 12 are both 18nm in thickness and 1nm in width, the eighth middle layer straight waveguide 13 is made of graphene, the eighth middle layer straight waveguide 13 is 1nm in thickness and 30nm in width, the ninth middle layer straight waveguide 14 and the tenth middle layer straight waveguide 15 are both made of silicon dioxide, and the ninth middle layer straight waveguide 14 and the tenth middle layer straight waveguide 15 are both 18nm in thickness, the widths of the first and second upper straight waveguides are all 1nm, the second upper straight waveguide 16 is made of silicon dioxide, the thickness of the second upper straight waveguide 16 is 20nm, the width of the second upper straight waveguide is 30nm, the second bottom straight waveguide 10 is positioned at the bottommost layer, the sixth and seventh middle straight waveguides 11 and 12 are arranged on the second bottom straight waveguide 10 at intervals in parallel, the distance between the sixth and seventh middle straight waveguides 11 and 12 is 28nm, the eighth and tenth middle straight waveguides 13 are arranged on the sixth and seventh middle straight waveguides 11 and 12, the ninth and tenth middle straight waveguides 14 and 15 are arranged on the eighth and tenth middle straight waveguides 13 at intervals in parallel, the distance between the ninth and tenth middle straight waveguides 14 and 15 is 28nm, and the second upper straight waveguide 16 is arranged on the ninth and tenth middle straight waveguides 14 and 15;
the third straight waveguide is formed by connecting a third bottom layer straight waveguide 17, an eleventh middle layer straight waveguide 18, a twelfth middle layer straight waveguide 19, a thirteenth middle layer straight waveguide 20, a fourteenth middle layer straight waveguide 21, a fifteenth middle layer straight waveguide 22 and a third upper layer straight waveguide 23 through a CMOS compatible process, the third bottom layer straight waveguide 17 is made of silicon dioxide, the third bottom layer straight waveguide 17 is 20nm in thickness and 30nm in width, the eleventh middle layer straight waveguide 18 and the twelfth middle layer straight waveguide 19 are made of silicon dioxide, the eleventh middle layer straight waveguide 18 and the twelfth middle layer straight waveguide 19 are both 18nm in thickness and 1nm in width, the thirteenth middle layer straight waveguide 20 is made of graphene, the thirteenth middle layer straight waveguide 20 is 1nm in thickness and 30nm in width, the fourteenth middle layer straight waveguide 21 and the fifteenth middle layer straight waveguide 22 are both made of silicon dioxide, the fourteenth middle layer straight waveguide 21 and the fifteenth middle layer straight waveguide 22 are both 18nm in thickness, the widths of the upper layer straight waveguides are all 1nm, the material of the upper layer straight waveguide 23 is silicon dioxide, the thickness of the upper layer straight waveguide 23 is 20nm, the width of the upper layer straight waveguide is 30nm, the third bottom layer straight waveguide 17 is positioned at the bottommost layer, the eleventh middle layer straight waveguide 18 and the twelfth middle layer straight waveguide 19 are parallelly arranged on the third bottom layer straight waveguide 17 at intervals, the distance between the eleventh middle layer straight waveguide 18 and the twelfth middle layer straight waveguide 19 is 28nm, the thirteenth middle layer straight waveguide 20 is arranged on the eleventh middle layer straight waveguide 18 and the twelfth middle layer straight waveguide 19, the fourteenth middle layer straight waveguide 21 and the fifteenth middle layer straight waveguide 22 are parallelly arranged on the thirteenth middle layer straight waveguide 20 at intervals, the distance between the fourteenth middle layer straight waveguide 21 and the fifteenth middle layer straight waveguide 22 is 28nm, and the third upper layer straight waveguide 23 is arranged on the fourteenth middle layer straight waveguide 21 and the fifteenth middle layer straight waveguide 22;
the first arc-shaped waveguide is formed by connecting a first bottom layer arc-shaped waveguide 24, a first middle layer arc-shaped waveguide 25, a second middle layer arc-shaped waveguide 26, a third middle layer arc-shaped waveguide 27, a fourth middle layer arc-shaped waveguide 28, a fifth middle layer arc-shaped waveguide 29 and a first upper layer arc-shaped waveguide 30 through a CMOS compatible process, the radians of the first bottom layer arc-shaped waveguide 24, the first middle layer arc-shaped waveguide 25, the second middle layer arc-shaped waveguide 26, the third middle layer arc-shaped waveguide 27, the fourth middle layer arc-shaped waveguide 28, the fifth middle layer arc-shaped waveguide 29 and the first upper layer arc-shaped waveguide 30 are all 90 degrees, the first bottom layer arc-shaped waveguide 24 is made of silicon dioxide, the thickness of the first bottom layer arc-shaped waveguide 24 is 20nm, the inner diameter of the first bottom layer arc-shaped waveguide 24 is 94.5nm, the outer diameter is 124.5nm, the materials of the first middle layer arc-shaped waveguide 25 and the second middle layer arc-shaped waveguide 26 are both made of silicon dioxide, the thicknesses, the inner diameter of the first middle layer arc waveguide 25 is 123.5nm, the outer diameter is 124.5nm, the inner diameter of the second middle layer arc waveguide 26 is 94.5nm, the outer diameter is 95.5nm, the material of the third middle layer arc waveguide 27 is graphene, the thickness of the third middle layer arc waveguide 27 is 1nm, the inner diameter of the third middle layer arc waveguide 27 is 94.5nm, the outer diameter is 124.5nm, the materials of the fourth middle layer arc waveguide 28 and the fifth middle layer arc waveguide 29 are both silicon dioxide, the thickness of the fourth middle layer arc waveguide 28 and the fifth middle layer arc waveguide 29 are both 18nm, the inner diameter of the third middle layer arc waveguide 27 is 123.5nm, the outer diameter is 124.5nm, the inner diameter of the fourth middle layer arc waveguide 28 is 94.5nm, the outer diameter is 95.5nm, the material of the first upper layer arc waveguide 30 is silicon dioxide, the thickness of the first upper layer arc waveguide 30 is 20nm, the inner diameter of the first upper layer arc waveguide 30 is 94.5nm, the outer diameter of the first upper layer arc waveguide is 124.5nm, the outer diameter of the first bottom layer arc waveguide is, The centers of the first middle layer arc-shaped waveguide 25, the second middle layer arc-shaped waveguide 26, the third middle layer arc-shaped waveguide 27, the fourth middle layer arc-shaped waveguide 28, the fifth middle layer arc-shaped waveguide 29 and the first upper layer arc-shaped waveguide 30 are positioned on the same straight line, the first bottom layer arc-shaped waveguide 24 is positioned at the bottommost layer, the first middle layer arc-shaped waveguide 25 and the second middle layer arc-shaped waveguide 26 are parallelly arranged on the first bottom layer arc-shaped waveguide 24 at intervals, and the first middle layer arc waveguide 25 is concentrically arranged at the inner side of the second middle layer arc waveguide 26, the third middle layer arc waveguide 27 is arranged on the first middle layer arc waveguide 25 and the second middle layer arc waveguide 26, the fourth middle layer arc waveguide 28 and the fifth middle layer arc waveguide 29 are parallelly arranged on the third middle layer arc waveguide 27 at intervals, the fourth middle arc waveguide 28 is concentrically arranged at the inner side of the fifth middle arc waveguide 29, and the first upper arc waveguide 30 is arranged on the fourth middle arc waveguide 28 and the fifth middle arc waveguide 29;
the second arc waveguide is formed by connecting a second bottom layer arc waveguide 31, a sixth middle layer arc waveguide 32, a seventh middle layer arc waveguide 33, an eighth middle layer arc waveguide 34, a ninth middle layer arc waveguide 35, a tenth middle layer arc waveguide 36 and a second upper layer arc waveguide 37 through a CMOS compatible process, the radians of the second bottom layer arc waveguide 31, the sixth middle layer arc waveguide 32, the seventh middle layer arc waveguide 33, the eighth middle layer arc waveguide 34, the ninth middle layer arc waveguide 35, the tenth middle layer arc waveguide 36 and the second upper layer arc waveguide 37 are all 90 degrees, the material of the second bottom layer arc waveguide 31 is silicon dioxide, the thickness of the second bottom layer arc waveguide 31 is 20n, the inner diameter of the second bottom layer arc waveguide 31 is 94.5nm, the outer diameter is 124.5nm, the materials of the sixth middle layer arc waveguide 32 and the seventh middle layer arc waveguide 33 are both silicon dioxide, the thicknesses of the sixth middle layer arc waveguide 32 and the seventh middle layer arc waveguide 33 are both 18nm, the sixth middle layer arc waveguide 32 has an inner diameter of 123.5nm and an outer diameter of 124.5nm, the seventh middle layer arc waveguide 33 has an inner diameter of 94.5nm and an outer diameter of 95.5nm, the eighth middle layer arc waveguide 34 is made of graphene, the eighth middle layer arc waveguide 34 has a thickness of 1nm, the eighth middle layer arc waveguide 34 has an inner diameter of 94.5nm and an outer diameter of 124.5nm, the ninth middle layer arc waveguide 35 and the tenth middle layer arc waveguide 36 are made of silicon dioxide, the ninth middle layer arc waveguide 35 and the eleventh middle layer arc waveguide 36 have a thickness of 18nm, the eighth middle layer arc waveguide 34 has an inner diameter of 123.5nm and an outer diameter of 124.5nm, the ninth middle layer arc waveguide 35 has an inner diameter of 94.5nm and an outer diameter of 95.5nm, the second upper layer arc waveguide 37 is made of silicon dioxide, the second upper layer arc waveguide 37 has a thickness of 20nm, the second upper layer arc waveguide 37 has an inner diameter of 94.5nm, an outer diameter of 124.5nm and a bottom layer arc waveguide thickness of 124.31 nm, The centers of the sixth middle layer arc waveguide 32, the seventh middle layer arc waveguide 33, the eighth middle layer arc waveguide 34, the ninth middle layer arc waveguide 35, the tenth middle layer arc waveguide 36 and the second upper layer arc waveguide 37 are positioned on the same straight line, the second bottom layer arc waveguide 31 is positioned on the bottommost layer, the sixth middle layer arc waveguide 32 and the seventh middle layer arc waveguide 33 are parallelly and alternately arranged on the second bottom layer arc waveguide 31, and the sixth middle layer arc waveguide 32 is concentrically disposed at the inner side of the seventh middle layer arc waveguide 33, the eighth middle layer arc waveguide 34 is disposed on the sixth middle layer arc waveguide 32 and the seventh middle layer arc waveguide 33, the ninth middle layer arc waveguide 35 and the eleventh middle layer arc waveguide 36 are disposed in parallel at an interval on the eighth middle layer arc waveguide 34, the ninth middle layer arc waveguide 35 is concentrically arranged at the inner side of the eleventh middle layer arc waveguide 36, and the second upper layer arc waveguide 37 is arranged on the ninth middle layer arc waveguide 35 and the twelfth middle layer arc waveguide 36;
the third arc-shaped waveguide is formed by connecting a third bottom layer arc-shaped waveguide 38, an eleventh middle layer arc-shaped waveguide 39, a twelfth middle layer arc-shaped waveguide 40, a thirteenth middle layer arc-shaped waveguide 41, a fourteenth middle layer arc-shaped waveguide 42, a fifteenth middle layer arc-shaped waveguide 43 and a third upper layer arc-shaped waveguide 44 through a CMOS compatible process, the radians of the third bottom layer arc-shaped waveguide 38, the eleventh middle layer arc-shaped waveguide 39, the twelfth middle layer arc-shaped waveguide 40, the thirteenth middle layer arc-shaped waveguide 41, the fourteenth middle layer arc-shaped waveguide 42, the fifteenth middle layer arc-shaped waveguide 43 and the third upper layer arc-shaped waveguide 44 are all 90 degrees, the material of the third bottom layer arc-shaped waveguide 38 is silicon dioxide, the thickness of the third bottom layer arc-shaped waveguide 38 is 20n, the inner diameter of the third bottom layer arc-shaped waveguide 38 is 94.5nm, the outer diameter is 124.5nm, the materials of the eleventh middle layer arc-shaped, the thickness of the eleventh middle layer arc waveguide 39 and the twelfth middle layer arc waveguide 40 are both 18nm, the inner diameter of the eleventh middle layer arc waveguide 39 is 123.5nm, the outer diameter is 124.5nm, the inner diameter of the twelfth middle layer arc waveguide 40 is 94.5nm, the outer diameter is 95.5nm, the material of the thirteenth middle layer arc waveguide 41 is graphene, the thickness of the thirteenth middle layer arc waveguide 41 is 1nm, the inner diameter of the thirteenth middle layer arc waveguide 41 is 94.5nm, the outer diameter is 124.5nm, the material of the fourteenth middle layer arc waveguide 42 and the fifteenth middle layer arc waveguide 43 is silicon dioxide, the thickness of the fourteenth middle layer arc waveguide 42 and the fifteenth middle layer arc waveguide 43 is 18nm, the inner diameter of the thirteenth middle layer arc waveguide 41 is 123.5nm, the outer diameter is 124.5nm, the inner diameter of the fourteenth middle layer arc waveguide 42 is 94.5nm, the outer diameter is 95.5nm, the material of the third upper layer arc waveguide 44 is silicon dioxide, the thickness of the third upper layer arc waveguide 44 is 20nm, the inner diameter of the third upper layer arc waveguide 44 is 94.5nm, the outer diameter is 124.5nm, the circle centers of the third bottom layer arc waveguide 38, the eleventh middle layer arc waveguide 39, the twelfth middle layer arc waveguide 40, the thirteenth middle layer arc waveguide 41, the fourteenth middle layer arc waveguide 42, the fifteenth middle layer arc waveguide 43 and the third upper layer arc waveguide 44 are positioned on the same straight line, the third bottom layer arc waveguide 38 is positioned at the bottommost layer, the eleventh middle layer arc waveguide 39 and the twelfth middle layer arc waveguide 40 are parallelly and alternately arranged on the third bottom layer arc waveguide 38, the eleventh middle layer arc waveguide 39 is concentrically arranged at the inner side of the twelfth middle layer arc waveguide 40, the thirteenth middle layer arc waveguide 41 is arranged on the eleventh middle layer arc waveguide 39 and the twelfth middle layer arc waveguide 40, the fourteenth middle layer arc waveguide 42 and the fifteenth middle layer arc waveguide 43 are parallelly and alternately arranged on the thirteenth middle layer arc waveguide 41, the fourteenth middle arc waveguide 42 is concentrically arranged at the inner side of the fifteenth middle arc waveguide 43, and the third upper arc waveguide 44 is arranged on the fourteenth middle arc waveguide 42 and the fifteenth middle arc waveguide 43;
the fourth arc-shaped waveguide is formed by connecting a fourth bottom layer arc-shaped waveguide 45, a sixteenth middle layer arc-shaped waveguide 46, a seventeenth middle layer arc-shaped waveguide 47, an eighteenth middle layer arc-shaped waveguide 48, a nineteenth middle layer arc-shaped waveguide 49, a twentieth middle layer arc-shaped waveguide 50 and a fourth upper layer arc-shaped waveguide 51 through a CMOS compatible process, the radians of the fourth bottom layer arc-shaped waveguide 45, the sixteenth middle layer arc-shaped waveguide 46, the seventeenth middle layer arc-shaped waveguide 47, the eighteenth middle layer arc-shaped waveguide 48, the nineteenth middle layer arc-shaped waveguide 49, the twentieth middle layer arc-shaped waveguide 50 and the fourth upper layer arc-shaped waveguide 51 are all 90 degrees, the fourth bottom layer arc-shaped waveguide 45 is made of silicon dioxide, the thickness of the fourth bottom layer arc-shaped waveguide 45 is 20n, the inner diameter of the fourth bottom layer arc-shaped waveguide 45 is 94.5nm, the outer diameter is 124.5nm, the thickness of the sixteenth-middle-layer arc waveguide 46 and the seventeenth-middle-layer arc waveguide 47 is 18nm, the inner diameter of the sixteenth-middle-layer arc waveguide 46 is 124.5nm, the outer diameter is 125.5nm, the inner diameter of the seventeenth-middle-layer arc waveguide 47 is 94.5nm, the outer diameter is 95.5nm, the eighteenth-middle-layer arc waveguide 48 is made of graphene, the thickness of the eighteenth-middle-layer arc waveguide 48 is 1nm, the inner diameter of the eighteenth-middle-layer arc waveguide 48 is 94.5nm, the outer diameter is 124.5nm, the nineteenth-middle-layer arc waveguide 49 and the twenty-middle-layer arc waveguide 50 are both made of silicon dioxide, the thickness of the nineteenth-middle-layer arc waveguide 49 and the twenty-middle-layer arc waveguide 50 is 18nm, the inner diameter of the eighteenth-middle-layer arc waveguide 48 is 123.5nm, the outer diameter is 124.5nm, the inner diameter of the nineteenth-middle-layer arc waveguide 49 is 94, the thickness of the fourth upper layer arc waveguide 51 is 20nm, the inner diameter of the fourth upper layer arc waveguide 51 is 94.5nm, the outer diameter is 124.5nm, the centers of the fourth bottom layer arc waveguide 45, the sixteenth middle layer arc waveguide 46, the seventeenth middle layer arc waveguide 47, the eighteenth middle layer arc waveguide 48, the nineteenth middle layer arc waveguide 49, the twentieth middle layer arc waveguide 50 and the fourth upper layer arc waveguide 51 are positioned on the same straight line, the fourth bottom layer arc waveguide 45 is positioned at the bottommost layer, the sixteenth middle layer arc waveguide 46 and the seventeenth middle layer arc waveguide 47 are parallelly and alternately arranged on the fourth bottom layer arc waveguide 45, the sixteenth middle layer arc waveguide 46 is concentrically arranged at the inner side of the seventeenth middle layer arc waveguide 47, the eighteenth middle layer arc waveguide 48 is arranged on the sixteenth middle layer arc waveguide 46 and the seventeenth middle layer arc waveguide 47, the nineteenth middle layer arc waveguide 49 and the twenty middle layer arc waveguide 50 are parallelly and alternately arranged on the eighteenth middle layer arc waveguide 48, the nineteenth-middle-layer arc waveguide 49 is concentrically arranged on the inner side of the twentieth-middle-layer arc waveguide 50, and the fourth upper-layer arc waveguide 51 is arranged on the nineteenth-middle-layer arc waveguide 49 and the twentieth-middle-layer arc waveguide 50;
the first micro-ring resonant cavity is formed by connecting a first bottom layer annular waveguide 52, a first middle layer annular waveguide 53, a second middle layer annular waveguide 54, a third middle layer annular waveguide 55, a fourth middle layer annular waveguide 56, a fifth middle layer annular waveguide 57 and a first upper layer annular waveguide 58 through a CMOS compatible process, the radians of the first bottom layer annular waveguide 52, the first middle layer annular waveguide 53, the second middle layer annular waveguide 54, the third middle layer annular waveguide 55, the fourth middle layer annular waveguide 56, the fifth middle layer annular waveguide 57 and the first upper layer annular waveguide 58 are all 90 degrees, the first bottom layer annular waveguide 52 is made of silicon dioxide, the thickness of the first bottom layer annular waveguide 52 is 20n, the inner diameter of the first bottom layer annular waveguide 52 is 70nm, the outer diameter is 100nm, the materials of the first middle layer annular waveguide 53 and the second middle layer annular waveguide 54 are both made of silicon dioxide, the thicknesses of the first middle layer annular waveguide 53 and the second middle layer annular waveguide 54 are both 18nm, the inner diameter of the first middle-layer annular waveguide 53 is 99nm, the outer diameter is 100nm, the inner diameter of the second middle-layer annular waveguide 54 is 70nm, the outer diameter is 71nm, the material of the third middle-layer annular waveguide 55 is graphene, the thickness of the third middle-layer annular waveguide 55 is 1nm, the inner diameter of the third middle-layer annular waveguide 55 is 70nm, the outer diameter is 100nm, the materials of the fourth middle-layer annular waveguide 56 and the fifth middle-layer annular waveguide 57 are both silica, the thicknesses of the fourth middle-layer annular waveguide 56 and the fifth middle-layer annular waveguide 57 are both 18nm, the inner diameter of the third middle-layer annular waveguide 55 is 99nm, the outer diameter is 100nm, the inner diameter of the fourth middle-layer annular waveguide 56 is 70nm, the outer diameter is 71nm, the material of the first upper-layer annular waveguide 58 is silica, the thickness of the first upper-layer annular waveguide 58 is 20nm, the inner diameter of the first upper-layer annular waveguide 58 is 70nm, the outer diameter is 100nm, the first, The centers of the first middle-layer annular waveguide 53, the second middle-layer annular waveguide 54, the third middle-layer annular waveguide 55, the fourth middle-layer annular waveguide 56, the fifth middle-layer annular waveguide 57 and the first upper-layer annular waveguide 58 are positioned on the same straight line, the first bottom-layer annular waveguide 52 is positioned at the bottommost layer, the first middle-layer annular waveguide 53 and the second middle-layer annular waveguide 54 are arranged on the first bottom-layer annular waveguide 52 at intervals, and the first middle layer annular waveguide 53 is concentrically disposed inside the second middle layer annular waveguide 54, the third middle layer annular waveguide 55 is disposed on the first middle layer annular waveguide 53 and the second middle layer annular waveguide 54, the fourth middle layer annular waveguide 56 and the fifth middle layer annular waveguide 57 are disposed on the third middle layer annular waveguide 55 at intervals, the fourth middle-layer annular waveguide 56 is concentrically arranged on the inner side of the fifth middle-layer annular waveguide 57, and the first upper-layer annular waveguide 58 is arranged on the fourth middle-layer annular waveguide 56 and the fifth middle-layer annular waveguide 57;
the second micro-ring resonant cavity is formed by connecting a second bottom layer annular waveguide 59, a sixth middle layer annular waveguide 60, a seventh middle layer annular waveguide 61, an eighth middle layer annular waveguide 62, a ninth middle layer annular waveguide 63, a tenth middle layer annular waveguide 64 and a second upper layer annular waveguide 65 through a CMOS compatible process, the radians of the second bottom layer annular waveguide 59, the sixth middle layer annular waveguide 60, the seventh middle layer annular waveguide 61, the eighth middle layer annular waveguide 62, the ninth middle layer annular waveguide 63, the tenth middle layer annular waveguide 64 and the second upper layer annular waveguide 65 are all 90 degrees, the second bottom layer annular waveguide 59 is made of silicon dioxide, the second bottom layer annular waveguide 59 is 20n thick, the second bottom layer annular waveguide 59 is 70nm in inner diameter and 100nm in outer diameter, the sixth middle layer annular waveguide 60 and the seventh middle layer annular waveguide 61 are made of silicon dioxide, the sixth middle layer annular waveguide 60 and the seventh middle layer annular waveguide 61 are both 18nm in thickness, the sixth middle layer annular waveguide 60 has an inner diameter of 99nm and an outer diameter of 100nm, the seventh middle layer annular waveguide 61 has an inner diameter of 70nm and an outer diameter of 71nm, the eighth middle layer annular waveguide 62 is made of graphene, the eighth middle layer annular waveguide 62 has a thickness of 1nm, the eighth middle layer annular waveguide 62 has an inner diameter of 70nm and an outer diameter of 100nm, the ninth middle layer annular waveguide 63 and the twelfth middle layer annular waveguide 64 are made of silica, the ninth middle layer annular waveguide 63 and the eleventh middle layer annular waveguide 64 have a thickness of 18nm, the ninth middle layer annular waveguide 63 has an inner diameter of 99nm and an outer diameter of 100nm, the twelfth middle layer annular waveguide 64 has an inner diameter of 70nm and an outer diameter of 71nm, the second upper layer annular waveguide 65 is made of silica, the second upper layer annular waveguide 65 has a thickness of 20nm, the second upper layer annular waveguide 65 has an inner diameter of 70nm and an outer diameter of 100nm, the second bottom layer annular waveguide 59, and the seventh middle layer annular waveguide 59, The centers of circles of a sixth middle layer annular waveguide 60, a seventh middle layer annular waveguide 61, an eighth middle layer annular waveguide 62, a ninth middle layer annular waveguide 63, a tenth middle layer annular waveguide 64 and a second upper layer annular waveguide 65 are positioned on the same straight line, the second bottom layer annular waveguide 59 is positioned at the bottommost layer, the sixth middle layer annular waveguide 60 and the seventh middle layer annular waveguide 61 are arranged on the second bottom layer annular waveguide 59 at intervals, and the sixth middle layer annular waveguide 60 is concentrically disposed inside the seventh middle layer annular waveguide 61, the eighth middle layer annular waveguide 62 is disposed on the sixth middle layer annular waveguide 60 and the seventh middle layer annular waveguide 61, the ninth middle layer annular waveguide 63 and the eleventh middle layer annular waveguide 64 are disposed at intervals on the eighth middle layer annular waveguide 62, and the ninth middle-layer annular waveguide 63 is concentrically disposed inside the eleventh middle-layer annular waveguide 64, and the second upper-layer annular waveguide 65 is disposed on the ninth middle-layer annular waveguide 63 and the twelfth middle-layer annular waveguide 64;
the third micro-ring resonant cavity is formed by connecting a third bottom layer annular waveguide 66, an eleventh middle layer annular waveguide 67, a twelfth middle layer annular waveguide 68, a thirteenth middle layer annular waveguide 69, a fourteenth middle layer annular waveguide 70, a fifteenth middle layer annular waveguide 71 and a third upper layer annular waveguide 72 through a CMOS compatible process, the radians of the third bottom layer annular waveguide 66, the eleventh middle layer annular waveguide 67, the twelfth middle layer annular waveguide 68, the thirteenth middle layer annular waveguide 69, the fourteenth middle layer annular waveguide 70, the fifteenth middle layer annular waveguide 71 and the third upper layer annular waveguide 72 are all 90 degrees, the material of the third bottom layer annular waveguide 66 is silicon dioxide, the thickness of the third bottom layer annular waveguide 66 is 20n, the inner diameter of the third bottom layer annular waveguide 66 is 70nm, the outer diameter is 100nm, the materials of the eleventh middle layer annular waveguide 67 and the twelfth middle layer annular waveguide 68 are both silicon dioxide, the thickness of the eleventh middle layer annular waveguide 67 and the twelfth middle layer annular waveguide 68 is 18nm, the inner diameter of the eleventh middle layer annular waveguide 67 is 99nm, the outer diameter of the eleventh middle layer annular waveguide is 100nm, the inner diameter of the twelfth middle layer annular waveguide 68 is 70nm, the outer diameter of the twelfth middle layer annular waveguide is 71nm, the material of the thirteenth middle layer annular waveguide 69 is graphene, the thickness of the thirteenth middle layer annular waveguide 69 is 1nm, the inner diameter of the thirteenth middle layer annular waveguide 69 is 70nm, the outer diameter of the thirteenth middle layer annular waveguide is 100nm, the materials of the fourteenth middle layer annular waveguide 70 and the fifteenth middle layer annular waveguide 71 are both silicon dioxide, the thickness of the fourteenth middle layer annular waveguide 70 and the fifteenth middle layer annular waveguide 71 is 18nm, the inner diameter of the fourteenth middle layer annular waveguide 70 is 99nm, the outer diameter of the fifteenth middle layer annular waveguide 71 is 70nm, the outer diameter of the fourteenth middle layer annular waveguide is 71nm, the, the thickness of the third upper layer annular waveguide 72 is 20nm, the inner diameter of the third upper layer annular waveguide 72 is 70nm, the outer diameter is 100nm, the centers of circles of the third bottom layer annular waveguide 66, the eleventh middle layer annular waveguide 67, the twelfth middle layer annular waveguide 68, the thirteenth middle layer annular waveguide 69, the fourteenth middle layer annular waveguide 70, the fifteenth middle layer annular waveguide 71 and the third upper layer annular waveguide 72 are positioned on the same straight line, the third bottom layer annular waveguide 66 is positioned at the bottommost layer, the eleventh middle layer annular waveguide 67 and the twelfth middle layer annular waveguide 68 are arranged on the third bottom layer annular waveguide 66 at intervals, the eleventh middle layer annular waveguide 67 is concentrically arranged at the inner side of the twelfth middle layer annular waveguide 68, the thirteenth middle layer annular waveguide 69 is arranged on the eleventh middle layer annular waveguide 67 and the twelfth middle layer annular waveguide 68, the fourteenth middle layer annular waveguide 70 and the fifteenth middle layer annular waveguide 71 are arranged on the thirteenth middle layer annular waveguide 69 at intervals, and the fourteenth middle ring waveguide 70 is concentrically disposed inside the fifteenth middle ring waveguide 71, and the third upper ring waveguide 72 is disposed on the fourteenth middle ring waveguide 70 and the fifteenth middle ring waveguide 71;
the fourth micro-ring resonator is formed by connecting a fourth bottom layer annular waveguide 73, a sixteenth middle layer annular waveguide 74, a seventeenth middle layer annular waveguide 75, an eighteenth middle layer annular waveguide 76, a nineteenth middle layer annular waveguide 77, a twentieth middle layer annular waveguide 78 and a fourth upper layer annular waveguide 79 through a CMOS compatible process, the radians of the fourth bottom layer annular waveguide 73, the sixteenth middle layer annular waveguide 74, the seventeenth middle layer annular waveguide 75, the eighteenth middle layer annular waveguide 76, the nineteenth middle layer annular waveguide 77, the twentieth middle layer annular waveguide 78 and the fourth upper layer annular waveguide 79 are all 90 degrees, the fourth bottom layer annular waveguide 73 is made of silicon dioxide, the thickness of the fourth bottom layer annular waveguide 73 is 20n, the inner diameter of the fourth bottom layer annular waveguide 73 is 70nm, the outer diameter is 100nm, the materials of the sixteenth middle layer annular waveguide 74 and the seventeenth middle layer annular waveguide 75 are both made of silicon dioxide, the thickness of the sixteenth middle layer annular waveguide 74 and the seventeenth middle layer annular waveguide 75 are both 18nm, the inner diameter of the sixteenth middle layer annular waveguide 74 is 99nm, the outer diameter thereof is 100nm, the inner diameter of the seventeenth middle layer annular waveguide 75 is 70nm, the outer diameter thereof is 71nm, the eighteenth middle layer annular waveguide 76 is made of graphene, the thickness of the eighteenth middle layer annular waveguide 76 is 1nm, the inner diameter of the eighteenth middle layer annular waveguide 76 is 70nm, the outer diameter thereof is 100nm, the material of the nineteenth middle layer annular waveguide 77 and the twenty middle layer annular waveguide 78 is silicon dioxide, the thickness of the nineteenth middle layer annular waveguide 77 and the twenty middle layer annular waveguide 78 is 18nm, the inner diameter of the nineteenth middle layer annular waveguide 77 is 99nm, the outer diameter thereof is 100nm, the inner diameter of the twenty middle layer annular waveguide 78 is 70nm, the outer diameter thereof is 71nm, the material of the fourth upper layer annular waveguide 79, the thickness of the fourth upper layer annular waveguide 79 is 20nm, the inner diameter of the fourth upper layer annular waveguide 79 is 70nm, the outer diameter is 100nm, the centers of circles of the fourth bottom layer annular waveguide 73, the sixteenth middle layer annular waveguide 74, the seventeenth middle layer annular waveguide 75, the eighteenth middle layer annular waveguide 76, the nineteenth middle layer annular waveguide 77, the twentieth middle layer annular waveguide 78 and the fourth upper layer annular waveguide 79 are positioned on the same straight line, the fourth bottom layer annular waveguide 73 is positioned at the bottommost layer, the sixteenth middle layer annular waveguide 74 and the seventeenth middle layer annular waveguide 75 are arranged on the fourth bottom layer annular waveguide 73 at intervals, the sixteenth middle layer annular waveguide 74 is concentrically arranged on the inner side of the seventeenth middle layer annular waveguide 75, the eighteenth middle layer annular waveguide 76 is arranged on the sixteenth middle layer annular waveguide 74 and the seventeenth middle layer annular waveguide 75, the nineteenth middle layer annular waveguide 77 and the twenty middle layer annular waveguide 78 are arranged on the eighteenth middle layer annular waveguide 76 at intervals, and a nineteenth-middle-layer ring waveguide 77 is concentrically disposed inside the twentieth-middle-layer ring waveguide 78, and a fourth upper-layer ring waveguide 79 is disposed on the nineteenth-middle-layer ring waveguide 77 and the twentieth-middle-layer ring waveguide 78.
In this embodiment, the substrate 1 is made of silicon, the thickness of the substrate 1 is 20nm, the buffer layer 2 is made of silicon dioxide, and the thickness of the buffer layer 2 is 20 nm.
The following software simulation verifies the benefits of the SWAP gate based on the graphene surface plasmon polariton:
when the chemical potential of the middle layer material graphene of the first straight waveguide, the second straight waveguide, the third straight waveguide, the first arc waveguide, the second arc waveguide, the third arc waveguide, the fourth arc waveguide, the first micro-ring resonant cavity, the second micro-ring resonant cavity, the third micro-ring resonant cavity and the fourth micro-ring resonant cavity is 0.644eV, the first Output end Output of the SWAP gate based on the graphene surface plasmon polariton is adopted1And a second Output terminal Output2Is shown in fig. 3(a), and the solid square dot curve in fig. 3(a) represents the first Output end of the SWAP gate1Solid circles indicate the second Output of the SWAP gate2The transmission line of (1). As can be seen from the analysis of fig. 3 (a): when the operating frequency is 29.5THz and the operand is '00', the first Output terminal Output of the SWAP gate1The logical operation result of (1) is '0', the Output is-29.95 dB, and the second Output end of the SWAP gate2The logical operation result of (1) is '0', and the output is-34.81 dB.
When the first straight waveguide, the second straight waveguide, the third straight waveguide, the first arc-shaped waveguide, the second arc-shaped waveguide and the third arc are arrangedWhen the chemical potential of the middle layer material graphene of the shape waveguide, the fourth arc waveguide, the first micro-ring resonant cavity, the second micro-ring resonant cavity and the third micro-ring resonant cavity is 0.644eV, and the chemical potential of the middle layer material graphene of the fourth micro-ring resonant cavity is 0.95eV, the transmission lines of the first Output end and the second Output end of the SWAP gate based on the graphene surface plasmon polariton are shown in fig. 3(b), and the solid square point curve in fig. 3(b) represents the first Output end Output of the SWAP gate1Solid circles indicate the second Output of the SWAP gate2The transmission line of (1). Analysis of FIG. 3(b) reveals that: when the operating frequency is 29.5THz and the operand is '01', the first Output terminal of the SWAP gate1The logical operation result of (1) is '1', the Output is-5.94 dB, and the second Output end of the SWAP gate is Output2The logical operation result of (d) is '0', and the output is-25.50 dB.
When the chemical potential of the middle layer material graphene of the first straight waveguide, the second straight waveguide, the third straight waveguide, the first arc waveguide, the second arc waveguide, the third arc waveguide, the fourth arc waveguide, the second micro-ring resonant cavity, the third micro-ring resonant cavity and the fourth micro-ring resonant cavity is 0.644eV, and the chemical potential of the middle layer material graphene of the first micro-ring resonant cavity is 0.95eV, the transmission lines of the first Output end and the second Output end of the SWAP gate based on the graphene surface plasmon polariton of the invention are shown in fig. 3(c), and the solid square point curve in fig. 3(c) represents the first Output end Output of the SWAP gate1Solid circles indicate the second Output of the SWAP gate2The transmission line of (1). Analysis of FIG. 3(c) reveals that: when the operating frequency is 29.5THz and the operand is '10', the first Output terminal of the SWAP gate1The logic operation result of (1) is that the Output of '0' is-22.95 dB, and the second Output end of the SWAP gate is Output2The result of the logical operation of (c) is a '1' output of-6.05 dB.
When the chemical potential of the middle layer material graphene of the first straight waveguide, the second straight waveguide, the third straight waveguide, the first arc-shaped waveguide, the second arc-shaped waveguide, the third arc-shaped waveguide, the fourth arc-shaped waveguide, the second micro-ring resonant cavity and the third micro-ring resonant cavity is 0.644eV, the first micro-ring resonant cavity and the fourth micro-ring resonant cavity are tunedWhen the chemical potential of the graphene as the middle layer material of the resonator is 0.95eV, transmission lines of the first Output end and the second Output end of the SWAP gate based on the graphene surface plasmon polariton are shown in fig. 3(d), and a solid square point curve in fig. 3(d) represents the first Output end Output of the SWAP gate1Solid circles indicate the second Output of the SWAP gate2The transmission line of (1). Analysis of FIG. 3(d) reveals that: when the operating frequency is 29.5THz and the operand is '11', the first Output terminal of the SWAP gate1The logic operation result of (1) is that the Output of the Output is-6.52 dB, and the second Output end of the SWAP gate2The result of the logical operation of (c) is a '1' output of-6.45 dB.
Analyzing fig. 3(a), fig. 3(b), fig. 3(c), and fig. 3(d), it can be known that the SWAP gate based on the graphene surface plasmon polariton of the present invention can accurately achieve the corresponding logical operation result, the worst crosstalk reaches-16.90 dB, and the worst extinction ratio reaches 16.43 dB.
In summary, the design of the SWAP gate based on the graphene surface plasmon polariton adopts the cascade connection of four micro-ring resonators, the designed structure is simple and compact, and reference is provided for further designing more complex logic devices. Meanwhile, the SWAP gate based on the graphene surface plasmon polaritons meets the propagation condition of the graphene surface plasmon polaritons under the matching of the structures of the first straight waveguide, the second straight waveguide, the third straight waveguide, the first micro-ring resonant cavity, the second micro-ring resonant cavity, the third micro-ring resonant cavity, the fourth micro-ring resonant cavity, the first arc-shaped waveguide, the second arc-shaped waveguide, the third arc-shaped waveguide and the fourth arc-shaped waveguide, so that the size of the device is greatly reduced, and the device is more favorable for on-chip integration.

Claims (3)

1. A SWAP gate based on graphene surface plasmons is characterized by comprising a substrate, a buffer layer, a first straight waveguide, a second straight waveguide, a third straight waveguide, a first arc-shaped waveguide, a second arc-shaped waveguide, a third arc-shaped waveguide, a fourth arc-shaped waveguide, a first micro-ring resonant cavity, a second micro-ring resonant cavity, a third micro-ring resonant cavity and a fourth micro-ring resonant cavity; the substrate and the buffer layer are both in a cuboid structure, the size of the long edge of the base body is equal to that of the long edge of the buffer layer, the size of the wide edge of the substrate is equal to that of the wide edge of the buffer layer, and the buffer layer is paved on the substrate to completely cover the upper surface of the substrate; the long side direction of the buffer layer is taken as the left-right direction, and the wide side direction is taken as the front-back direction;
the first straight waveguide, the second straight waveguide and the third straight waveguide are respectively tiled on the upper surface of the buffer layer, the first straight waveguide, the second straight waveguide and the third straight waveguide are respectively parallel to the long side of the buffer layer, the second straight waveguide is positioned on the front side of the first straight waveguide, the widths of the first straight waveguide, the second straight waveguide and the third straight waveguide are all 30nm, the length of the first straight waveguide is 100nm, the length of the second straight waveguide is 850nm, the length of the third straight waveguide is 850nm, the first micro-ring resonator, the second micro-ring resonator, the third micro-ring resonator and the fourth micro-ring resonator are respectively tiled on the upper surface of the buffer layer, and the first micro-ring resonator is positioned on the front side of the second straight waveguide, if the first micro-ring resonator is shifted backward by 20nm, the second straight waveguide will be tangent to the outer wall of the first micro-ring resonator, the second micro-ring resonator and the third micro-ring resonator are respectively located between the second straight waveguide and the third straight waveguide, and the second micro-ring resonator is located at the front side of the third micro-ring resonator, if the second micro-ring resonator is shifted forward by 2nm, the second straight waveguide will be tangent to the outer wall of the second micro-ring resonator, if the second micro-ring resonator is shifted backward by 4nm, the outer wall of the second micro-ring resonator will be tangent to the outer wall of the third micro-ring resonator, if the third micro-ring resonator is shifted backward by 2nm, the third straight waveguide will be tangent to the outer wall of the third micro-ring resonator, and the fourth micro-ring resonator is located at the rear side of the third straight waveguide, if the fourth micro-ring resonant cavity translates forward by 20nm, the third straight waveguide is tangent to the outer wall of the fourth micro-ring resonant cavity, the distance between the centers of the first micro-ring resonant cavity and the fourth micro-ring resonant cavity is 708nm, and the distance between the centers of the second micro-ring resonant cavity and the third micro-ring resonant cavity is 204 nm; the connecting line of the circle center of the first micro-ring resonant cavity and the circle center of the fourth micro-ring resonant cavity, and the connecting line of the circle center of the second micro-ring resonant cavity and the circle center of the third micro-ring resonant cavity are respectively parallel to the wide side of the buffer layer, the inner ring radius of the first micro-ring resonant cavity, the second micro-ring resonant cavity, the third micro-ring resonant cavity and the fourth micro-ring resonant cavity is 70nm, and the outer ring radius is 100 nm; the inner diameters of the first arc-shaped waveguide, the second arc-shaped waveguide, the third arc-shaped waveguide and the fourth arc-shaped waveguide are all 94.5nm, and the outer diameters are all 124.5 nm; the left end of the second straight waveguide is connected with the right end of the first arc waveguide, the rear end of the first arc waveguide is connected with the front end of the second arc waveguide, the left end of the second arc waveguide is connected with the right end of the first straight waveguide, the left end of the third arc waveguide is connected with the right end of the first straight waveguide, the rear end of the third arc waveguide is connected with the front end of the fourth arc waveguide, the right end of the fourth arc waveguide is connected with the left end of the third straight waveguide, the left end of the first straight waveguide is the input end of the SWAP gate, the right end of the second straight waveguide is the first output end of the SWAP gate, and the right end of the third straight waveguide is the second output end of the SWAP gate.
2. The graphene surface plasmon based SWAP gate according to claim 1, wherein the first straight waveguide is formed by connecting a first bottom straight waveguide, a first middle straight waveguide, a second middle straight waveguide, a third middle straight waveguide, a fourth middle straight waveguide, a fifth middle straight waveguide and a first upper straight waveguide through a CMOS compatible process, the first bottom straight waveguide is made of silicon dioxide, the first bottom straight waveguide is 20nm thick and 30nm wide, the first middle straight waveguide and the second middle straight waveguide are made of silicon dioxide, the first middle straight waveguide and the second middle straight waveguide are both 18nm thick and 1nm wide, the third middle straight waveguide is made of graphene, the third middle straight waveguide is 1nm thick and 30nm wide, the fourth middle layer straight waveguide and the fifth middle layer straight waveguide are made of silicon dioxide, the fourth middle layer straight waveguide and the fifth middle layer straight waveguide are both 18nm in thickness and 1nm in width, the first upper layer straight waveguide is made of silicon dioxide, the first upper layer straight waveguide is 20nm in thickness and 30nm in width, the first bottom layer straight waveguide is positioned at the bottommost layer, the first middle layer straight waveguide and the second middle layer straight waveguide are parallelly arranged on the first bottom layer straight waveguide at intervals, the distance between the first middle layer straight waveguide and the second middle layer straight waveguide is 28nm, the third middle layer straight waveguide is arranged on the first middle layer straight waveguide and the second middle layer straight waveguide, and the fourth middle layer straight waveguide and the fifth middle layer straight waveguide are parallelly arranged on the third middle layer straight waveguide at intervals, the distance between the fourth middle layer straight waveguide and the fifth middle layer straight waveguide is 28nm, and the first upper layer straight waveguide is arranged on the fourth middle layer straight waveguide and the fifth middle layer straight waveguide;
the second straight waveguide is formed by connecting a second bottom layer straight waveguide, a sixth middle layer straight waveguide, a seventh middle layer straight waveguide, an eighth middle layer straight waveguide, a ninth middle layer straight waveguide, a tenth middle layer straight waveguide and a second upper layer straight waveguide through a CMOS compatible process, the second bottom layer straight waveguide is made of silicon dioxide, the second bottom layer straight waveguide is 20nm in thickness and 30nm in width, the sixth middle layer straight waveguide and the seventh middle layer straight waveguide are made of silicon dioxide, the sixth middle layer straight waveguide and the seventh middle layer straight waveguide are both 18nm in thickness and 1nm in width, the eighth middle layer straight waveguide is made of graphene, the eighth middle layer straight waveguide is 1nm in thickness and 30nm in width, and the ninth middle layer straight waveguide and the tenth middle layer straight waveguide are both made of silicon dioxide, the ninth middle layer straight waveguide and the tenth middle layer straight waveguide are 18nm in thickness and 1nm in width, the second upper layer straight waveguide is made of silicon dioxide, the second upper layer straight waveguide is 20nm in thickness and 30nm in width, the second bottom layer straight waveguide is positioned at the bottommost layer, the sixth middle layer straight waveguide and the seventh middle layer straight waveguide are parallelly arranged on the second bottom layer straight waveguide at intervals, the distance between the sixth middle layer straight waveguide and the seventh middle layer straight waveguide is 28nm, the eighth middle layer straight waveguide is arranged on the sixth middle layer straight waveguide and the seventh middle layer straight waveguide, the ninth middle layer straight waveguide and the tenth middle layer straight waveguide are parallelly arranged on the eighth middle layer straight waveguide at intervals, and the distance between the ninth middle layer straight waveguide and the tenth middle layer straight waveguide is 28nm, the second upper layer straight waveguide is arranged on the ninth middle layer straight waveguide and the tenth middle layer straight waveguide;
the third straight waveguide is formed by connecting a third bottom layer straight waveguide, an eleventh middle layer straight waveguide, a twelfth middle layer straight waveguide, a thirteenth middle layer straight waveguide, a fourteenth middle layer straight waveguide, a fifteenth middle layer straight waveguide and a third upper layer straight waveguide through a CMOS compatible process, the third bottom layer straight waveguide is made of silicon dioxide, the third bottom layer straight waveguide is 20nm in thickness and 30nm in width, the eleventh middle layer straight waveguide and the twelfth middle layer straight waveguide are made of silicon dioxide, the eleventh middle layer straight waveguide and the twelfth middle layer straight waveguide are both 18nm in thickness and 1nm in width, the thirteenth middle layer straight waveguide is made of graphene, the thirteenth middle layer straight waveguide is 1nm in thickness and 30nm in width, and the fourteenth middle layer straight waveguide and the fifteenth middle layer straight waveguide are both made of silicon dioxide, the fourteenth middle layer straight waveguide and the fifteenth middle layer straight waveguide are 18nm in thickness and 1nm in width, the third upper layer straight waveguide is made of silicon dioxide, the third upper layer straight waveguide is 20nm in thickness and 30nm in width, the third bottom layer straight waveguide is positioned at the bottommost layer, the eleventh middle layer straight waveguide and the twelfth middle layer straight waveguide are parallelly arranged on the third bottom layer straight waveguide at intervals, the distance between the eleventh middle layer straight waveguide and the twelfth middle layer straight waveguide is 28nm, the thirteenth middle layer straight waveguide is arranged on the eleventh middle layer straight waveguide and the twelfth middle layer straight waveguide, the fourteenth middle layer straight waveguide and the fifteenth middle layer straight waveguide are parallelly arranged on the thirteenth middle layer straight waveguide at intervals, and the distance between the fourteenth straight waveguide and the fifteenth middle layer straight waveguide is 28nm, the third upper layer straight waveguide is arranged on the fourteenth middle layer straight waveguide and the fifteenth middle layer straight waveguide;
the first arc waveguide is formed by connecting a first bottom layer arc waveguide, a first middle layer arc waveguide, a second middle layer arc waveguide, a third middle layer arc waveguide, a fourth middle layer arc waveguide, a fifth middle layer arc waveguide and a first upper layer arc waveguide through a CMOS compatible process, the radians of the first bottom layer arc waveguide, the first middle layer arc waveguide, the second middle layer arc waveguide, the third middle layer arc waveguide, the fourth middle layer arc waveguide, the fifth middle layer arc waveguide and the first upper layer arc waveguide are all 90 degrees, the first bottom layer arc waveguide is made of silicon dioxide, the thickness of the first bottom layer arc waveguide is 20nm, the inner diameter of the first bottom layer arc waveguide is 94.5nm, the outer diameter of the first bottom layer arc waveguide is 124.5nm, and the first middle layer arc waveguide and the second middle layer arc waveguide are both made of silicon dioxide, the thickness of the first middle layer arc waveguide and the second middle layer arc waveguide are both 18nm, the inner diameter of the first middle layer arc waveguide is 123.5nm, the outer diameter of the first middle layer arc waveguide is 124.5nm, the inner diameter of the second middle layer arc waveguide is 94.5nm, the outer diameter of the second middle layer arc waveguide is 95.5nm, the material of the third middle layer arc waveguide is graphene, the thickness of the third middle layer arc waveguide is 1nm, the inner diameter of the third middle layer arc waveguide is 94.5nm, the outer diameter of the third middle layer arc waveguide is 124.5nm, the material of the fourth middle layer arc waveguide and the material of the fifth middle layer arc waveguide are both silica, the thickness of the fourth middle layer arc waveguide and the thickness of the fifth middle layer arc waveguide are both 18nm, the inner diameter of the third middle layer arc waveguide is 123.5nm, the outer diameter of the third middle layer arc waveguide is 124.5nm, the inner diameter of the fourth middle layer arc waveguide is 94.5nm, the outer diameter of the fourth middle layer arc waveguide is 95.5nm, and the material of the first upper layer arc, the thickness of the first upper layer arc waveguide is 20nm, the inner diameter of the first upper layer arc waveguide is 94.5nm, the outer diameter of the first upper layer arc waveguide is 124.5nm, the circle centers of the first bottom layer arc waveguide, the first middle layer arc waveguide, the second middle layer arc waveguide, the third middle layer arc waveguide, the fourth middle layer arc waveguide, the fifth middle layer arc waveguide and the first upper layer arc waveguide are positioned on the same straight line, the first bottom layer arc waveguide is positioned on the bottommost layer, the first middle layer arc waveguide and the second middle layer arc waveguide are arranged on the first bottom layer arc waveguide in parallel at intervals, the first middle layer arc waveguide is concentrically arranged on the inner side of the second middle layer arc waveguide, and the third middle layer arc waveguide is arranged on the first middle layer arc waveguide and the second middle layer arc waveguide, the fourth middle layer arc waveguide and the fifth middle layer arc waveguide are arranged on the third middle layer arc waveguide at intervals in parallel, the fourth middle layer arc waveguide is concentrically arranged on the inner side of the fifth middle layer arc waveguide, and the first upper layer arc waveguide is arranged on the fourth middle layer arc waveguide and the fifth middle layer arc waveguide;
the second arc waveguide is formed by connecting a second bottom layer arc waveguide, a sixth middle layer arc waveguide, a seventh middle layer arc waveguide, an eighth middle layer arc waveguide, a ninth middle layer arc waveguide, a tenth middle layer arc waveguide and a second upper layer arc waveguide through a CMOS compatible process, the radians of the second bottom layer arc waveguide, the sixth middle layer arc waveguide, the seventh middle layer arc waveguide, the eighth middle layer arc waveguide, the ninth middle layer arc waveguide, the tenth middle layer arc waveguide and the second upper layer arc waveguide are all 90 degrees, the second bottom layer arc waveguide is made of silicon dioxide, the thickness of the second bottom layer arc waveguide is 20n, the inner diameter of the second bottom layer arc waveguide is 94.5nm, the outer diameter of the second bottom layer arc waveguide is 124.5nm, and the materials of the sixth middle layer arc waveguide and the seventh middle layer arc waveguide are both silicon dioxide, the thickness of the sixth middle layer arc waveguide and the thickness of the seventh middle layer arc waveguide are both 18nm, the inner diameter of the sixth middle layer arc waveguide is 123.5nm, the outer diameter of the sixth middle layer arc waveguide is 124.5nm, the inner diameter of the seventh middle layer arc waveguide is 94.5nm, the outer diameter of the seventh middle layer arc waveguide is 95.5nm, the material of the eighth middle layer arc waveguide is graphene, the thickness of the eighth middle layer arc waveguide is 1nm, the inner diameter of the eighth middle layer arc waveguide is 94.5nm, the outer diameter of the eighth middle layer arc waveguide is 124.5nm, the material of the ninth middle layer arc waveguide and the tenth middle layer arc waveguide are both silica, the thickness of the ninth middle layer arc waveguide and the tenth middle layer arc waveguide are both 18nm, the inner diameter of the eighth middle layer arc waveguide is 123.5nm, the outer diameter of the eighth middle layer arc waveguide is 124.5nm, the inner diameter of the ninth middle layer arc waveguide is 94.5nm, the outer diameter of the ninth middle layer arc waveguide is 95.5nm, and the material of the second upper layer arc waveguide is, the thickness of the second upper layer arc waveguide is 20nm, the inner diameter of the second upper layer arc waveguide is 94.5nm, the outer diameter of the second upper layer arc waveguide is 124.5nm, the circle centers of the second bottom layer arc waveguide, the sixth middle layer arc waveguide, the seventh middle layer arc waveguide, the eighth middle layer arc waveguide, the ninth middle layer arc waveguide, the tenth middle layer arc waveguide and the second upper layer arc waveguide are positioned on the same straight line, the second bottom layer arc waveguide is positioned on the bottommost layer, the sixth middle layer arc waveguide and the seventh middle layer arc waveguide are arranged on the second bottom layer arc waveguide in parallel at intervals, the sixth middle layer arc waveguide is concentrically arranged on the inner side of the seventh middle layer arc waveguide, and the eighth middle layer arc waveguide is arranged on the sixth middle layer arc waveguide and the seventh middle layer arc waveguide, the ninth middle layer arc waveguide and the tenth middle layer arc waveguide are arranged on the eighth middle layer arc waveguide at intervals in parallel, the ninth middle layer arc waveguide is concentrically arranged on the inner side of the tenth middle layer arc waveguide, and the second upper layer arc waveguide is arranged on the ninth middle layer arc waveguide and the tenth middle layer arc waveguide;
the third arc waveguide is formed by connecting a third bottom layer arc waveguide, an eleventh middle layer arc waveguide, a twelfth middle layer arc waveguide, a thirteenth middle layer arc waveguide, a fourteenth middle layer arc waveguide, a fifteenth middle layer arc waveguide and a third upper layer arc waveguide through a CMOS compatible process, the radians of the third bottom layer arc waveguide, the eleventh middle layer arc waveguide, the twelfth middle layer arc waveguide, the thirteenth middle layer arc waveguide, the fourteenth middle layer arc waveguide, the fifteenth middle layer arc waveguide and the third upper layer arc waveguide are all 90 degrees, the third bottom layer arc waveguide is made of silicon dioxide, the thickness of the third bottom layer arc waveguide is 20n, the inner diameter of the third bottom layer arc waveguide is 94.5nm, the outer diameter of the third bottom layer arc waveguide is 124.5nm, the eleventh middle layer arc waveguide and the twelfth middle layer arc waveguide are made of silicon dioxide, the thickness of the eleventh middle layer arc waveguide and the thickness of the twelfth middle layer arc waveguide are both 18nm, the inner diameter of the eleventh middle layer arc waveguide is 123.5nm, the outer diameter of the eleventh middle layer arc waveguide is 124.5nm, the inner diameter of the twelfth middle layer arc waveguide is 94.5nm, the outer diameter of the twelfth middle layer arc waveguide is 95.5nm, the material of the thirteenth middle layer arc waveguide is graphene, the thickness of the thirteenth middle layer arc waveguide is 1nm, the inner diameter of the thirteenth middle layer arc waveguide is 94.5nm, the outer diameter of the thirteenth middle layer arc waveguide is 124.5nm, the material of the fourteenth middle layer arc waveguide and the material of the fifteenth middle layer arc waveguide are both silicon dioxide, the thickness of the fourteenth middle layer arc waveguide and the thickness of the fifteenth middle layer arc waveguide are both 18nm, the inner diameter of the thirteenth middle layer arc waveguide is 123.5nm, the outer diameter of the fourteenth middle layer arc waveguide is 124.5nm, the inner diameter of the fourteenth middle layer arc waveguide is 94.5nm, the outer diameter of the third upper layer arc waveguide is 95.5nm, the material of the third upper layer arc waveguide is silicon dioxide, the thickness of the third upper layer arc waveguide is 20nm, the inner diameter of the third upper layer arc waveguide is 94.5nm, the outer diameter of the third upper layer arc waveguide is 124.5nm, the centers of the third bottom layer arc waveguide, the eleventh middle layer arc waveguide, the twelfth middle layer arc waveguide, the thirteenth middle layer arc waveguide, the fourteenth middle layer arc waveguide, the fifteenth middle layer arc waveguide and the third upper layer arc waveguide are positioned on the same straight line, the third bottom layer arc waveguide is positioned on the bottommost layer, the eleventh middle layer arc waveguide and the twelfth middle layer arc waveguide are parallelly arranged on the third bottom layer arc waveguide at intervals, and the eleventh middle layer arc waveguide is concentrically arranged on the inner side of the twelfth middle layer arc waveguide, the thirteenth middle layer arc waveguide is arranged on the eleventh middle layer arc waveguide and the twelfth middle layer arc waveguide, the fourteenth middle layer arc waveguide and the fifteenth middle layer arc waveguide are arranged on the thirteenth middle layer arc waveguide at intervals in parallel, the fourteenth middle layer arc waveguide is concentrically arranged on the inner side of the fifteenth middle layer arc waveguide, and the third upper layer arc waveguide is arranged on the fourteenth middle layer arc waveguide and the fifteenth middle layer arc waveguide;
the fourth arc waveguide is formed by connecting a fourth bottom layer arc waveguide, a sixteenth middle layer arc waveguide, a seventeenth middle layer arc waveguide, an eighteenth middle layer arc waveguide, a nineteenth middle layer arc waveguide, a twentieth middle layer arc waveguide and a fourth upper layer arc waveguide through a CMOS compatible process, the radians of the fourth bottom layer arc waveguide, the sixteenth middle layer arc waveguide, the seventeenth middle layer arc waveguide, the eighteenth middle layer arc waveguide, the nineteenth middle layer arc waveguide, the twentieth middle layer arc waveguide and the fourth upper layer arc waveguide are all 90 degrees, the fourth bottom layer arc waveguide is made of silicon dioxide, the fourth bottom layer arc waveguide is 20n thick, the fourth bottom layer arc waveguide is 94.5nm in inner diameter and 124.5nm in outer diameter, the sixteenth middle layer arc waveguide and the seventeenth middle layer arc waveguide are made of silicon dioxide, the thickness of the sixteenth middle layer arc-shaped waveguide and the seventeenth middle layer arc-shaped waveguide are both 18nm, the inner diameter of the sixteenth middle layer arc-shaped waveguide is 124.5nm, the outer diameter of the sixteenth middle layer arc-shaped waveguide is 125.5nm, the inner diameter of the seventeenth middle layer arc-shaped waveguide is 94.5nm, the outer diameter of the seventeenth middle layer arc-shaped waveguide is 95.5nm, the eighteenth middle layer arc-shaped waveguide is made of graphene, the thickness of the eighteenth middle layer arc-shaped waveguide is 1nm, the inner diameter of the eighteenth middle layer arc-shaped waveguide is 94.5nm, the outer diameter of the eighteenth middle layer arc-shaped waveguide is 124.5nm, the nineteenth middle layer arc-shaped waveguide and the twenty middle layer arc-shaped waveguide are both made of silicon dioxide, the thickness of the nineteenth middle layer arc-shaped waveguide and the twenty middle layer arc-shaped waveguide is both 18nm, the inner diameter of the eighteenth middle layer arc-shaped waveguide is 123.5nm, the outer, the outer diameter of the fourth upper layer arc waveguide is 95.5nm, the material of the fourth upper layer arc waveguide is silicon dioxide, the thickness of the fourth upper layer arc waveguide is 20nm, the inner diameter of the fourth upper layer arc waveguide is 94.5nm, the outer diameter of the fourth upper layer arc waveguide is 124.5nm, the centers of the fourth bottom layer arc waveguide, the sixteenth middle layer arc waveguide, the seventeenth middle layer arc waveguide, the eighteenth middle layer arc waveguide, the nineteenth middle layer arc waveguide, the twentieth middle layer arc waveguide and the fourth upper layer arc waveguide are positioned on the same straight line, the fourth bottom layer arc waveguide is positioned on the bottommost layer, the sixteenth middle layer arc waveguide and the seventeenth middle layer arc waveguide are arranged on the fourth bottom layer arc waveguide at intervals in parallel, and the sixteenth middle layer arc waveguide is concentrically arranged on the inner side of the seventeenth arc waveguide, the eighteenth middle layer arc waveguide is arranged on the sixteenth middle layer arc waveguide and the seventeenth middle layer arc waveguide, the nineteenth middle layer arc waveguide and the twentieth middle layer arc waveguide are arranged on the eighteenth middle layer arc waveguide at intervals in parallel, the nineteenth middle layer arc waveguide is concentrically arranged on the inner side of the twentieth middle layer arc waveguide, and the fourth upper layer arc waveguide is arranged on the nineteenth middle layer arc waveguide and the twentieth middle layer arc waveguide;
the first micro-ring resonant cavity is formed by connecting a first bottom layer annular waveguide, a first middle layer annular waveguide, a second middle layer annular waveguide, a third middle layer annular waveguide, a fourth middle layer annular waveguide, a fifth middle layer annular waveguide and a first upper layer annular waveguide through a CMOS (complementary metal oxide semiconductor) compatible process, the radians of the first bottom layer annular waveguide, the first middle layer annular waveguide, the second middle layer annular waveguide, the third middle layer annular waveguide, the fourth middle layer annular waveguide, the fifth middle layer annular waveguide and the first upper layer annular waveguide are all 90 degrees, the first bottom layer annular waveguide is made of silicon dioxide, the thickness of the first bottom layer annular waveguide is 20n, the inner diameter of the first bottom layer annular waveguide is 70nm, the outer diameter of the first bottom layer annular waveguide is 100nm, and the materials of the first middle layer annular waveguide and the second middle layer annular waveguide are both made of silicon dioxide, the thickness of the first middle layer annular waveguide and the thickness of the second middle layer annular waveguide are both 18nm, the inner diameter of the first middle layer annular waveguide is 99nm, the outer diameter of the first middle layer annular waveguide is 100nm, the inner diameter of the second middle layer annular waveguide is 70nm, the outer diameter of the second middle layer annular waveguide is 71nm, the material of the third middle layer annular waveguide is graphene, the thickness of the third middle layer annular waveguide is 1nm, the inner diameter of the third middle layer annular waveguide is 70nm, the outer diameter of the third middle layer annular waveguide is 100nm, the material of the fourth middle layer annular waveguide and the material of the fifth middle layer annular waveguide are both silicon dioxide, the thickness of the fourth middle layer annular waveguide and the thickness of the fifth middle layer annular waveguide are both 18nm, the inner diameter of the third middle layer annular waveguide is 99nm, the outer diameter of the third middle layer annular waveguide is 100nm, the inner diameter of the fourth middle layer annular waveguide is 70nm, the outer diameter of the fourth middle layer annular waveguide is 71nm, and the material of the, the thickness of the first upper layer annular waveguide is 20nm, the inner diameter of the first upper layer annular waveguide is 70nm, the outer diameter of the first upper layer annular waveguide is 100nm, the circle centers of the first bottom layer annular waveguide, the first middle layer annular waveguide, the second middle layer annular waveguide, the third middle layer annular waveguide, the fourth middle layer annular waveguide, the fifth middle layer annular waveguide and the first upper layer annular waveguide are positioned on the same straight line, the first bottom layer annular waveguide is positioned at the bottommost layer, the first middle layer annular waveguide and the second middle layer annular waveguide are arranged on the first bottom layer annular waveguide at intervals, the first middle layer annular waveguide is concentrically arranged at the inner side of the second middle layer annular waveguide, and the third middle layer annular waveguide is arranged on the first middle layer annular waveguide and the second middle layer annular waveguide, the fourth middle-layer annular waveguide and the fifth middle-layer annular waveguide are arranged on the third middle-layer annular waveguide at intervals, the fourth middle-layer annular waveguide is concentrically arranged on the inner side of the fifth middle-layer annular waveguide, and the first upper-layer annular waveguide is arranged on the fourth middle-layer annular waveguide and the fifth middle-layer annular waveguide;
the second micro-ring resonant cavity is formed by connecting a second bottom layer annular waveguide, a sixth middle layer annular waveguide, a seventh middle layer annular waveguide, an eighth middle layer annular waveguide, a ninth middle layer annular waveguide, a tenth middle layer annular waveguide and a second upper layer annular waveguide through a CMOS compatible process, the radians of the second bottom layer annular waveguide, the sixth middle layer annular waveguide, the seventh middle layer annular waveguide, the eighth middle layer annular waveguide, the ninth middle layer annular waveguide, the tenth middle layer annular waveguide and the second upper layer annular waveguide are all 90 degrees, the second bottom layer annular waveguide is made of silicon dioxide, the thickness of the second bottom layer annular waveguide is 20n, the inner diameter of the second bottom layer annular waveguide is 70nm, the outer diameter of the second bottom layer annular waveguide is 100nm, and the materials of the sixth middle layer annular waveguide and the seventh middle layer annular waveguide are both silicon dioxide, the thickness of the sixth middle layer annular waveguide and the thickness of the seventh middle layer annular waveguide are both 18nm, the inner diameter of the sixth middle layer annular waveguide is 99nm, the outer diameter of the sixth middle layer annular waveguide is 100nm, the inner diameter of the seventh middle layer annular waveguide is 70nm, the outer diameter of the seventh middle layer annular waveguide is 71nm, the material of the eighth middle layer annular waveguide is graphene, the thickness of the eighth middle layer annular waveguide is 1nm, the inner diameter of the eighth middle layer annular waveguide is 70nm, the outer diameter of the eighth middle layer annular waveguide is 100nm, the material of the ninth middle layer annular waveguide and the material of the tenth middle layer annular waveguide are both silicon dioxide, the thickness of the ninth middle layer annular waveguide and the thickness of the tenth middle layer annular waveguide are both 18nm, the inner diameter of the ninth middle layer annular waveguide is 99nm, the outer diameter of the tenth middle layer annular waveguide is 70nm, the outer diameter of the tenth middle layer annular waveguide is 71nm, and the material of the second upper layer annular waveguide is silicon dioxide, the thickness of the second upper layer annular waveguide is 20nm, the inner diameter of the second upper layer annular waveguide is 70nm, the outer diameter of the second upper layer annular waveguide is 100nm, the circle centers of the second bottom layer annular waveguide, the sixth middle layer annular waveguide, the seventh middle layer annular waveguide, the eighth middle layer annular waveguide, the ninth middle layer annular waveguide, the tenth middle layer annular waveguide and the second upper layer annular waveguide are positioned on the same straight line, the second bottom layer annular waveguide is positioned at the bottommost layer, the sixth middle layer annular waveguide and the seventh middle layer annular waveguide are arranged on the second bottom layer annular waveguide at intervals, the sixth middle layer annular waveguide is concentrically arranged at the inner side of the seventh middle layer annular waveguide, the eighth middle layer annular waveguide is arranged on the sixth middle layer annular waveguide and the seventh middle layer annular waveguide, the ninth middle-layer annular waveguide and the tenth middle-layer annular waveguide are arranged on the eighth middle-layer annular waveguide at intervals, the ninth middle-layer annular waveguide is concentrically arranged on the inner side of the tenth middle-layer annular waveguide, and the second upper-layer annular waveguide is arranged on the ninth middle-layer annular waveguide and the tenth middle-layer annular waveguide;
the third micro-ring resonant cavity is formed by connecting a third bottom layer annular waveguide, an eleventh middle layer annular waveguide, a twelfth middle layer annular waveguide, a thirteenth middle layer annular waveguide, a fourteenth middle layer annular waveguide, a fifteenth middle layer annular waveguide and a third upper layer annular waveguide through a CMOS compatible process, the radians of the third bottom layer annular waveguide, the eleventh middle layer annular waveguide, the twelfth middle layer annular waveguide, the thirteenth middle layer annular waveguide, the fourteenth middle layer annular waveguide, the fifteenth middle layer annular waveguide and the third upper layer annular waveguide are all 90 degrees, the third bottom layer annular waveguide is made of silicon dioxide, the thickness of the third bottom layer annular waveguide is 20n, the inner diameter of the third bottom layer annular waveguide is 70nm, the outer diameter of the third bottom layer annular waveguide is 100nm, and the eleventh middle layer annular waveguide and the twelfth middle layer annular waveguide are both made of silicon dioxide, the thickness of the eleventh middle layer annular waveguide and the thickness of the twelfth middle layer annular waveguide are both 18nm, the inner diameter of the eleventh middle layer annular waveguide is 99nm, the outer diameter of the eleventh middle layer annular waveguide is 100nm, the inner diameter of the twelfth middle layer annular waveguide is 70nm, the outer diameter of the twelfth middle layer annular waveguide is 71nm, the material of the thirteenth middle layer annular waveguide is graphene, the thickness of the thirteenth middle layer annular waveguide is 1nm, the inner diameter of the thirteenth middle layer annular waveguide is 70nm, the outer diameter of the thirteenth middle layer annular waveguide is 100nm, the material of the fourteenth middle layer annular waveguide and the fifteenth middle layer annular waveguide is silicon dioxide, the thickness of the fourteenth middle layer annular waveguide and the thickness of the fifteenth middle layer annular waveguide are both 18nm, the inner diameter of the fourteenth middle layer annular waveguide is 99nm, the outer diameter of the fourteenth middle layer annular waveguide is 100nm, and the inner diameter of the fifteenth middle layer annular waveguide is 70nm, the outer diameter of the third upper layer annular waveguide is 71nm, the material of the third upper layer annular waveguide is silicon dioxide, the thickness of the third upper layer annular waveguide is 20nm, the inner diameter of the third upper layer annular waveguide is 70nm, the outer diameter of the third upper layer annular waveguide is 100nm, the circle centers of the third bottom layer annular waveguide, the eleventh middle layer annular waveguide, the twelfth middle layer annular waveguide, the thirteenth middle layer annular waveguide, the fourteenth middle layer annular waveguide, the fifteenth middle layer annular waveguide and the third upper layer annular waveguide are positioned on the same straight line, the third bottom layer annular waveguide is positioned at the bottommost layer, the eleventh middle layer annular waveguide and the twelfth middle layer annular waveguide are arranged on the third bottom layer annular waveguide at intervals, and the eleventh middle layer annular waveguide is concentrically arranged at the inner side of the twelfth middle layer annular waveguide, the thirteenth middle ring waveguide is disposed on the eleventh middle ring waveguide and the twelfth middle ring waveguide, the fourteenth middle ring waveguide and the fifteenth middle ring waveguide are disposed on the thirteenth middle ring waveguide at intervals, the fourteenth middle ring waveguide is concentrically disposed on the inner side of the fifteenth middle ring waveguide, and the third upper ring waveguide is disposed on the fourteenth middle ring waveguide and the fifteenth middle ring waveguide;
the fourth micro-ring resonant cavity is formed by connecting a fourth bottom layer annular waveguide, a sixteenth middle layer annular waveguide, a seventeenth middle layer annular waveguide, an eighteenth middle layer annular waveguide, a nineteenth middle layer annular waveguide, a twentieth middle layer annular waveguide and a fourth upper layer annular waveguide through a CMOS compatible process, the radians of the fourth bottom layer annular waveguide, the sixteenth middle layer annular waveguide, the seventeenth middle layer annular waveguide, the eighteenth middle layer annular waveguide, the nineteenth middle layer annular waveguide, the twentieth middle layer annular waveguide and the fourth upper layer annular waveguide are all 90 degrees, the fourth bottom layer annular waveguide is made of silicon dioxide, the thickness of the fourth bottom layer annular waveguide is 20n, the inner diameter of the fourth bottom layer annular waveguide is 70nm, the outer diameter of the fourth bottom layer annular waveguide is 100nm, the sixteenth middle layer annular waveguide and the seventeenth annular waveguide are made of silicon dioxide, the thickness of the sixteenth middle layer annular waveguide and the seventeenth middle layer annular waveguide is 18nm, the inner diameter of the sixteenth middle layer annular waveguide is 99nm, the outer diameter of the sixteenth middle layer annular waveguide is 100nm, the inner diameter of the seventeenth middle layer annular waveguide is 70nm, the outer diameter of the seventeenth middle layer annular waveguide is 71nm, the eighteenth middle layer annular waveguide is made of graphene, the thickness of the eighteenth middle layer annular waveguide is 1nm, the inner diameter of the eighteenth middle layer annular waveguide is 70nm, the outer diameter of the eighteenth middle layer annular waveguide is 100nm, the nineteenth middle layer annular waveguide and the twenty middle layer annular waveguide are made of silicon dioxide, the thickness of the nineteenth middle layer annular waveguide and the twenty middle layer annular waveguide is 18nm, the inner diameter of the nineteenth middle layer annular waveguide is 99nm, the outer diameter of the nineteenth middle layer annular waveguide is 100nm, and the inner diameter of the twenty middle layer annular waveguide is 70nm, the outer diameter of the fourth upper layer annular waveguide is 71nm, the material of the fourth upper layer annular waveguide is silicon dioxide, the thickness of the fourth upper layer annular waveguide is 20nm, the inner diameter of the fourth upper layer annular waveguide is 70nm, the outer diameter of the fourth upper layer annular waveguide is 100nm, the circle centers of the fourth bottom layer annular waveguide, the sixteenth middle layer annular waveguide, the seventeenth middle layer annular waveguide, the eighteenth middle layer annular waveguide, the nineteenth middle layer annular waveguide, the twentieth middle layer annular waveguide and the fourth upper layer annular waveguide are positioned on the same straight line, the fourth bottom layer annular waveguide is positioned at the bottommost layer, the sixteenth middle layer annular waveguide and the seventeenth middle layer annular waveguide are arranged on the fourth bottom layer annular waveguide at intervals, and the sixteenth middle layer annular waveguide is concentrically arranged at the inner side of the seventeenth middle layer annular waveguide, the eighteenth middle layer annular waveguide is arranged on the sixteenth middle layer annular waveguide and the seventeenth middle layer annular waveguide, the nineteenth middle layer annular waveguide and the twentieth middle layer annular waveguide are arranged on the eighteenth middle layer annular waveguide at intervals, the nineteenth middle layer annular waveguide is concentrically arranged on the inner side of the twentieth middle layer annular waveguide, and the fourth upper layer annular waveguide is arranged on the nineteenth middle layer annular waveguide and the twentieth middle layer annular waveguide.
3. The graphene surface plasmon based SWAP gate of claim 1, wherein the substrate is made of silicon, the substrate is 20nm thick, the buffer layer is made of silicon dioxide, and the buffer layer is 20nm thick.
CN202010057246.8A 2020-01-17 2020-01-17 SWAP gate based on graphene surface plasmon polaritons Active CN111240124B (en)

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CN109188825A (en) * 2018-10-09 2019-01-11 宁波大学 Optics half adder based on graphene surface plasmon
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