CN111226231A - 使用主机传达的合并权重和每层指令的封装通过神经网络加速器进行的多层神经网络处理 - Google Patents

使用主机传达的合并权重和每层指令的封装通过神经网络加速器进行的多层神经网络处理 Download PDF

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CN111226231A
CN111226231A CN201880067687.7A CN201880067687A CN111226231A CN 111226231 A CN111226231 A CN 111226231A CN 201880067687 A CN201880067687 A CN 201880067687A CN 111226231 A CN111226231 A CN 111226231A
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A·吴
E·德拉耶
E·盖塞米
滕晓
J·泽杰达
吴永军
S·塞特勒
A·西拉萨奥
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Xilinx Inc
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CN201880067687.7A 2017-10-17 2018-10-16 使用主机传达的合并权重和每层指令的封装通过神经网络加速器进行的多层神经网络处理 Pending CN111226231A (zh)

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US15/785,800 2017-10-17
US15/785,800 US11620490B2 (en) 2017-10-17 2017-10-17 Multi-layer neural network processing by a neural network accelerator using host communicated merged weights and a package of per-layer instructions
PCT/US2018/056112 WO2019079319A1 (en) 2017-10-17 2018-10-16 NEURONAL MULTICOUCHE NETWORK PROCESSING BY A NEURONAL NETWORK ACCELERATOR USING CONTAINED HOST COMMUNICATION WEIGHTS AND A LAYERED INSTRUCTION PACKAGE

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CN113485762B (zh) * 2020-09-19 2024-07-26 广东高云半导体科技股份有限公司 用可配置器件卸载计算任务以提高系统性能的方法和装置
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CN114595077A (zh) * 2020-12-07 2022-06-07 辉达公司 用于神经网络计算的应用编程接口
CN113326479A (zh) * 2021-05-28 2021-08-31 哈尔滨理工大学 一种基于fpga的k均值算法的实现方法
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KR20200069338A (ko) 2020-06-16
WO2019079319A1 (en) 2019-04-25
US20190114529A1 (en) 2019-04-18
KR102578508B1 (ko) 2023-09-13
JP2020537785A (ja) 2020-12-24
EP3698296B1 (en) 2024-07-17
JP7196167B2 (ja) 2022-12-26
EP3698296A1 (en) 2020-08-26
US11620490B2 (en) 2023-04-04

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