CN111223780B - Semiconductor device and forming method thereof - Google Patents
Semiconductor device and forming method thereof Download PDFInfo
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- CN111223780B CN111223780B CN201811418850.8A CN201811418850A CN111223780B CN 111223780 B CN111223780 B CN 111223780B CN 201811418850 A CN201811418850 A CN 201811418850A CN 111223780 B CN111223780 B CN 111223780B
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- fin
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- isolation
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- 238000000034 method Methods 0.000 title claims abstract description 77
- 239000004065 semiconductor Substances 0.000 title claims abstract description 70
- 238000002955 isolation Methods 0.000 claims abstract description 119
- 238000005530 etching Methods 0.000 claims abstract description 42
- 239000000463 material Substances 0.000 claims abstract description 36
- 239000010410 layer Substances 0.000 claims description 78
- 239000000758 substrate Substances 0.000 claims description 52
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 14
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 14
- 239000011241 protective layer Substances 0.000 claims description 12
- 238000010405 reoxidation reaction Methods 0.000 claims description 5
- 238000000926 separation method Methods 0.000 claims description 4
- 239000006117 anti-reflective coating Substances 0.000 claims description 2
- 239000012141 concentrate Substances 0.000 claims 1
- 230000008569 process Effects 0.000 abstract description 32
- 230000000903 blocking effect Effects 0.000 abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 25
- 229910052710 silicon Inorganic materials 0.000 description 23
- 239000010703 silicon Substances 0.000 description 23
- 238000005229 chemical vapour deposition Methods 0.000 description 17
- 230000000694 effects Effects 0.000 description 17
- 239000011229 interlayer Substances 0.000 description 17
- 150000002500 ions Chemical class 0.000 description 14
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 14
- 239000003989 dielectric material Substances 0.000 description 13
- 229910004298 SiO 2 Inorganic materials 0.000 description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 11
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- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 6
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 6
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- 239000011368 organic material Substances 0.000 description 4
- VEALVRVVWBQVSL-UHFFFAOYSA-N strontium titanate Chemical compound [Sr+2].[O-][Ti]([O-])=O VEALVRVVWBQVSL-UHFFFAOYSA-N 0.000 description 4
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- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
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- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 2
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 2
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- 229910052757 nitrogen Inorganic materials 0.000 description 2
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 2
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- WNUPENMBHHEARK-UHFFFAOYSA-N silicon tungsten Chemical compound [Si].[W] WNUPENMBHHEARK-UHFFFAOYSA-N 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
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- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- RUDFQVOCFDJEEF-UHFFFAOYSA-N yttrium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[Y+3].[Y+3] RUDFQVOCFDJEEF-UHFFFAOYSA-N 0.000 description 2
- 229910001928 zirconium oxide Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
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- GEIAQOFPUVMAGM-UHFFFAOYSA-N Oxozirconium Chemical compound [Zr]=O GEIAQOFPUVMAGM-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- 125000005210 alkyl ammonium group Chemical group 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
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- 239000011737 fluorine Substances 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-M hydroxide Chemical compound [OH-] XLYOFNOQVPJJNP-UHFFFAOYSA-M 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
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- 238000011065 in-situ storage Methods 0.000 description 1
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- 229910052698 phosphorus Inorganic materials 0.000 description 1
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- 238000004528 spin coating Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66553—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using inside spacers, permanent or not
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
The embodiment of the invention provides a semiconductor device and a forming method thereof. According to the embodiment of the invention, before the isolation wall covering the pseudo gate structure is formed, the fin parts on the two sides of the pseudo gate structure are etched to the second height, so that the formed isolation wall can extend to the side surface of the fin part below the pseudo gate structure besides covering the side wall of the pseudo gate structure, and therefore, the gate structure, the source region and the drain region can be better isolated. And simultaneously, after forming the isolation wall, etching the fin part at the outer side of the isolation wall to a third height so as to remove isolation wall materials remained on the upper surface of the fin part and the side wall of the fin part, thereby avoiding the residual isolation wall materials from blocking the epitaxial growth of the source region and the drain region in the subsequent epitaxial growth process and ensuring the reliability of the device.
Description
Technical Field
The present disclosure relates to semiconductor technology, and more particularly, to a semiconductor device and a method for forming the same.
Background
As the size of semiconductor devices is gradually reduced, the density of fin portions in fin field effect transistors (FinField-Effect Transistor, finFET) is also increasing, and spacer material residues are easily formed on the upper surfaces and sidewalls of the fin portions during the process of forming the dummy gate spacers, which affects the reliability of the devices.
Disclosure of Invention
In view of the above, the embodiments of the present invention provide a semiconductor device and a method for forming the same, so as to solve the problem of forming spacer material residues on the upper surface and the sidewalls of the fin portion, and ensure the reliability of the device.
The method for forming the semiconductor device provided by the embodiment of the invention comprises the following steps:
providing a semiconductor substrate, wherein a fin part and a pseudo gate structure crossing the fin part are formed on the semiconductor substrate, and the fin part has a first height;
etching the fin parts on two sides of the pseudo gate structure to enable the fin parts on two sides of the pseudo gate structure to have a second height lower than the first height;
forming a separation wall covering the side wall of the pseudo gate structure and part of the fin part;
etching the fin outside the isolation wall to enable the fin outside the isolation wall to have a third height lower than the second height;
epitaxially growing on the etched fin part to form a source region and a drain region;
and removing the pseudo gate structure and forming a gate structure at the original position of the pseudo gate structure.
Further, the semiconductor substrate further includes: shallow trench isolation structures covering the semiconductor substrate between the fins;
the method further comprises the steps of:
and before etching the fin parts on two sides of the pseudo gate structure, forming a protective layer on the shallow trench isolation structure, wherein the top surface of the protective layer is lower than the top surface of the fin part.
Further, etching depths of the fin portions on two sides of the pseudo gate structure are configured to enable top surfaces of the fin portions to be in the same horizontal plane with top surfaces of the protection layers.
Further, the third height is equal to the height of the shallow trench isolation structure.
Further, the protective layer is an organic dielectric layer or a bottom anti-reflection coating.
Further, the method further comprises: and re-oxidizing the pseudo gate structure and the fin part before forming the isolation wall.
Further, the isolation wall is made of silicon nitride.
According to another aspect of an embodiment of the present invention, there is provided a semiconductor device including:
a semiconductor substrate, wherein a fin part is formed on the semiconductor substrate, and the fin part is provided with a ladder-shaped structure;
a gate structure crossing the fin, the fin under the gate structure having a first height;
the isolation wall covers the side wall of the grid structure and part of the fin part, and the fin part below the isolation wall has a second height;
the fin parts below the source region and the drain region are provided with a third height;
wherein the first height, the second height and the third height decrease in sequence.
Further, the device further comprises: shallow trench isolation structures covering the semiconductor substrate between the fins.
Further, the height of the shallow trench isolation structure is equal to the third height.
Further, the isolation wall is made of silicon nitride.
The embodiment of the invention provides a semiconductor device and a forming method thereof. According to the embodiment of the invention, before the isolation wall covering the pseudo gate structure is formed, the fin parts on the two sides of the pseudo gate structure are etched to the second height, so that the formed isolation wall can extend to the side surface of the fin part below the pseudo gate structure besides covering the side wall of the pseudo gate structure, and therefore, the gate structure, the source region and the drain region can be better isolated. And simultaneously, after forming the isolation wall, etching the fin part at the outer side of the isolation wall to a third height so as to remove isolation wall materials remained on the upper surface of the fin part and the side wall of the fin part, thereby avoiding the residual isolation wall materials from blocking the epitaxial growth of the source region and the drain region in the subsequent epitaxial growth process and ensuring the reliability of the device.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:
fig. 1 is a flowchart of a method of forming a semiconductor device according to an embodiment of the present invention;
fig. 2 to 11 are schematic views of structures formed at respective steps of a method for forming a semiconductor device according to an embodiment of the present invention;
fig. 12 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention;
fig. 13 is a schematic cross-sectional view of another semiconductor device;
fig. 14 is a current profile on a fin of another semiconductor device.
Detailed Description
The present invention is described below based on examples, but the present invention is not limited to only these examples. In the following detailed description of the present invention, certain specific details are set forth in detail. The present invention will be fully understood by those skilled in the art without the details described herein. Well-known methods, procedures, flows, components and circuits have not been described in detail so as not to obscure the nature of the invention.
Moreover, those of ordinary skill in the art will appreciate that the drawings are provided herein for illustrative purposes and that the drawings are not necessarily drawn to scale.
Unless the context clearly requires otherwise, throughout the description and the claims, the words "comprise", "comprising", and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is, it is the meaning of "including but not limited to". In the description of the present invention, unless otherwise indicated, "multiple layers" means two or more layers.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. Spatially relative terms, such as "under …," "under," "lower," "above …," "upper," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "under" or "beneath" other elements or features would then be oriented "over" the other elements or features. Thus, the exemplary term "below" is intended to encompass both an orientation of above and below. The device may take other orientations (rotated 90 degrees or at other orientations), and the spatial relationship descriptors used herein interpreted accordingly.
The "sidewall" is a surface other than the top and bottom surfaces, and "covering the sidewall of the dummy gate structure" means covering the front, back, left side, and right side of the dummy gate structure.
Fig. 1 is a flowchart of a method for forming a semiconductor device according to an embodiment of the present invention, and referring to fig. 1, the method for forming the semiconductor device according to the embodiment of the present invention includes the steps of:
step S100, a semiconductor substrate is provided, wherein a fin portion and a pseudo gate structure crossing the fin portion are formed on the semiconductor substrate, and the fin portion has a first height.
Step S200, etching the fin portions on two sides of the dummy gate structure, so that the fin portions on two sides of the dummy gate structure have a second height lower than the first height.
And step S300, forming a separation wall covering the side wall of the pseudo gate structure and part of the fin part.
And S400, etching the fin parts outside the isolation wall so that the fin parts outside the isolation wall have a third height lower than the second height.
And S500, epitaxially growing on the etched fin part to form a source region and a drain region.
And S600, removing the pseudo gate structure and forming a gate structure at the original position of the pseudo gate structure.
In the following description, the following description further describes an embodiment of the present invention by using the method to form a semiconductor device during the gate last process. It should be understood that the method of the embodiment of the present invention is not limited to the back gate process, but may be applied to other process such as the front gate process.
Fig. 2 to 11 are schematic views of structures formed at respective steps of a method for forming a semiconductor device according to an embodiment of the present invention. Fig. 2 is a schematic three-dimensional structure of a semiconductor substrate, referring to fig. 2, in step S100, a semiconductor substrate 100 is provided, a fin 10 and a dummy gate structure 20 crossing the fin 10 are formed on the semiconductor substrate 100, wherein the fin 10 has a first height.
The semiconductor substrate 100 in step S100 may be a silicon single crystal substrate, a germanium single crystal substrate, or a silicon germanium single crystal substrate. Alternatively, the semiconductor substrate 100 may also be a silicon-on-insulator (SOI) substrate, a silicon-on-insulator (SSOI), a silicon-on-insulator (S-SiGeOI), a silicon-on-insulator (SiGeOI), a germanium-on-insulator (GeOI), a silicon-on-epitaxial layer structure substrate, or a compound semiconductor substrate. The compound semiconductor substrate includes silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, or indium dysprosium. Preferably, the semiconductor substrate 100 is a silicon single crystal substrate. A plurality of structures such as an epitaxial interfacial layer or a strained layer may be formed on the surface of the semiconductor substrate 100 to improve the electrical performance of the semiconductor device.
The fin 10 may be formed by patterning the semiconductor substrate 100, or a fin material layer may be formed on the semiconductor substrate 100 and then patterned to form the fin 10. Each fin 10 has a parallel or substantially parallel positional relationship therebetween. As an example, the semiconductor substrate 100 is patterned to form the fin 10.
The dummy gate structure 20 includes a polysilicon layer 21 and a gate oxide layer 22 stacked in this order. The purpose of dummy gate structure 20 is to define the size and location of the gate structure in subsequent processes.
Preferably, the semiconductor substrate 100 further includes: shallow trench isolation structures (Shallow Trench Isolation, STI) 11 covering the semiconductor substrate 100 between the fins 10, the material of the shallow trench isolation structures 11 may be silicon nitride (Si) 3 N 4 ) Silicon oxynitride (SiON), low-K dielectric material (dielectric constant greater than or equal to 2.5 and less than 3.9), or ultra-low K dielectric material (dielectric constant less than 2.5). Preferably, the material of the shallow trench isolation structure 11 is silicon oxide (SiO 2 )。
Fig. 3 is a schematic cross-sectional view of fig. 2 along line XX, as shown in fig. 3, in an alternative implementation, the shallow trench isolation structure 11 covers the semiconductor substrate 100 and the upper surface of the fin 10 and the sidewalls of the fin 10.
In an alternative implementation, the method for forming the shallow trench isolation structure 11 is as follows: forming an isolation material layer covering the semiconductor substrate 100 and the fin 10, the entire surface of the isolation material layer being higher than the top surface of the fin 10; and etching back the isolation material layer to form the shallow trench isolation structure 11.
The isolation material layer may be formed by chemical vapor deposition (Chemical Vapor Deposition, CVD) as is commonly used in the art, such as low temperature chemical vapor deposition (LowTemperature Chemical Vapor Deposition, LTCVD), plasma chemical vapor deposition (Plasma Chemical Vapor Deposition, PCVD), low pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition, LPCVD), rapid thermal chemical vapor deposition (Rapid Thermo Chemical Vapor Deposition, RTCVD), plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD), fluid chemical vapor deposition (Fluid Chemical Vapor Deposition, FCVD). Preferably, a fluid chemical vapor deposition process may be employed to provide a better filling effect of the regions between adjacent fins 10.
The shallow trench isolation structures 11 are used for electrical isolation between adjacent fins 10. The shallow trench isolation structure 11 may avoid implantation of dopant ions into the semiconductor substrate 100 during subsequent epitaxial growth.
Preferably, as shown in fig. 4, the forming method of the embodiment of the present invention further includes step S200a, forming a protection layer 12 on the shallow trench isolation structure 11. Wherein the top surface of the protection layer 12 may be equal to or lower than the top surface of the fin 10. Preferably, the top surface of the protection layer 12 is lower than the top surface of the fin 10, so as to improve the etching efficiency in the subsequent process of etching the fin, and simultaneously function as an etching stop layer, so as to better control the etching height.
The material of the protective layer 12 may be a fluid organic material, preferably an organic dielectric layer (Organic Dielectrical Layer, ODL) or a bottom anti-reflective coating (BARC), etc.
The fluid organic material is selected as the protective layer 12, because the fluid organic material has the characteristic of better filling property, has a good filling effect on gaps between the fin parts 10, and can play a good role in isolating and protecting parts except the fin parts to be etched in the process of etching the fin parts 10. The protection layer 12 protects the fin 10 and the shallow trench isolation structure 11 covered by the organic material from etching during a subsequent process of etching the fin 10. For the above purpose, in this step, the top surface of the protection layer 12 is lower than the top surface of the fin 10. The formation method of the protective layer 12 includes spin coating, drop coating, brush coating, and the like.
Referring to fig. 5, in step S200, the fin portions 10 on both sides of the dummy gate structure 20 are etched, that is, the fin portions not covered by the dummy gate structure 20 are etched, so that the fin portions 10 on both sides of the dummy gate structure 20 have a second height lower than the first height. Preferably, the top surface of the fin 10 and the top surface of the protection layer 12 are substantially at the same level after etching.
The etching process can be selected from the existing etching methods such as dry etching, wet etching and the like. Preferably, a dry etch is used to etch the fin 10, the dry etch may be selective to an etching gas, and may be selective to trifluoromethane (CHF 3 ) Sulfur hexafluoride (SF) 6 ) Carbon tetrafluoride (CF) 4 ) Carbon tetrafluoride (CF) 4 ) Oxygen (O) 2 ) And carbon tetrafluoride (CF) 4 ) Hydrogen (H) 2 ) Etc. as an etching gas. In embodiments of the present invention, CHF is preferably used 3 As an etching gas, the etching pressure may be 5 to 300mTorr, preferably 8 to 10mTorr.
The fin portions 10 uncovered by the dummy gate structures 20 are etched to the second height, and in the subsequent process of forming the isolation wall, the isolation wall can correspondingly extend to the upper surface of the fin portions of the second height, namely, due to the reduction of the height of the fin portions, the height of the corresponding isolation wall is increased, so that the isolation wall can achieve a better isolation effect.
Preferably, as shown in fig. 6, the forming method of the embodiment of the present invention further includes step S300a, removing the protection layer 12, and performing a reoxidation treatment on the dummy gate structure 20 and the fin 10.
The method for removing the protective layer 12 may be Ashing (Ashing Process), or may be a targeted solution removal method or etching method according to different protective layer materials. For example, when the protective layer material is ODL, the removal solution therefor may be an alkylammonium hydroxide-containing solution. Alternatively, dry etching may be used, for example, conventional plasma etching may be used. The etching gas may be nitrogen (N) 2 ) Oxygen (O) 2 ) Carbon tetrafluoride (CF) 4 ) Or sulfur dioxide (SO) 2 ) Etc. Preferably, nitrogen (N) containing no fluorine is used 2 ) Oxygen (O) 2 ) This may be such that the shallow trench isolation structures 11 underneath are not etched at all while the ODL is etched.
The dummy gate structure 20 and the fin portion 10 are subjected to reoxidation treatment to form a flat oxide layer 13, so that defects formed on the surfaces of the fin portion 10 and the dummy gate structure 20 in the etching process can be flattened, and meanwhile, the formation of silicon nitride (Si) 3 N 4 ) The stress of the isolation wall and the dummy gate structure 20, the defects of cracking, peeling and the like of the isolation wall are prevented, and the reliability of the device is ensured.
The reoxidation process may be performed using a furnace tube oxidation process. The furnace tube oxidation process comprises feeding silicon wafer into furnace tube, placing the silicon wafer in the environment of gas containing oxidant, allowing oxidant molecules to reach silicon surface via a Boundary Layer (BL), and reacting with silicon atoms to generate silicon oxide (SiO) 2 ). When the original pure silicon surface grows silicon oxide (SiO) 2 ) Thereafter, the formed silicon oxide (SiO 2 ) The layer prevents direct contact of the oxidizing agent with the silicon (Si) surface. The oxidizing agent is diffused through the silicon oxide (SiO 2 ) The layer reaching silicon oxide (SiO) 2 ) The silicon (Si) interface reacts with the silicon atoms to form new silicon oxide (SiO) 2 ) A layer of silicon oxide (SiO 2 ) The film is continually thickened.
In an alternative implementation, the oxidizing gas (oxidant) used in the reoxidation process is oxygen (O 2 ) And (2) andthe flow rate of the oxygen is 1.5 slm-2.5 slm. The oxidation temperature is 800-810 ℃. The oxidation time is 800 s-1000 s.
In other embodiments of the present invention, water vapor may be used as the oxidizing gas. However, the oxidation rate is faster when water vapor is used as the oxidizing gas, and thus, it is necessary to control the corresponding oxidation conditions more finely.
As shown in fig. 7, in step S300, a spacer 30 is formed to cover the sidewalls of the dummy gate structure 20 and a portion of the fin.
The isolation wall 30 can protect the side wall of the dummy gate structure 20 from being damaged in the process of the subsequent source-drain epitaxy production, and isolate the gate structure formed in the subsequent process from the source region and the drain region, so as to avoid short circuit.
The isolation wall 30 may be made of silicon nitride (Si 3 N 4 ) Silicon oxynitride (SiON) or silicon oxycarbide (SiOC), preferably silicon nitride (Si) 3 N 4 ). This is because silicon nitride (Si 3 N 4 ) Has a higher selectivity than polysilicon, while silicon nitride (Si 3 N 4 ) Is compact and has good effect of isolating ion diffusion.
The partition wall 30 may be formed by conventional chemical vapor deposition methods, such as low temperature chemical vapor deposition, low pressure chemical vapor deposition, rapid thermal chemical vapor deposition, plasma enhanced chemical vapor deposition, etc.
In other methods of forming, the isolation wall is formed on a sidewall of the dummy gate structure, wherein the isolation wall formed at a position above the fin extends from an upper surface of the dummy gate structure, along the sidewall of the dummy gate structure, to an upper surface of the fin at the first height. Unlike other forming methods, the embodiment of the invention etches the fin 10 in advance, so that the isolation wall 30 above the fin covers the fin below the dummy gate structure. Thus, the lower surface of the partial isolation wall 30 above the fin portion is lower than the lower surface of the dummy gate structure 20, and the isolation effect can be better achieved. Meanwhile, as the isolation wall extends downwards, the distribution of current on the fin part of the finally formed fin-type field effect transistor moves downwards in the on state, so that ion current is concentrated in the middle area of the fin part. The problems of hot carrier injection (Hot Carrier Injection, HCI) Effect, self-heating Effect (Self-heating Effect) and the like caused by concentration of ion current at the top end of the fin part in the on state of the fin field Effect transistor are solved, and the reliability of the device is improved.
Referring to fig. 8, in step S400, the fins 10 outside the isolation wall 30 are etched such that the fins 10 outside the isolation wall 30 have a third height lower than the second height. Preferably, the third height is equal to the height of the shallow trench isolation structure 11. At the same time as etching the fin 10, the oxide layer 13 of the fin is also etched accordingly.
Etching the fin portion 10 outside the isolation wall 30 can remove the isolation wall material remaining on the upper surface and the sidewalls of the fin portion 10. Preferably, the part of the fin portion 10 outside the isolation wall 30 and higher than the shallow trench isolation structure 11 is removed, so that the isolation wall material remained on the upper surface of the fin portion 10 and on the side wall is completely removed, the residual side wall material is prevented from blocking the epitaxial growth of the source region and the drain region in the subsequent epitaxial growth process, and the performance of the device is ensured.
The etching process may be performed by an etching method known to those skilled in the art, such as dry etching, wet etching, etc. Preferably, a dry etch is used to etch the fin 10, the dry etch may be selective to an etching gas, and may be selective to trifluoromethane (CHF 3 ) Sulfur hexafluoride (SF) 6 ) Carbon tetrafluoride (CF) 4 ) Carbon tetrafluoride (CF) 4 ) Oxygen (O) 2 ) And carbon tetrafluoride (CF) 4 ) Hydrogen (H) 2 ) Etc. as an etching gas. In embodiments of the present invention, trifluoromethane (CHF) is preferably used 3 ) As an etching gas, the etching pressure may be 5 to 300mTorr, preferably 8 to 10mTorr.
Referring to fig. 9, in step S500, epitaxial growth is performed on the etched fin 10 to form the source region 41 and the drain region 42. A semiconductor material, such as silicon (Si) or silicon germanium (SiGe), is epitaxially grown on the etched fin 10 to form raised active regions (including source and/or drain regions) on the upper surface of the fin 10 on both sides of the spacer 30. For an N-type semiconductor device, silicon (Si) may be epitaxially grown on the upper surface of the fin 10 outside the isolation wall 30 to form raised source and drain regions 41 and 42. For P-type semiconductor devices, silicon germanium (SiGe) may be epitaxially grown on the upper surface of fin 10 outside of spacer 30 to form raised source and drain regions 41, 42 to facilitate introducing stress to the device. Wherein in-situ doping, such as doping with phosphorus (P) or boron (B), etc., may be performed during epitaxial growth.
The epitaxial growth process may be selected from etching methods known to those skilled in the art, such as a Vapor Phase Epitaxy (VPE), a Liquid Phase Epitaxy (Liquid-Phase Epitaxy), a molecular Beam Epitaxy (Molecular Beam Epitaxy, MBE), and an Ion Beam Epitaxy (IBE).
The source region and the drain region are formed by adopting an epitaxial growth process, so that the widths of the source region and the drain region are larger than the width of the fin part, the series resistance can be reduced, and the driving current is improved; and meanwhile, the positions of the source region and the drain region can be raised to reduce parasitic junction capacitance, so that the performance of the transistor is improved.
Referring to fig. 10 and 11, in step S600, the dummy gate structure 20 is removed, and a gate structure 50 is formed at a position where the dummy gate structure 20 was originally located.
Specifically, step S600 includes:
and S1, forming an interlayer dielectric layer (Inter Layer Dielectrics, ILD) covering the shallow trench isolation structure, the source region, the drain region, the isolation wall and the pseudo gate structure.
And S2, removing the pseudo gate structure, and forming a groove at the position of the original pseudo gate structure.
Step S3, forming a gate structure 50 in the recess.
In step S1, an interlayer dielectric layer 60 is formed to cover the shallow trench isolation structure 11, the source region 41, the drain region 42, the isolation wall 30, and the dummy gate structure 20. The interlayer dielectric layer 60 may be made of silicon oxide (SiO 2 ) Silicon oxynitride (SiON) or silicon oxycarbide (SiOC), preferably silicon oxide (SiO) 2 )。
In an alternative implementation, the method of forming interlayer dielectric layer 60 includes: forming an interlayer dielectric material layer covering the dummy gate structure 20, the shallow trench isolation structure 11, the source region, the drain region and the isolation wall 30, wherein the whole surface of the interlayer dielectric material layer is higher than the top surface of the dummy gate structure 20; the interlayer dielectric material layer and the gate oxide layer 22 above the top surface of the dummy gate structure 20 are removed, exposing the top of the polysilicon layer 21, thereby forming an interlayer dielectric layer 60. The removal of the interlayer dielectric material layer and the gate oxide layer 22 above the top surface of the dummy gate structure 20 may be achieved by chemical mechanical polishing (Chemical Mechanical Polishing, CMP).
The interlayer dielectric layer 60 protects the source and drain regions from external ions during subsequent processing.
In step S2, the dummy gate structure 20 is removed, and a groove 70 is formed at the position of the original dummy gate structure 20. The isolation material of the surface of the fin 10 under the dummy gate structure 20 is removed at the same time as the dummy gate structure 20 is removed. The method for removing the dummy gate structure 20 may be wet etching, dry etching, or a combination of both wet etching and dry etching. As an example, a wet etching process is used to remove the dummy gate structure 20, and specific parameters include: the adopted etching solution is hydrofluoric acid solution, the mass percentage of hydrofluoric acid is 1:100-1:1000, and the etching temperature is 15-75 ℃.
In step S3, a gate structure 50 is formed in the recess 70 (i.e. the position where the dummy gate structure 20 is located), and preferably, the gate structure 50 includes a gate dielectric layer 51 and a gate electrode layer 52.
Specifically, the gate dielectric layer 51 is made of silicon oxide (SiO 2 ) Or a relative dielectric constant greater than that of silicon oxide (SiO 2 ) A high K dielectric material of relative dielectric constant. The high-K dielectric material includes: hafnium oxide (HfO) 2 ) Lanthanum oxide (La) 2 O 3 ) Zirconium oxide (ZrO) 2 ) Tantalum oxide (Ta) 2 O 5 ) Titanium oxide (TiO) 2 ) Barium strontium titanate (Ba) 1-x Sr x TiO 3 BST), barium titanium oxide (BaTiO) 3 ) Strontium titanium oxide (SrTiO) 3 ) Yttria (Y) 2 O 3 ) Alumina (Al) 2 O 3 ) Is to of (a)One less. The material of the gate dielectric layer 51 is preferably hafnium oxide (HfO 2 ). The gate dielectric layer 51 may be formed by chemical vapor deposition, such as low temperature chemical vapor deposition, low pressure chemical vapor deposition, rapid thermal chemical vapor deposition, plasma enhanced chemical vapor deposition, etc.
The gate dielectric layer 51 serves to isolate the gate structure from the silicon channel.
The gate electrode layer 52 comprises aluminum (Al), copper (Cu), silver (Ag), gold (Au), platinum (Pt), nickel (Ni), titanium (Ti), cobalt (Co), thallium (TI), tantalum (Ta), tungsten (W), tungsten silicide (WSi) 2 ) Titanium nitride (TiN) and thallium nitride (TI) 3 N), preferably tungsten (W).
The gate dielectric layer 51 and the gate electrode layer 52 may be formed by chemical vapor deposition methods commonly used in the art, such as low temperature chemical vapor deposition, plasma chemical vapor deposition, low pressure chemical vapor deposition, rapid thermal chemical vapor deposition, and plasma enhanced chemical vapor deposition.
In an alternative implementation, a gate dielectric layer 51 and a gate electrode layer 52 are deposited in sequence in recess 70. The gate electrode layer material fills the recess 70 to form the gate electrode layer 52 higher than the interlayer dielectric layer 60, and finally the gate electrode layer is polished by chemical mechanical polishing until the interlayer dielectric layer is exposed to form the gate structure 50.
In this embodiment, the formed High-K Metal Gate structure (HKMG) has low leakage current, so that the device has better performance. It should be appreciated that in alternative implementations, other materials may be used to form the gate structure, such as polysilicon.
It should be understood that, in the embodiments of the present invention, the fin portion may have other different shapes, such as a trapezoid with a top width smaller than a bottom width, a diamond, and so on, and the shape of the fin portion is adjusted according to the process conditions and the application scenario.
According to the embodiment of the invention, before the isolation wall covering the pseudo gate structure is formed, the fin parts on two sides of the pseudo gate structure are etched to the second height, so that the lower surface of the part, above the fin parts, of the formed isolation wall is lower than the lower surface of the pseudo gate structure, and the gate structure, the source region and the drain region can be better isolated. Meanwhile, the distribution of the current on the fin portion can be changed, so that the ion current is concentrated in the middle area of the fin portion. The problems of hot carrier injection effect, self-heating effect and the like caused by concentration of ion current on the top end of the fin part are solved, and the reliability of the device is improved. After forming the isolation wall, etching the fin part on the outer side of the isolation wall to a third height so as to remove isolation wall materials remained on the upper surface of the fin part and the side wall of the fin part, thereby avoiding the residual isolation wall materials from blocking the epitaxial growth of the source region and the drain region in the subsequent epitaxial growth process and ensuring the reliability of the device.
Still further preferably, the device further comprises an oxide layer covering the dummy gate structure sidewalls and a portion of the fin sidewalls.
As shown in fig. 12, an embodiment of the present invention further provides a semiconductor device, including: the semiconductor substrate 100, the fin 10, the gate structure 50, the isolation wall 30, the shallow trench isolation structure 11, the interlayer dielectric layer 60, the source region 41, and the drain region 42.
Specifically, the semiconductor substrate 100 may be a silicon single crystal substrate, a germanium single crystal substrate, or a silicon germanium single crystal substrate. Alternatively, the semiconductor substrate 100 may also be a silicon-on-insulator (SOI) substrate, a silicon-on-insulator (SSOI), a silicon-on-insulator (S-SiGeOI), a silicon-on-insulator (SiGeOI), a germanium-on-insulator (GeOI), a silicon-on-epitaxial layer structure substrate, or a compound semiconductor substrate. The compound semiconductor substrate includes silicon carbide (SiC), gallium arsenide, gallium phosphide, indium arsenide, or indium dysprosium. Preferably, the semiconductor substrate 100 is a silicon single crystal substrate. A plurality of structures such as an epitaxial interfacial layer or a strained layer may be formed on the surface of the semiconductor substrate 100 to improve the electrical performance of the semiconductor device.
The fin 10 is formed on the semiconductor substrate 100 and has a stepped structure. The fin portion 10 is made of monocrystalline silicon identical to the semiconductor substrate.
The gate structure 50 spans across the fin and the fin 10 below the gate structure 50 has a first height. The gate structure 50 includes a gate dielectric layer 51 and a gate electrode layer 52 stacked in sequence.
The gate dielectric layer 51 is made of silicon oxide (SiO 2 ) Or a relative dielectric constant greater than that of silicon oxide (SiO 2 ) A high K dielectric material of relative dielectric constant. The high-K dielectric material includes: hafnium oxide (HfO) 2 ) Lanthanum oxide (La) 2 O 3 ) Zirconium oxide (ZrO 2), tantalum oxide (Ta) 2 O 5 ) Titanium oxide (TiO) 2 ) Barium strontium titanate (Ba 1-xSrxTiO) 3 BST), barium titanium oxide (BaTiO) 3 ) Strontium titanium oxide (SrTiO) 3 ) Yttria (Y) 2 O 3 ) Alumina (Al) 2 O 3 ) At least one of them. The material of the gate dielectric layer 51 is preferably hafnium oxide (HfO 2 )。
The gate electrode layer 52 comprises aluminum (Al), copper (Cu), silver (Ag), gold (Au), platinum (Pt), nickel (Ni), titanium (Ti), cobalt (Co), thallium (TI), tantalum (Ta), tungsten (W), tungsten silicide (WSi) 2 ) Titanium nitride (TiN) and thallium nitride (TI) 3 N), preferably tungsten (W).
In the embodiment, the formed high-K metal gate has low leakage current, so that the device has better performance. It should be appreciated that in other alternative implementations, polysilicon gates may also be formed.
Preferably, the device further includes an oxide layer (not shown in the figure), which covers the dummy gate structure sidewalls and a portion of the fin sidewalls.
The isolation wall 30 covers the sidewall of the gate structure 50 and a portion of the fin 10, and the fin 10 under the isolation wall 30 has a second height smaller than the first height. The isolation wall 30 may be made of silicon nitride (Si 3 N 4 ) Silicon oxynitride (SiON) or silicon oxycarbide (SiOC), preferably silicon nitride (Si) 3 N 4 ). This is because silicon nitride (Si 3 N 4 ) Has a higher selectivity than polysilicon, while silicon nitride (Si 3 N 4 ) Is compact and has good effect of isolating ion diffusion.
Different from other forming methods, the fin portion 10 below the isolation wall 30 is lower than the fin portion 10 below the gate structure 50, so that the isolation wall 30 extends to the side wall of the fin portion 10 below the dummy gate structure 20, and the isolation effect can be better achieved. Meanwhile, as the isolation wall extends downwards, the distribution of current on the fin part of the finally formed fin-type field effect transistor moves downwards in the on state, so that ion current is concentrated in the middle area of the fin part. The problems of hot carrier injection effect, self-heating effect and the like caused by concentration of ion current at the top end of the fin part in the on state of the fin field effect transistor are solved, and the reliability of the device is improved.
The shallow trench isolation structures 11 cover the semiconductor substrate 100 between the fins for electrical isolation between adjacent fins. The material of the shallow trench isolation structure 11 may be silicon oxide (SiO 2 ) Silicon nitride (Si) 3 N 4 ) Silicon oxynitride (SiON), low-K dielectric material (dielectric constant greater than or equal to 2.5 and less than 3.9), or ultra-low-K dielectric material (dielectric constant less than 2.5), preferably, the material of the shallow trench isolation structure 11 is silicon oxide (SiO) 2 )。
The source region 41 and the drain region 42 are on the fin 10 outside the isolation wall 30, and the fin 10 below the source region 41 and the drain region 42 has a third height. Preferably, the third height of the fin 10 is equal to the height of the shallow trench isolation structure 11. Such a design ensures that the spacer material remaining on the surface of the fin 10 is removed during the formation of the spacer 30.
The interlayer dielectric layer 60 covers the sidewalls of the gate structure 50, the shallow trench isolation structure 11, the source region, the drain region, and the isolation wall 30. The material of interlayer dielectric layer 60 may be silicon oxide (SiO 2 ) Silicon oxynitride (SiON) or silicon oxycarbide (SiOC), preferably silicon oxide (SiO) 2 )。
The interlayer dielectric layer 60 can protect the source region and the drain region from external ions during a subsequent process.
Fig. 13 is a schematic cross-sectional view of another semiconductor device, and fig. 14 is a current distribution diagram on a fin of the other semiconductor device. In other semiconductor devices, the fin has no step shape, the isolation wall covers only the side wall of the dummy gate structure, and current on the fin is concentrated at the upper portion of the fin in the on state.
In this embodiment, the fin portion has a stepped structure, and the fin portion below the isolation wall is lower than the fin portion below the gate structure, so that the isolation effect can be better achieved. Meanwhile, as the isolation wall extends downwards, the distribution of the ion current on the fin part is changed, so that the ion current is concentrated in the middle area of the fin part. The problems of hot carrier injection effect, self-heating effect and the like caused by concentration of ion current at the top end of the fin part in the on state of the fin field effect transistor are solved, and the reliability of the device is improved. The fin parts below the source region and the drain region are lower than the fin parts below the isolation wall, so that the isolation wall material remained on the surface of the fin parts is removed in the formation process of the isolation wall, the source region and the drain region are not influenced by the residual isolation wall material, and the reliability of the device is ensured.
The embodiment of the invention provides a semiconductor device and a forming method thereof. According to the embodiment of the invention, before the isolation wall covering the pseudo gate structure is formed, the fin parts on the two sides of the pseudo gate structure are etched to the second height, so that the formed isolation wall can extend to the side surface of the fin part below the pseudo gate structure besides covering the side wall of the pseudo gate structure, and therefore, the gate structure, the source region and the drain region can be better isolated. And simultaneously, after forming the isolation wall, etching the fin part at the outer side of the isolation wall to a third height so as to remove isolation wall materials remained on the upper surface of the fin part and the side wall of the fin part, thereby avoiding the residual isolation wall materials from blocking the epitaxial growth of the source region and the drain region in the subsequent epitaxial growth process and ensuring the reliability of the device.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, and various modifications and variations may be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (7)
1. A method of forming a semiconductor device, comprising:
providing a semiconductor substrate, wherein a fin part and a pseudo gate structure crossing the fin part are formed on the semiconductor substrate, and the fin part has a first height;
etching the fin parts on two sides of the pseudo gate structure to enable the fin parts on two sides of the pseudo gate structure to have a second height lower than the first height;
forming a separation wall covering the side wall of the pseudo gate structure and part of the fin part, wherein the height difference between the first height and the second height is used for enabling the formed separation wall to concentrate ion current in the middle area of the fin part when the device is in a conducting state after the device is formed;
etching the fin parts outside the isolation wall to enable the fin parts outside the isolation wall to have a third height lower than the second height so as to remove isolation wall materials remained on the upper surface of the fin parts and the side walls of the fin parts;
epitaxially growing on the etched fin part to form a source region and a drain region;
and removing the pseudo gate structure and forming a gate structure at the original position of the pseudo gate structure.
2. The method of claim 1, wherein the semiconductor substrate further comprises: shallow trench isolation structures covering the semiconductor substrate between the fins;
the method further comprises the steps of:
and forming a protective layer on the shallow trench isolation structure before etching the fin parts on two sides of the pseudo gate structure.
3. The method of claim 2, wherein an etch depth of the fin on both sides of the dummy gate structure is configured such that a top surface of the fin is at a same level as a top surface of a protective layer.
4. The method of claim 2 wherein the third height is equal to a height of the shallow trench isolation structure.
5. The method of claim 2, wherein the protective layer is an organic dielectric layer or a bottom antireflective coating.
6. The method according to claim 1, wherein the method further comprises: and performing reoxidation treatment on the pseudo gate structure and the fin parts before forming the isolation wall.
7. The method of claim 1, wherein the isolation wall is made of silicon nitride.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811418850.8A CN111223780B (en) | 2018-11-26 | 2018-11-26 | Semiconductor device and forming method thereof |
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