CN111223735B - Etching method and etching equipment for semiconductor device hole structure - Google Patents
Etching method and etching equipment for semiconductor device hole structure Download PDFInfo
- Publication number
- CN111223735B CN111223735B CN201811415584.3A CN201811415584A CN111223735B CN 111223735 B CN111223735 B CN 111223735B CN 201811415584 A CN201811415584 A CN 201811415584A CN 111223735 B CN111223735 B CN 111223735B
- Authority
- CN
- China
- Prior art keywords
- semiconductor device
- etching
- plasma
- focusing ring
- dielectric layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000005530 etching Methods 0.000 title claims abstract description 151
- 239000004065 semiconductor Substances 0.000 title claims abstract description 147
- 238000000034 method Methods 0.000 title claims abstract description 45
- 230000002093 peripheral effect Effects 0.000 claims abstract description 44
- 230000008569 process Effects 0.000 claims abstract description 24
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 20
- 238000006243 chemical reaction Methods 0.000 claims description 11
- 230000007246 mechanism Effects 0.000 claims description 11
- 229910052681 coesite Inorganic materials 0.000 claims description 10
- 229910052906 cristobalite Inorganic materials 0.000 claims description 10
- 239000000377 silicon dioxide Substances 0.000 claims description 10
- 235000012239 silicon dioxide Nutrition 0.000 claims description 10
- 229910052682 stishovite Inorganic materials 0.000 claims description 10
- 229910052905 tridymite Inorganic materials 0.000 claims description 10
- CPELXLSAUQHCOX-UHFFFAOYSA-N Hydrogen bromide Chemical compound Br CPELXLSAUQHCOX-UHFFFAOYSA-N 0.000 claims description 8
- 230000004913 activation Effects 0.000 claims description 7
- 238000001312 dry etching Methods 0.000 claims description 6
- 101100107923 Vitis labrusca AMAT gene Proteins 0.000 claims description 4
- 230000004888 barrier function Effects 0.000 claims description 4
- 229910000042 hydrogen bromide Inorganic materials 0.000 claims description 4
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims description 3
- 239000000460 chlorine Substances 0.000 claims description 3
- 229910052801 chlorine Inorganic materials 0.000 claims description 3
- 230000005611 electricity Effects 0.000 claims description 3
- 230000003068 static effect Effects 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 52
- 230000002159 abnormal effect Effects 0.000 description 8
- 230000007797 corrosion Effects 0.000 description 8
- 238000005260 corrosion Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
- 230000004048 modification Effects 0.000 description 5
- 238000012986 modification Methods 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 230000001012 protector Effects 0.000 description 4
- 230000009467 reduction Effects 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 3
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 2
- 239000006227 byproduct Substances 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 238000012876 topography Methods 0.000 description 2
- 229910003691 SiBr Inorganic materials 0.000 description 1
- 229910003676 SiBr4 Inorganic materials 0.000 description 1
- 229910003910 SiCl4 Inorganic materials 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- AIFMYMZGQVTROK-UHFFFAOYSA-N silicon tetrabromide Chemical compound Br[Si](Br)(Br)Br AIFMYMZGQVTROK-UHFFFAOYSA-N 0.000 description 1
- FDNAPBUWERUEDA-UHFFFAOYSA-N silicon tetrachloride Chemical compound Cl[Si](Cl)(Cl)Cl FDNAPBUWERUEDA-UHFFFAOYSA-N 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32431—Constructional details of the reactor
- H01J37/32623—Mechanical discharge control means
- H01J37/32642—Focus rings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
- H01J37/32082—Radio frequency generated discharge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
- H01J2237/32—Processing objects by plasma generation
- H01J2237/33—Processing objects by plasma generation characterised by the type of processing
- H01J2237/334—Etching
Landscapes
- Chemical & Material Sciences (AREA)
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Plasma & Fusion (AREA)
- Analytical Chemistry (AREA)
- Inorganic Chemistry (AREA)
- General Chemical & Material Sciences (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The embodiment of the invention provides an etching method and etching equipment for a hole structure of a semiconductor device, and provides a semiconductor device which completes a front-layer process; generating a plasma; controlling the density of plasma by using a single radio frequency power supply system, reducing the bombardment force of the plasma when the single radio frequency power supply system is used for etching different media in the semiconductor device, reflecting the plasma by using a focusing ring, driving the plasma into the region of the semiconductor device, and etching a hole structure in the different media of the semiconductor device; when the distance between the inner peripheral edge of the focusing ring and the outer peripheral edge of the semiconductor device is less than or equal to 1mm, the height of the focusing ring is set to be 5.1-27.9 mm; and when the distance is larger than 1mm, the height of the focusing ring is set to be 1.1-6.2 mm.
Description
Technical Field
The invention relates to the technical field of etching equipment, in particular to an etching method of a hole structure of a semiconductor device and etching equipment.
Background
The hole structure is typically etched during the fabrication of the semiconductor device,
at present, there is an etching apparatus, such as AMAT MXP Poly etching apparatus, which is configured with a single (one) radio frequency power supply system (RF system for short) for controlling plasma density and bombardment strength thereof, and when etching different media of a semiconductor device, the etching apparatus can use the single radio frequency power supply system to reduce the bombardment strength of plasma to ensure a better etching selectivity when etching different media of the semiconductor device, but reducing the bombardment strength to ensure a higher etching selectivity tends to reduce the power of the single radio frequency power supply system, and the plasma density can be reduced therewith, which affects the etching uniformity of each region of the semiconductor device. At present, the etching equipment with a single radio frequency power supply system adopts a focusing ring (focus ring) to improve the etching uniformity.
However, although the focus ring can improve the etching uniformity, more plasma is reflected by the focus ring to bombard the sidewall of the hole structure, which reduces the protection effect of the sidewall protector, thereby reducing the reaction activation energy of the medium in the sidewall area, and accelerating the etching rate of the bombarded area of the sidewall, resulting in abnormal morphology of the finally etched hole structure. Particularly, when etching a medium which has low reaction activation energy and is easy to react, such as silicon, the rate of etching the medium is high, and when the sidewall protector is bombarded, the etching rate of the sidewall is accelerated, the morphology of the etched hole structure is abnormal, and even the sidewall area of the hole structure is etched through, so that the filler inside the hole structure is short-circuited with the adjacent hierarchical structure. Fig. 1 and fig. 2 are schematic diagrams of the longitudinal cross section of the hole structure of the semiconductor device etched by using the current etching apparatus equipped with a single radio frequency power supply system, and it can be seen from fig. 1 and fig. 2 that the shape of the side wall of the hole structure in the circle (the medium on the side wall in the circle is a Si layer, and a SiO2 layer with higher chemical reaction activation energy is on the Si layer) is abnormal.
For the etching equipment with the single radio frequency power supply system, theoretically, the etching equipment can be selectively modified into a double radio frequency power supply system, one radio frequency power supply system controls the plasma bombardment strength to ensure the etching selection ratio, and the other radio frequency power supply system controls the plasma density to ensure the etching uniformity.
Disclosure of Invention
Based on this, there is a need for an etching method and an etching apparatus for a hole structure of a semiconductor device.
A method for etching a hole structure of a semiconductor device, the method comprising:
providing a semiconductor device having completed a previous process;
generating a plasma;
controlling the density of plasma by using a single radio frequency power supply system, reducing the bombardment force of the plasma when the single radio frequency power supply system is used for etching different media in the semiconductor device, reflecting the plasma by using a focusing ring, driving the plasma into the region of the semiconductor device, and etching a hole structure in the different media of the semiconductor device;
when the distance between the inner peripheral edge of the focusing ring and the outer peripheral edge of the semiconductor device is smaller than or equal to 1mm, the height of the focusing ring is set to be 5.1-27.9 mm; and when the distance is larger than 1mm, the height of the focusing ring is set to be 1.1-6.2 mm.
According to the etching method of the hole structure of the semiconductor device, a double radio frequency power supply system is not needed, only the focusing ring with the height of 1.1-27.9 mm is used for reflecting plasma in the process of etching the hole structure, and compared with the focusing ring with the height of 1.1-27.9 mm, the plasma reflected by the focusing ring and hitting the side wall area of the hole structure of the semiconductor device can be reduced, so that the appearance of the hole structure of the semiconductor device can be improved, a single radio frequency power supply system does not need to be replaced by the double radio frequency power supply system, the hardware modification scale is small, the period is short, the cost is low, the feasibility is high, and the etching selection ratio and the etching uniformity of each area in the process of etching different media in the semiconductor device can be ensured. And when the distance between the inner peripheral edge of the focusing ring and the outer peripheral edge of the semiconductor device is less than 1mm, the height range of the focusing ring is higher than that when the distance is more than or equal to 1mm, so that the reduction degree of the reflected plasma in the semiconductor device area can be reduced, the corrosion difference of each area of the semiconductor device is reduced, the areas of the semiconductor device are corroded more uniformly, and the corrosion rate uniformity of the etching equipment in the process of etching the semiconductor device is ensured.
In one embodiment, the distance between the inner periphery of the focusing ring and the outer periphery of the semiconductor device is less than or equal to 1mm, and the height of the focusing ring is (19.1-0.25) mm to (19.1+0.25) mm.
In one embodiment, the step of etching the hole structure in the different medium of the semiconductor device is to etch the hole structure in the different medium of the semiconductor device by using plasma including chlorine and hydrogen bromide, by using dry etching, and by using an anisotropic etching mechanism.
In one embodiment, a first dielectric layer and a second dielectric layer are formed in the semiconductor device, the first dielectric layer is formed on the second dielectric layer, and the chemical reaction activation energy of the first dielectric layer is higher than that of the second dielectric layer;
the step of etching the hole structure in different media of the semiconductor device is to etch the first dielectric layer first, and then etch the second dielectric layer by taking the first dielectric layer as a barrier layer to obtain the hole structure of the semiconductor device.
In one embodiment, the semiconductor device is a DMOS device, the DMOS device includes a Si layer and a SiO2 layer, the first dielectric layer is the SiO2 layer, and the second dielectric layer is the Si layer.
It is also presented an etching apparatus comprising:
a plasma generator for generating plasma;
the focusing ring is used for reflecting the plasma and driving the plasma into the semiconductor device area; and
the single radio frequency power supply system is used for controlling the density of the plasma and reducing the bombardment strength of the plasma when the semiconductor device is etched so as to ensure the etching selection ratio when hole structures are etched in different media of the semiconductor device;
when the distance between the inner peripheral edge of the focusing ring and the outer peripheral edge of the semiconductor device is less than or equal to 1mm, the height of the focusing ring is 5.1 mm-27.9 mm; and when the distance between the inner peripheral edge of the focusing ring and the outer peripheral edge of the semiconductor device is more than 1mm, the height of the focusing ring is 1.1-6.2 mm.
The etching equipment does not need to be modified to have a double-radio-frequency power supply system, only needs the focusing ring with the height of 1.1-27.9 mm to reflect the plasma, can improve the appearance of the hole structure of the semiconductor device, and has the advantages of small modification scale, short period, low cost and high feasibility. The etching equipment only provided with the single radio frequency power supply system is used for etching the hole structure of the semiconductor device, so that the capacity of the semiconductor device can be enlarged, and the utilization rate of the stock etching equipment is also improved. And when the distance between the inner peripheral edge of the focusing ring and the outer peripheral edge of the semiconductor device is less than 1mm, the height range of the focusing ring is higher than that when the distance is more than or equal to 1mm, so that the reduction degree of the reflected plasma in the semiconductor device area can be reduced, the corrosion difference of each area of the semiconductor device is reduced, the more uniform each area of the semiconductor device is corroded, and the corrosion rate uniformity of the etching equipment in the process of etching the semiconductor device is ensured.
In one embodiment, the distance between the inner periphery of the focusing ring and the outer periphery of the semiconductor device is less than or equal to 1mm, and the height of the focusing ring is (19.1-0.25) mm to (19.1+0.25) mm.
In one embodiment, the single rf power supply system is a bias power rf power supply system, and the bias power rf power supply system is configured to reduce power to reduce a bias bombardment strength of the plasma, so as to ensure an etching selection ratio when etching different media in the semiconductor device.
In one embodiment, a cavity is arranged in the etching equipment, and the etching equipment further comprises an electrostatic chuck, a covering ring and a base; the focusing ring is located on the covering ring, the electrostatic chuck is used for adsorbing a semiconductor device by utilizing static electricity, the covering ring covers the base, and part of the covering ring is used for supporting the semiconductor device.
In one embodiment, the etching equipment is AMAT MXP Poly etching equipment.
Drawings
FIG. 1 is a topographical view of a longitudinal cross-section of a semiconductor device hole structure etched using current etching equipment;
FIG. 2 is a schematic diagram of a longitudinal cross-section of another semiconductor device hole structure etched by using a current etching apparatus;
FIG. 3 is a schematic flow chart illustrating a method for etching a via structure of a semiconductor device according to an embodiment of the present disclosure;
fig. 4 is a schematic diagram of a DMOS device with a preceding layer process completed in one embodiment;
fig. 5 is a schematic structural diagram of a DMOS device in which a hole structure is etched based on fig. 5;
FIG. 6 is a schematic cross-sectional right half view of an embodiment of an etching apparatus with a wafer mounted thereon;
FIG. 7 is a schematic diagram of a plasma after reducing the height of a focus ring in one embodiment;
FIG. 8 is a topographical view of a longitudinal cross-section of an aperture feature in an edge area of a semiconductor device etched using the methods of embodiments of the present application in an exemplary embodiment;
FIG. 9 is a schematic structural diagram of a chamber of an etching apparatus, such as a wafer, in one embodiment;
FIG. 10 is a schematic top view of a focus ring in accordance with an exemplary embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Fig. 3 is a schematic flow chart of an etching method for a semiconductor device hole structure according to an embodiment of the present application.
Referring to fig. 3, the method for etching a semiconductor device hole structure in the embodiment of the present application includes steps 302 to 304:
Specifically, the semiconductor device may be a wafer that includes a plurality of dies and completes a previous process. The wafer has a plurality of dies arranged therein, each die having a corresponding hole structure etched therein.
A first dielectric layer and a second dielectric layer are formed in the semiconductor device, the first dielectric layer is formed on the second dielectric layer, and the chemical reaction activation energy of the first dielectric layer is higher than that of the second dielectric layer; and the subsequent step of etching the hole structure in different media of the semiconductor device is to etch the first dielectric layer first and then etch the second dielectric layer by taking the first dielectric layer as a barrier layer to obtain the hole structure of the semiconductor device. Specifically, the semiconductor device is a DMOS device, the DMOS device includes a Si layer and a SiO2 layer, the first dielectric layer is the SiO2 layer, and the second dielectric layer is the Si layer.
Specifically, the semiconductor device provided may be a DMOS device with a previous process completed as shown in fig. 4, and fig. 5 is a DOMS device with a hole structure etched in fig. 4. Fig. 4 and 5 each include a substrate 410, an epitaxial layer 420, a well 430, an active region 440, a shallow trench isolation structure 450, a gate oxide layer 460, a field oxide layer 470, gate polysilicon 480, and an interlayer dielectric layer 490, the interlayer dielectric layer 490 being located on the gate polysilicon 480, the interlayer dielectric layer 490 being a SiO2 layer, and the gate polysilicon 480 being a Si layer. A hole structure is then etched in the interlevel dielectric layer 490 and gate polysilicon 480 in fig. 4. Specifically, a plasma containing chlorine and hydrogen bromide is used, dry etching is adopted, an anisotropic etching mechanism is used, a SiO2 layer is etched firstly, and then a Si layer is etched by taking a SiO2 layer as a barrier layer, so that a hole structure of the DMOS device is obtained. Wherein, the chemical reaction formula of the anisotropic etching reaction mechanism (including damage mechanism and protection mechanism) of the dry etching in the etching process is as follows:
si + Cl2+ HBr- - > SiCl4(g) + SiBr 4; during etching, Cl2 and HBr enter the cavity of the etching equipment in a gas state to generate plasma to etch the Si layer, and SiBr4 is the main component of the side wall protector.
At step 304, a plasma is generated.
Specifically, the plasma may be generated by a plasma generator.
And 306, controlling the density of the plasma by using a single radio frequency power supply system, reducing the bombardment strength of the plasma when the single radio frequency power supply system is used for etching different media in the semiconductor device, reflecting the plasma by using a focusing ring with the height of 1.1-27.9 mm, driving the plasma into the region of the semiconductor device, and etching a hole structure in the different media of the semiconductor device.
In this embodiment, a dry etching process is usually used to etch the semiconductor device, and the dry etching process is a commonly used etching process. The anisotropic etch reaction mechanism of the dry etch process includes a Damage (Damage) mechanism and a Block (Block) mechanism. The damage mechanism is a process of utilizing positive ions in plasma to impact an etched medium after acceleration and then reacting to form a byproduct, and the process has good directionality, but the etching selection ratio (the ratio of the etching rates of different etched media) of different etched media is very small. The protection mechanism is a process of generating byproducts by reacting radicals in plasma with an etched medium and generating polymers on the side wall of the etched medium by utilizing a specific reaction, and the polymers can serve as side wall protectors to protect the side wall of the hole structure from being damaged.
Generally, a semiconductor device needs to etch through a plurality of layers of different media to etch out a target hole structure. Different etching rates are generally configured for different media, that is, a certain etching selection ratio is ensured for different media, and the etching selection ratio cannot be too small. In the embodiment, the single radio frequency power supply system is adopted, namely only one radio frequency power supply system is configured to ensure that different media have better etching selection ratio. The etching selection ratio of different media can be controlled by the bombardment strength, because the bond energy and the chemical reaction activation energy of different media are different, the smaller the bombardment strength is, the more obvious the etching rate difference of different media is, and the better the etching selection ratio is; the larger the bombardment force is, the more easily any medium can react with the plasma, and the etching rates of different media tend to be consistent. However, reducing the bombardment force to ensure a higher etching selectivity necessarily reduces the power of the single radio frequency power supply system, and the plasma density is reduced accordingly, which affects the etching uniformity of each region of the semiconductor device. The focusing ring of the embodiment can reflect the plasma when etching the hole structure of the semiconductor device, so that the plasma can hit the semiconductor device region, thereby increasing the plasma density in the semiconductor region and improving the etching uniformity.
And the height of the focusing ring of the embodiment is in the range of 1.1 mm-27.9 mm, compared with the focusing ring higher than the height range, the focusing ring of the embodiment can reduce the plasma reflected by the focusing ring and hitting the side wall area of the hole structure of the semiconductor device, can improve the appearance of the hole structure of the semiconductor device, and can improve the etching uniformity to a certain extent.
Through the experiment of the inventor, the area of the abnormal hole structure in the semiconductor device etched by the focusing ring with the height range higher than 1.1 mm-27.9 mm is mostly found in the area of the edge of the semiconductor device, and the shape of the hole structure etched in the area of 4.5mm of the edge is easy to be abnormal. For example, as shown in FIG. 6, where the wafer 40 is surrounded by a focus ring 50, the first complete die on the edge of the wafer 40 (the region of the wafer 40 in dashed lines in FIG. 6, die size 2970um 2240um) is prone to anomalies when etching via structures. Referring to (a) and (b) of fig. 7, as shown in (b) of fig. 7, when the height of the focus ring is set to be in the range of 1.1mm to 27.9mm, part of the plasma is not reflected to the semiconductor device region but is emitted outside the focus ring. The focusing ring with the height of 1.1 mm-27.9 mm can especially reduce the plasma reflected by the inner wall of the focusing ring and hitting the side wall area of the hole structure in the edge area of the semiconductor device, and improve the appearance of the hole structure in the edge area, because the edge of the semiconductor device is generally reflected by more plasma, and the side wall of the hole structure at the edge is bombarded more seriously than the side wall of the hole structure near the center.
The better the etch rate uniformity for each region of the wafer, the less the etch variability for each region, the more uniform the etch. The inventors have found that the height of the focus ring affects the uniformity of the etching rate, and the lower the height of the focus ring is, although it is helpful to improve the topography of the edge region of the wafer, it will improve the uniformity of the etching rate, i.e. the etching rate of each region of the semiconductor wafer will be different, especially the etching rate of the edge region will be lower than that of the middle region, which will increase the etching difference of each region of the wafer. Table 1 is a comparison table of the morphology of the hole structure in the edge region of the wafer and the uniformity of the etching rate of the wafer after the inventors etch the wafer with focus rings of different heights.
TABLE 1
| Height of focusing ring (mm) | Pore structure topography in edge regions | Uniformity of etch rate |
| 38.1 | NG | 4.2％ |
| 33.2 | NG | 4.7％ |
| 27.9 | OK | 5.2％ |
| 23.3 | OK | 6.1％ |
| 19.1 | OK | 6.3％ |
| 14.3 | OK | 7.8％ |
| 8.4 | OK | 8.5％ |
| 5.1 | OK | 9.2％ |
| 0 | OK | 10.9％ |
As can be seen from table 1, when the height of the focus ring is too high, such as 33.2mm and 38.1mm in table 1, the hole structure at the edge of the wafer is abnormal because the edge area of the wafer is reflected by the focus ring with more plasma, and the sidewall of the hole structure at the edge of the wafer is bombarded by the reflected plasma from the focus ring with more plasma. The lower the height of the focus ring, the more uniform the etch rate, because more plasma is driven directly out of the focus ring, and the plasma density in various regions of the wafer decreases to a different degree, with the plasma density in the edge region of the wafer decreasing most.
If there is no or negligible space between the inner peripheral edge of the focus ring and the outer peripheral edge of the semiconductor device, the plasma density in the edge region of the wafer is reduced to a greater extent than if there is a space and the space is larger, so as to improve the morphology of the hole structure in the edge region of the semiconductor device and ensure the uniformity of the etching rate of less than 10%, the height of the focus ring when the space between the inner peripheral edge of the focus ring and the outer peripheral edge of the semiconductor device is smaller may be set higher than the height of the focus ring when the space between the inner peripheral edge of the focus ring and the outer peripheral edge of the semiconductor device is larger, so as to ensure the uniformity of the etching rate of the etching apparatus when etching the semiconductor device. For example, in the embodiment of the present application, when the distance between the inner peripheral edge of the focus ring and the outer peripheral edge of the semiconductor device is 1mm or less, the height of the focus ring is set to 5.1mm to 27.9mm, specifically (19.1 to 0.25) mm to (19.1+0.25) mm. When the distance between the inner peripheral edge of the focusing ring and the outer peripheral edge of the semiconductor device is larger than 1mm, the height of the focusing ring is set to be 1.1 mm-6.2 mm.
According to the etching method of the hole structure of the semiconductor device, a double radio frequency power supply system is not needed, only the focusing ring with the height of 1.1-27.9 mm is used for reflecting plasma in the process of etching the hole structure, and compared with the focusing ring with the height of 1.1-27.9 mm, the plasma reflected by the focusing ring and hitting the side wall area of the hole structure of the semiconductor device can be reduced, so that the appearance of the hole structure of the semiconductor device can be improved, a single radio frequency power supply system does not need to be replaced by the double radio frequency power supply system, the hardware modification scale is small, the period is short, the cost is low, the feasibility is high, and the etching selection ratio and the etching uniformity of each area in the process of etching different media in the semiconductor device can be ensured. And when the distance between the inner peripheral edge of the focusing ring and the outer peripheral edge of the semiconductor device is less than 1mm, the height range of the focusing ring is higher than that when the distance is more than or equal to 1mm, so that the reduction degree of the reflected plasma in the semiconductor device area can be reduced, the corrosion difference of each area of the semiconductor device is reduced, the areas of the semiconductor device are corroded more uniformly, and the corrosion rate uniformity of the etching equipment in the process of etching the semiconductor device is ensured.
The etching method in the embodiment of the application can improve the morphology of the hole structure of the semiconductor device, and particularly can improve the abnormal morphology of the hole structure in the edge area of the semiconductor device. As shown in fig. 8, which is a profile of a longitudinal section of a hole structure in an edge area of a semiconductor device etched by the etching method in the embodiment of the present application in an embodiment, the hole structure profile in fig. 8 is obviously improved compared with the abnormal profile in fig. 1 and fig. 2. The etching method of the semiconductor device hole structure can ensure the etching selection ratio and the etching uniformity of each area of the semiconductor device when different media in the semiconductor device are etched, can also enlarge the productivity of the semiconductor device and increase the utilization rate of the stored etching equipment with the single radio frequency power supply system.
The embodiment of the application also provides etching equipment. Referring to fig. 6 and 9, the etching apparatus includes: a plasma generator (not shown) for generating plasma; the focusing ring 50 with the height of 1.1 mm-27.9 mm is used for reflecting the plasma and driving the plasma into the semiconductor device area; and a single radio frequency power supply system (not shown) for controlling the plasma density and for reducing the bombardment force of the plasma when etching the semiconductor device, so as to ensure the etching selection ratio when etching the hole structure in different media of the semiconductor device; wherein the focus ring 50 surrounds an outer peripheral edge of the semiconductor device, as shown in fig. 9. The height of the focus ring when the distance between the inner peripheral edge of the focus ring 50 and the outer peripheral edge of the semiconductor device is small may be set higher than the height of the focus ring when the distance between the inner peripheral edge of the focus ring 50 and the outer peripheral edge of the semiconductor device is large, for example, when the distance between the inner peripheral edge of the focus ring 50 and the outer peripheral edge of the semiconductor device is less than or equal to 1mm, the height of the focus ring 50 may be 5.1mm to 27.9mm, specifically (19.1-0.25) mm to (19.1+0.25) mm; when the distance between the inner peripheral edge of the focusing ring 50 and the outer peripheral edge of the semiconductor device is larger than 1mm, the height of the focusing ring 50 is 1.1 mm-6.2 mm.
Specifically, referring to fig. 9, fig. 9 is a schematic structural diagram of a chamber 10 of an etching apparatus, which takes a wafer as an example, in an embodiment. The etching equipment is internally provided with a cavity 10, and also comprises a fixing device for fixing a wafer and a cover ring (cover ring)20 for protecting the bottom structure of the etching equipment, wherein the fixing device can be an electrostatic chuck 30 which adsorbs the wafer 40 by utilizing static electricity; the focus ring 50, cover ring 20, and electrostatic chuck 30 are disposed within the chamber 10. A focus ring 50 surrounds the outer peripheral edge of the wafer 40. The plasma generator generates plasma to strike the wafer 40 in the chamber 10, and the hole structure of the wafer 40 is etched by the plasma. Specifically, referring to fig. 6, fig. 6 is a schematic cross-sectional view of the etching apparatus with a wafer mounted on the right half, in fig. 6, the etching apparatus further includes a base 60, a cover ring 20 covers the base 60, and a portion of the cover ring 20 is used for supporting the wafer 40, i.e., the wafer 40 is fixed by the electrostatic chuck 30 and extends partially onto the cover ring 20. Wafer 40 in fig. 6 is a wafer with a photolithographic process to remove the approximately 1.5mm edge of the non-conductive pattern.
The etching apparatus may be an AMAT MXP Poly etching apparatus. The single radio frequency power supply system can be a Bias power radio frequency power supply system (Bias RF system for short) with the frequency of 13.56MHz, and the Bias power radio frequency power supply system is used for reducing power to reduce the Bias bombardment strength of plasma so as to ensure the etching selection ratio when different media in a semiconductor device are etched.
Specifically, the shape of the focus ring is adapted to the shape of the semiconductor device. For example, the semiconductor device that is the wafer is circular, and the shape of the focus ring that surrounds the wafer is also circular. As shown in fig. 10, fig. 10 is a schematic top view of a focus ring in an embodiment, and in fig. 10, the focus ring 50 is also circular in shape, and the wafer 40 surrounded by the focus ring 50 is also circular.
The etching equipment does not need to be modified to have a double-radio-frequency power supply system, only needs the focusing ring 50 with the height of 1.1-27.9 mm to reflect plasma, can improve the appearance of the hole structure of the semiconductor device, and has the advantages of small modification scale, short period, low cost and high feasibility. The etching equipment only provided with the single radio frequency power supply system is used for etching the hole structure of the semiconductor device, so that the capacity of the semiconductor device can be enlarged, and the utilization rate of the stock etching equipment is also improved. And when the distance between the inner peripheral edge of the focusing ring 50 and the outer peripheral edge of the semiconductor device is less than 1mm, the height range of the focusing ring 50 is higher than that when the distance is more than or equal to 1mm, so that the degree of reduction of the reflected plasma in the semiconductor device area can be reduced, the corrosion difference of each area of the semiconductor device is reduced, the more uniform each area of the semiconductor device is corroded, and the uniformity of the corrosion rate of the etching equipment in the process of etching the semiconductor device is ensured.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A method for etching a hole structure of a semiconductor device is characterized by comprising the following steps:
providing a semiconductor device having completed a previous process;
generating a plasma;
controlling the density of plasma by using a single radio frequency power supply system, reducing the bombardment force of the plasma when the single radio frequency power supply system is used for etching different media in the semiconductor device, reflecting the plasma by using a focusing ring, driving the plasma into the region of the semiconductor device, and etching a hole structure in the different media of the semiconductor device;
when the distance between the inner peripheral edge of the focusing ring and the outer peripheral edge of the semiconductor device is less than or equal to 1mm, the height of the focusing ring is set to be 5.1-27.9 mm; and when the distance is larger than 1mm, the height of the focusing ring is set to be 1.1-6.2 mm.
2. The method of claim 1,
the distance between the inner peripheral edge of the focusing ring and the outer peripheral edge of the semiconductor device is less than or equal to 1mm, and the height of the focusing ring is (19.1-0.25) mm to (19.1+0.25) mm.
3. The method according to claim 1 or 2,
the step of etching the hole structures in the different media of the semiconductor device is to etch the hole structures in the different media of the semiconductor device by using plasma comprising chlorine and hydrogen bromide, adopting dry etching and using an anisotropic etching mechanism.
4. The method according to claim 1 or 2,
a first dielectric layer and a second dielectric layer are formed in the semiconductor device, the first dielectric layer is formed on the second dielectric layer, and the chemical reaction activation energy of the first dielectric layer is higher than that of the second dielectric layer;
the step of etching the hole structure in different media of the semiconductor device is to etch the first dielectric layer first, and then etch the second dielectric layer by taking the first dielectric layer as a barrier layer to obtain the hole structure of the semiconductor device.
5. The method of claim 4, wherein the semiconductor device is a DMOS device comprising a Si layer and a SiO2 layer, wherein the first dielectric layer is the SiO2 layer, and wherein the second dielectric layer is the Si layer.
6. An etching apparatus, comprising:
a plasma generator for generating plasma;
the focusing ring is used for reflecting the plasma and driving the plasma into the semiconductor device area; and
the single radio frequency power supply system is used for controlling the density of the plasma and reducing the bombardment strength of the plasma when the semiconductor device is etched so as to ensure the etching selection ratio when hole structures are etched in different media of the semiconductor device;
when the distance between the inner peripheral edge of the focusing ring and the outer peripheral edge of the semiconductor device is less than or equal to 1mm, the height of the focusing ring is 5.1 mm-27.9 mm; when the distance is larger than 1mm, the height of the focusing ring is 1.1 mm-6.2 mm.
7. Etching apparatus according to claim 6,
the distance between the inner peripheral edge of the focusing ring and the outer peripheral edge of the semiconductor device is less than or equal to 1mm, and the height of the focusing ring is (19.1-0.25) mm to (19.1+0.25) mm.
8. Etching apparatus according to claim 6,
the single radio frequency power supply system is a bias power radio frequency power supply system, and the bias power radio frequency power supply system is used for reducing power so as to reduce the bias bombardment strength of plasma, so that the etching selection ratio when different media in a semiconductor device are etched is ensured.
9. The etching apparatus according to claim 6, wherein a cavity is formed in the etching apparatus, and the etching apparatus further comprises an electrostatic chuck, a cover ring and a base;
the focusing ring is located on the covering ring, the electrostatic chuck is used for adsorbing a semiconductor device by utilizing static electricity, the covering ring covers the base, and part of the covering ring is used for supporting the semiconductor device.
10. Etching apparatus according to any of claims 6 to 9, wherein the etching apparatus is an AMAT MXP Poly etching apparatus.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811415584.3A CN111223735B (en) | 2018-11-26 | 2018-11-26 | Etching method and etching equipment for semiconductor device hole structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811415584.3A CN111223735B (en) | 2018-11-26 | 2018-11-26 | Etching method and etching equipment for semiconductor device hole structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111223735A CN111223735A (en) | 2020-06-02 |
| CN111223735B true CN111223735B (en) | 2022-08-12 |
Family
ID=70827769
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811415584.3A Active CN111223735B (en) | 2018-11-26 | 2018-11-26 | Etching method and etching equipment for semiconductor device hole structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111223735B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101587820A (en) * | 2008-05-20 | 2009-11-25 | 中芯国际集成电路制造(上海)有限公司 | Plasma etching method and device for improving depth difference of grooves |
| CN101651078A (en) * | 2008-08-13 | 2010-02-17 | 东京毅力科创株式会社 | Focus ring, plasma processing apparatus and plasma processing method |
| CN102522305A (en) * | 2011-12-27 | 2012-06-27 | 中微半导体设备(上海)有限公司 | Plasma processing apparatus and focus ring assembly |
| CN104008946A (en) * | 2014-06-12 | 2014-08-27 | 上海华力微电子有限公司 | Focusing ring for aluminum etching process and aluminum etching process |
-
2018
- 2018-11-26 CN CN201811415584.3A patent/CN111223735B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101587820A (en) * | 2008-05-20 | 2009-11-25 | 中芯国际集成电路制造(上海)有限公司 | Plasma etching method and device for improving depth difference of grooves |
| CN101651078A (en) * | 2008-08-13 | 2010-02-17 | 东京毅力科创株式会社 | Focus ring, plasma processing apparatus and plasma processing method |
| CN102522305A (en) * | 2011-12-27 | 2012-06-27 | 中微半导体设备(上海)有限公司 | Plasma processing apparatus and focus ring assembly |
| CN104008946A (en) * | 2014-06-12 | 2014-08-27 | 上海华力微电子有限公司 | Focusing ring for aluminum etching process and aluminum etching process |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111223735A (en) | 2020-06-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR102034556B1 (en) | Plasma processing method | |
| KR100553483B1 (en) | Rf plasma reactor with hybrid conductor and multi-radius dome ceiling | |
| JP5912637B2 (en) | Manufacturing method of semiconductor device | |
| US9449838B2 (en) | Semiconductor device manufacturing method | |
| US7582532B2 (en) | Method for fabricating semiconductor device | |
| US6756313B2 (en) | Method of etching silicon nitride spacers with high selectivity relative to oxide in a high density plasma chamber | |
| US20040238488A1 (en) | Wafer edge etching apparatus and method | |
| US20160079040A1 (en) | Plasma Processing Devices Having a Surface Protection Layer | |
| KR102307417B1 (en) | Etching method | |
| JP2006032965A (en) | Semiconductor etching apparatus | |
| TW201705428A (en) | Apparatus and methods for spacer deposition and selective removal in an advanced patterning process | |
| KR20000012948A (en) | Dielectric window of etching apparatus for fabricating semiconductor device | |
| JP2010080846A (en) | Dry etching method | |
| TWI687995B (en) | Method of silicon extraction using a hydrogen plasma | |
| CN111223735B (en) | Etching method and etching equipment for semiconductor device hole structure | |
| CN110911344B (en) | Manufacturing method of semiconductor substrate shallow trench and semiconductor substrate shallow trench structure | |
| US20180190475A1 (en) | Focus ring and plasma-processing apparatus including the same | |
| US9653316B2 (en) | Plasma processing method and plasma processing apparatus | |
| JP4982962B2 (en) | Manufacturing method of semiconductor device | |
| US20080003791A1 (en) | Method for fabricating recess gate in semiconductor device | |
| US20240006182A1 (en) | Method for etching silicon wafer | |
| JP2017168645A (en) | Manufacturing method for semiconductor device | |
| US9530671B2 (en) | Etching method | |
| JP5264383B2 (en) | Dry etching method | |
| KR102170584B1 (en) | Plasma processing method and plasma processing apparatus |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |