CN111223408B - Display panel, edge damage detection method, preparation method and display device - Google Patents
Display panel, edge damage detection method, preparation method and display device Download PDFInfo
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Abstract
The embodiment of the application provides a display panel, an edge damage detection method, a preparation method and a display device, and relates to the technical field of display panels. The display panel includes: a display region, an opening in the display region, a switching device around the opening, a gate signal line surrounding the opening, and a light emitting signal line; the first end of the switching device is electrically connected with the light-emitting signal wire; the second end of the switching device is electrically connected with the signal input end of the grid signal line; the control end of the switching device is electrically connected with the signal output end of the grid signal wire. The edge breakage detection method comprises the following steps: if the edge of the opening is not damaged, the switch device is closed, and the grid signal line does not output the first level signal; if the edge of the opening is damaged, the switch device is conducted, and the grid signal line outputs a first level signal to the light-emitting signal line. The embodiment of the application can effectively judge whether the edge of the opening of the AA Hole is damaged.
Description
Technical Field
The application relates to the technical field of display panels, in particular to a display panel, an edge damage detection method, a preparation method and a display device.
Background
With the rapid development of an AA Hole (indicating that an AA Area is punched, the AA Area refers to an active Area, and the effective display Area 12 is an Area for displaying a graphic) full-screen mobile phone, a high screen occupation ratio has become an important development direction of various current mobile phone manufacturers. Punching holes in the AA area can improve the screen occupation ratio, but an effective detection method for the edge breakage Crack of the AA Hole is not available temporarily.
Therefore, it is necessary to design a detection scheme for detecting edge damage Crack of the opening of the display panel with the AA Hole, so as to effectively detect whether the edge of the opening of the AA Hole is damaged or not.
Disclosure of Invention
The application provides a display panel, an edge damage detection method, a preparation method and a display device aiming at the defects of the existing mode, and aims to solve the technical problem that whether the edge of an opening of an AA Hole is damaged or not can not be effectively detected in the prior art.
In a first aspect, an embodiment of the present application provides a display panel, including: a display region, an opening in the display region, a switching device around the opening, a gate signal line surrounding the opening, and a light emitting signal line; the first end of the switching device is electrically connected with the light-emitting signal wire; the second end of the switching device is electrically connected with the signal input end of the grid signal line; the control end of the switching device is electrically connected with the signal output end of the grid signal wire.
In one possible embodiment, the switching device is a thin film transistor; the control end of the thin film transistor is a grid electrode of the thin film transistor; if the first end of the thin film transistor is the drain electrode of the thin film transistor, the second end of the thin film transistor is the source electrode of the thin film transistor;
if the first end of the thin film transistor is the source electrode of the thin film transistor, the second end of the thin film transistor is the drain electrode of the thin film transistor.
In one possible embodiment, the display panel further includes: the semiconductor device includes a substrate, an active layer and a gate electrode layer stacked on the substrate, and a gate insulating layer filled between the active layer and the gate electrode layer;
the gate layer comprises a first gate region, a second gate region and a third gate region, and the second gate region is connected with the third gate region;
the first gate region is used as a light emitting signal line, and the third gate region is used as a gate signal line;
the first gate region and the active layer are electrically connected through a first signal line;
the third gate region and the active layer are electrically connected through a second signal line.
In one possible embodiment, the display panel further includes an interlayer dielectric layer stacked on the gate insulating layer;
two sides of the first signal line sequentially penetrate through the interlayer dielectric layer and the gate insulating layer and are respectively and electrically connected with the first gate region and the active layer;
two sides of the second signal line sequentially penetrate through the interlayer dielectric layer and the gate insulating layer and are respectively and electrically connected with the active layer and the third gate region;
the middle section of the first signal line and the middle section of the second signal line are both located on the interlayer dielectric layer.
In one possible embodiment, the substrate is at least one of a polyimide film layer, a barrier film layer, and a buffer film layer.
In a second aspect, an embodiment of the present application further provides a method for detecting edge damage of an opening of a display panel, which is applied to the display panel of the first aspect, and includes the following steps:
if the edge of the opening is not damaged, the switch device is closed, and the grid signal line does not output the first level signal;
if the edge of the opening is damaged, the switch device is conducted, and the grid signal line outputs a first level signal to the light-emitting signal line.
In a third aspect, an embodiment of the present application further provides a method for manufacturing a display panel, which is applied to the display panel of the first aspect, and includes the following steps:
providing an active layer on a substrate;
arranging a first gate insulating layer on one side of the active layer, which is far away from the substrate;
arranging a gate layer on one side, far away from the substrate, of the first gate insulating layer, wherein the gate layer comprises a first gate region, a second gate region and a third gate region, and the second gate region is connected with the third gate region;
preparing an insulating layer on one side of the grid layer away from the substrate;
respectively forming via holes at the positions of the insulating layer corresponding to the first gate region, the third gate region and the active layer;
and preparing a signal wire at one side of each through hole and the insulating layer far away from the substrate, so that the first gate region and the active layer are electrically connected through a first signal wire in the signal wire, and the third gate region and the active layer are electrically connected through a second signal wire in the signal wire.
In one possible embodiment, on the side of the gate layer away from the substrate, an insulating layer is prepared, including:
preparing a second gate insulating layer on one side of the gate layer away from the substrate;
and preparing an interlayer dielectric layer on the side of the second gate insulating layer far away from the substrate.
In one possible embodiment, the forming of the via holes at the positions of the insulating layer corresponding to the first gate region, the third gate region and the active layer respectively includes:
respectively forming via holes at the positions of the interlayer dielectric layer and the second gate insulating layer, which correspond to the first gate region and the third gate region;
through holes are respectively formed in the interlayer dielectric layer, the second grid electrode insulating layer and the first grid electrode insulating layer at positions corresponding to the active layers; and the number of the first and second groups,
preparing a signal wire on one side of each via hole and the insulating layer far away from the substrate, so that the first gate region and the active layer are electrically connected through a first signal wire in the signal wire, and the third gate region and the active layer are electrically connected through a second signal wire in the signal wire, wherein the signal wire comprises:
and filling metal materials in the through holes, and correspondingly connecting the metal materials in the two corresponding through holes through the metal materials on one side of the insulating layer, which is far away from the substrate, so as to form a first signal line and a second signal line.
In a fourth aspect, an embodiment of the present application further provides a display device, including: the display panel of the first aspect.
The technical scheme provided by the embodiment of the application has the following beneficial technical effects:
the display panel of the embodiment of the application is provided with the switch device at the periphery of the opening of the AA Hole, the first end of the switch device is electrically connected with the light-emitting signal wire, the second end of the switch device is electrically connected with the signal input end of the grid signal wire, the grid signal wire is arranged around the opening, and the control end of the switch device is electrically connected with the signal output end of the grid signal wire. According to the display panel provided by the embodiment of the application, if the edge of the opening is not damaged, the switch device is closed, and the grid signal line does not output the first level signal; if the edge of the opening is damaged, the switch device is switched on, the grid signal line outputs a first level signal to the light-emitting signal line, so that interference is generated on the light-emitting signal line, a horizontal bright line or a short horizontal bright line appears on a black picture of the display panel, whether the edge of the opening of the AA Hole is damaged or not can be effectively judged, and the technical problem that whether the edge of the opening of the AA Hole is damaged or not can not be effectively detected in the prior art is solved.
Additional aspects and advantages of the present application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the present application.
Drawings
The foregoing and/or additional aspects and advantages of the present application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
FIG. 1 is a schematic view of a display panel according to an embodiment of the present disclosure;
FIG. 2 is a diagram illustrating the structural relationship of the opening, the switching device, the gate signal line, and the light emitting signal line according to the embodiment of the present application;
FIG. 3 is a timing diagram of a light emitting signal line according to an embodiment of the present application;
FIG. 4 is a flowchart illustrating a method for fabricating a display panel according to an embodiment of the present disclosure;
fig. 5 to 7 are schematic structural diagrams in a process of manufacturing a display panel according to an embodiment of the present application;
fig. 8 is a schematic structural diagram of a display panel obtained by a method for manufacturing a display panel according to an embodiment of the present application.
Reference numerals:
1-opening, 2-switching device, 3-grid signal line, 4-luminous signal line, 5-substrate, 6-active layer;
7-gate layer, 7 a-first gate region, 7 b-second gate region, 7 c-third gate region;
8-a first gate insulating layer, 9-a second gate insulating layer, 10-an interlayer dielectric layer;
11 a-a first signal line, 11 b-a second signal line;
12-display area.
Detailed Description
Reference will now be made in detail to the present application, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar parts or parts having the same or similar functions throughout. In addition, if a detailed description of the known art is not necessary for illustrating the features of the present application, it is omitted. The embodiments described below with reference to the drawings are exemplary only for the purpose of explaining the present application and are not to be construed as limiting the present application.
It will be understood by those within the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
As used herein, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present. Further, "connected" or "coupled" as used herein may include wirelessly connected or wirelessly coupled. As used herein, the term "and/or" includes all or any element and all combinations of one or more of the associated listed items.
The inventors of the present application have studied and found that when an EOA output test line is present on an integrated circuit/COF (Chip on FPC) side of a display panel and a short circuit occurs between the EOA output test line and another frame of the COF, a potential of a light emitting signal is pulled high in a black screen, thereby causing a short cross luminance line. Based on the above principle, the inventor of the present application considers that if the first level signal is output to the light-emitting signal line when the edge of the opening is not damaged, and the light-emitting signal of the light-emitting signal line is interfered, so that a bright horizontal line or a short bright horizontal line appears on the black frame of the display panel, it can be determined that the edge of the opening is damaged.
The following describes the technical solutions of the present application and how to solve the above technical problems with specific embodiments.
Referring to fig. 1 and 2, an embodiment of the present application provides a display panel including: a display region 12, an opening 1 located in the display region 12, a switching device 2 located at the periphery of the opening 1, a gate signal line 3 disposed around the opening 1, and a light emitting signal line 4; a first terminal of the switching device 2 is electrically connected to the light emitting signal line 4; a second end of the switching device 2 is electrically connected with a signal input end of the gate signal line 3; a control terminal of the switching device 2 is electrically connected to a signal output terminal of the gate signal line 3.
Referring to fig. 1, a display area 12 in the drawing indicates an AA area in the drawing, an opening 1 indicates an AA Hole, one end of an ET (emulation Test) wire is used for connecting with a binding area, and the other end is used for connecting with a lighting device outside a screen and is used for a screen lighting Test; the bonding region is used for bonding a driver IC chip (Integrated Circuit).
In the display panel of the embodiment of the application, the switch device 2 is arranged at the periphery of the opening 1, and if the edge of the opening 1 is not damaged, the switch device 2 is closed, and the gate signal line 3 does not output the first level signal; if the edge of the opening 1 is damaged, the switching device 2 is turned on, and the gate signal line outputs the first level signal to the light-emitting signal line 4, so that interference is generated on the light-emitting signal line 4, a horizontal bright line or a short horizontal bright line appears on a black picture in the display area 12 of the display panel, and the edge damage of the opening 1 can be effectively judged.
Alternatively, the switching device 2 is a Thin-film transistor (TFT); the control end of the thin film transistor is a grid electrode of the thin film transistor; if the first end of the thin film transistor is the drain electrode of the thin film transistor, the second end of the thin film transistor is the source electrode of the thin film transistor; if the first end of the thin film transistor is the source electrode of the thin film transistor, the second end of the thin film transistor is the drain electrode of the thin film transistor.
Optionally, referring to fig. 8, the display panel further includes: a substrate 5, an active layer 6 and a gate electrode layer 7 stacked on the substrate 5, and a gate insulating layer filled between the active layer 6 and the gate electrode layer 7; the gate layer 7 comprises a first gate region 7a, a second gate region 7b and a third gate region 7c, the second gate region 7b and the third gate region 7c being connected. The first gate region 7a serves as the light emitting signal line 4, and the third gate region 7c serves as the gate signal line 3; the first gate region 7a and the active layer 6 are electrically connected through a first signal line 11 a; the third gate region 7c and the active layer 6 are electrically connected through a second signal line 11 b. Specifically, in the present embodiment, the gate insulating layer includes the first gate insulating layer 8 and the second gate insulating layer 9.
Alternatively, as shown in fig. 8, the display panel further includes an interlayer dielectric layer 10 stacked on the gate insulating layer. Both sides of the first signal line 11a sequentially pass through the interlayer dielectric layer 10 and the gate insulating layer and are electrically connected to the first gate region 7a and the active layer 6, respectively. Both sides of the second signal line 11b sequentially pass through the interlayer dielectric layer 10 and the gate insulating layer, and are electrically connected to the active layer 6 and the third gate region 7c, respectively. The intermediate section of the first signal line 11a and the intermediate section of the second signal line 11b are both located on the interlayer dielectric layer 10.
Optionally, the substrate 5 is at least one of a polyimide film layer, a barrier film layer, and a buffer film layer.
As an example, referring to fig. 8, a PI/Barrier/Buffer layer represents at least one of a PolyImide film, a Barrier film, and a Buffer film layer, and PI represents PolyImide, PolyImide; barrier represents a Barrier film layer, Buffer represents a Buffer film layer; P-Si is a polysilicon layer corresponding to the active layer 6; GI1 (Gate Insulator, GI) corresponding to the first Gate insulating layer 8; GI2 corresponding to the second gate insulating layer 9; EM (Emit, light-emitting signal line) indicating the light-emitting signal line 4 corresponding to the first gate region 7 a; gate, which represents a Gate corresponding to the second Gate region 7 b; VGH (Voltage High, gate High potential of the TFT thin film transistor), which corresponds to the gate signal line 3, the third gate region 7c, the ILD (Interlayer Dielectric), and the Interlayer Dielectric layer 10 in the embodiment of the present application; SD (Signal Line), SD on the left corresponds to the first Signal Line 11a, and SD on the right corresponds to the second Signal Line 11 b.
Based on the same inventive concept, the embodiment of the present application further provides a method for detecting edge damage of an opening 1 of a display panel, which is applied to the display panel of the first aspect, and includes the following steps:
if the edge of the opening 1 is not damaged, the switching device 2 is closed, and the grid signal line 3 does not output the first level signal;
if the edge of the opening 1 is broken, the switching device 2 is turned on, and the gate signal line 3 outputs a first level signal to the light emitting signal line 4.
Referring to fig. 2 and 3, the switching device 2 according to the embodiment of the present application will be described in detail with reference to a P-type TFT as an example. When the emission signal line 4, i.e., EM, is at the high potential of 7V, the gate signal line 3, i.e., VGH, outputs 7V (or other suitable potential), and if no Crack occurs at the edge of AA Hole, VGS-VG-VS-7V-0V, the switching device 2 is turned off, and the EM signal of the emission signal line 4 is not disturbed. When the EM is at the low potential-7V, VGH outputs 7V (or other suitable potential), where VGS-VS is 7V-0V, the switching device 2 is turned off, and the EM signal is not disturbed. When the EM is at the low potential of-7V, the VGH outputs 7V (or other suitable potential), and if a damaged Crack occurs at the AA Hole edge, the edge of the opening 1 is broken, the gate VG of the switching device 2 is 0V, the VGs is 0V-7V, the switching device 2 is turned on, the VGH signal of the gate signal line 3 is written, the EM signal of the light-emitting signal line 4 is disturbed, a horizontal bright line or a short horizontal bright line appears on a black screen, and it can be determined that a damaged Crack occurs at the AA Hole edge.
Optionally, when the switching devices 3 are all thin film transistors and also N-type TFTs or the first end and the second end of each transistor are different poles of the TFT, the electrical connection manner of each element in the pixel driving circuit provided in the embodiment of the present application may be adaptively adjusted, and the adaptively adjusted electrical connection manner still belongs to the protection scope of the embodiment of the present application.
Based on the same inventive concept, an embodiment of the present application further provides a method for manufacturing a display panel, which is applied to the display panel of the first aspect, and as shown in fig. 4, the method for manufacturing a display panel includes the following steps:
s401, an active layer 6 is provided on a substrate 5.
Optionally, step S401 is adopted to obtain a structure diagram shown in fig. 5, where a PI/Barrier/Buffer layer represents at least one of a PolyImide film, a Barrier film, and a Buffer film layer, and PI represents PolyImide, PolyImide; barrier represents a Barrier film layer, Buffer represents a Buffer film layer; P-Si is a polysilicon layer corresponding to the active layer 6; the active layer 6 covers a portion of the substrate 5.
Alternatively, after the source layer 6 is provided, a blank area of AA Hole may be deposited and doping of the threshold voltage of the switching device 2, i.e., the threshold voltage of the TFT, may be performed.
S402, a first gate insulating layer 8 is disposed on the side of the active layer 6 away from the substrate 5.
Alternatively, step S402 is adopted to obtain a structure diagram shown in fig. 6, i.e., GI1 (Gate Insulator, GI) corresponds to the first Gate Insulator 8; the first gate insulating layer 8 covers the entire active layer 6, serving as an insulator.
Alternatively, after the first gate insulating layer 8 is disposed, a TFT is prepared, and if the TFT is a P-type TFT, P-type doping is performed.
And S403, arranging a gate layer 7 on the side, away from the substrate 5, of the first gate insulating layer 8, wherein the gate layer 7 comprises a first gate region 7a, a second gate region 7b and a third gate region 7c, and the second gate region 7b is connected with the third gate region 7 c.
And S404, preparing an insulating layer on the side of the gate layer 7 away from the substrate 5.
Alternatively, after the steps S403 and S404 are performed, the structure diagram shown in fig. 7 is obtained, i.e., GI2 corresponds to the second gate insulating layer 9; EM (Emit, light-emitting signal line) indicating the light-emitting signal line 4 corresponding to the first gate region 7 a; gate, which represents a Gate corresponding to the second Gate region 7 b; VGH, which represents the threshold voltage for turning on the TFT, corresponds to the gate signal line 3, corresponds to the third gate region 7c, and corresponds to the Interlayer Dielectric layer 10. The insulating layer comprises an interlayer dielectric layer 10 and a second gate insulating layer 9, and the second gate insulating layer 9 covers the entire gate layer 7 to perform an insulating function.
Optionally, step S404 specifically includes: preparing a second gate insulating layer 9 on the side of the gate layer 7 away from the substrate 5; on the side of the second gate insulation layer 9 remote from the substrate 5, an interlayer dielectric layer 10 is prepared.
S405, respectively forming through holes in the insulating layer corresponding to the first gate region 7a, the third gate region 7c and the active layer 6.
Optionally, step S405 specifically includes: via holes are respectively formed in the interlayer dielectric layer 10 and the second gate insulating layer 9 at positions corresponding to the first gate region 7a and the third gate region 7 c; via holes are respectively formed in the interlayer dielectric layer 10, the second gate insulating layer 9, and the first gate insulating layer 8 corresponding to the active layer 6.
And S406, preparing a signal line on one side of each through hole and the insulating layer far away from the substrate 5, so that the first gate region 7a and the active layer 6 are electrically connected through the first signal line 11a in the signal line, and the third gate region 7c and the active layer 6 are electrically connected through the second signal line 11b in the signal line.
Alternatively, the structure shown in fig. 8 is obtained by using step S405 and step S406, where SD (Signal Line) corresponds to the first Signal Line 11a on the left side and the second Signal Line 11b on the right side.
Optionally, step S406 specifically includes: and filling a metal material in each through hole, and correspondingly connecting the metal materials in the two corresponding through holes through the metal material on the side of the insulating layer far away from the substrate 5, thereby forming a first signal line 11a and a second signal line 11 b. The signal line SD is made of a metal material, and Ti/Al/Ti (titanium/aluminum/titanium) may be used, and the Ti/Al/Ti layer is a Ti layer, an Al layer, and a Ti layer stacked in this order.
Alternatively, in practical applications, after depositing the insulating layer, a CNT Mask (Contact Mask) is modified to be punched, and a magnetron sputtering Sputter deposits an SD signal line as shown in fig. 8, so as to connect the gate layer 7 and the active layer 6 through the SD signal line via hole.
According to the embodiment of the application, an independent TFT is additionally arranged in the marginal blank area of the AA Hole, one end of the TFT is connected with a transverse light-emitting signal wire 4, namely a first gate area 7a, and is connected with an active layer 6 through a first signal wire 11a by SD punching, the other end of the TFT is connected with a separately led-out gate signal wire 3 through SD punching, namely a third gate area 7c, and the third gate area 7c winds around the AA Hole for a circle and is simultaneously connected with the gate of the TFT.
Based on the same inventive concept, the embodiment of the present application further provides a display device, including: the display panel of the first aspect.
Those of skill in the art will appreciate that the various operations, methods, steps in the processes, acts, or solutions discussed in this application can be interchanged, modified, combined, or eliminated. Further, other steps, measures, or schemes in various operations, methods, or flows that have been discussed in this application can be alternated, altered, rearranged, broken down, combined, or deleted. Further, steps, measures, schemes in the prior art having various operations, methods, procedures disclosed in the present application may also be alternated, modified, rearranged, decomposed, combined, or deleted.
In the description of the present application, it is to be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience in describing the present application and simplifying the description, but do not indicate or imply that the referred device or element must have a particular orientation, be constructed in a particular orientation, and be operated, and thus should not be construed as limiting the present application.
The terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless otherwise specified.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In the description herein, particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.
It should be understood that, although the steps in the flowcharts of the figures are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and may be performed in other orders unless explicitly stated herein. Moreover, at least a portion of the steps in the flow chart of the figure may include multiple sub-steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, which are not necessarily performed in sequence, but may be performed alternately or alternately with other steps or at least a portion of the sub-steps or stages of other steps.
The foregoing is only a partial embodiment of the present application, and it should be noted that, for those skilled in the art, several modifications and decorations can be made without departing from the principle of the present application, and these modifications and decorations should also be regarded as the protection scope of the present application.
Claims (10)
1. A display panel, comprising: a display region (12), an opening (1) located in the display region (12), a switching device (2) located at the periphery of the opening (1), a gate signal line (3) disposed around the opening (1), and a light emitting signal line (4);
a first end of the switching device (2) is electrically connected with the light-emitting signal line (4);
the second end of the switching device (2) is electrically connected with the signal input end of the grid signal wire (3);
the control end of the switching device (2) is electrically connected with the signal output end of the grid signal wire (3);
if the edge of the opening (1) is not broken, the grid signal line (3) is not broken and is electrically conducted with the control end of the switch device (2), and the switch device (2) is closed, so that the grid signal line (3) does not output a first level signal to the light-emitting signal line (4);
if the edge of the opening (1) is broken, the gate signal line (3) is broken, and the switching device (2) is turned on, so that the gate signal line (3) outputs the first level signal to the light emitting signal line (4).
2. A display panel according to claim 1, characterized in that the switching device (2) is a thin film transistor;
the control end of the thin film transistor is a grid electrode of the thin film transistor;
if the first end of the thin film transistor is the drain electrode of the thin film transistor, the second end of the thin film transistor is the source electrode of the thin film transistor;
and if the first end of the thin film transistor is the source electrode of the thin film transistor, the second end of the thin film transistor is the drain electrode of the thin film transistor.
3. The display panel according to claim 1, characterized in that the display panel further comprises: a substrate (5), an active layer (6) and a gate electrode layer (7) which are stacked on the substrate (5), and a gate insulating layer which is filled between the active layer (6) and the gate electrode layer (7);
the gate layer (7) comprises a first gate region (7a), a second gate region (7b) and a third gate region (7c), and the second gate region (7b) is connected with the third gate region (7 c);
the first gate region (7a) serves as a light emitting signal line (4), and the third gate region (7c) serves as a gate signal line (3);
the first gate region (7a) and the active layer (6) are electrically connected by a first signal line (11 a);
the third gate region (7c) and the active layer (6) are electrically connected by a second signal line (11 b).
4. The display panel according to claim 3, further comprising an interlayer dielectric layer (10) stacked on the gate insulating layer;
both sides of the first signal line (11a) sequentially penetrate through the interlayer dielectric layer (10) and the gate insulating layer and are respectively and electrically connected with the first gate region (7a) and the active layer (6);
both sides of the second signal line (11b) sequentially penetrate through the interlayer dielectric layer (10) and the gate insulating layer and are respectively and electrically connected with the active layer (6) and the third gate region (7 c);
the intermediate section of the first signal line (11a) and the intermediate section of the second signal line (11b) are both located on the interlayer dielectric layer (10).
5. The display panel according to claim 3, wherein the substrate (5) is at least one of a polyimide film layer, a barrier film layer, and a buffer film layer.
6. A method for detecting edge breakage of a hole (1) in a display panel, applied to a display panel according to any one of claims 1 to 5, comprising the steps of:
if the edge of the opening (1) is not damaged, the switching device (2) is closed, and the grid signal line (3) does not output a first level signal;
if the edge of the opening (1) is damaged, the switching device (2) is conducted, and the grid signal line (3) outputs a first level signal to the light-emitting signal line (4).
7. A method for manufacturing a display panel, applied to the display panel according to any one of claims 1 to 5, comprising the steps of:
an active layer (6) is arranged on the substrate (5);
-providing a first gate insulation layer (8) on a side of the active layer (6) remote from the substrate (5);
arranging a gate layer (7) on the side of the first gate insulating layer (8) far away from the substrate (5), wherein the gate layer (7) comprises a first gate region (7a), a second gate region (7b) and a third gate region (7c), and the second gate region (7b) is connected with the third gate region (7 c);
preparing an insulating layer on the side of the gate layer (7) far away from the substrate (5);
through holes are respectively formed in the insulating layer corresponding to the first gate region (7a), the third gate region (7c) and the active layer (6);
preparing a signal line on a side of each of the via holes and the insulating layer away from the substrate (5) such that the first gate region (7a) and the active layer (6) are electrically connected by a first signal line (11a) of the signal lines, and the third gate region (7c) and the active layer (6) are electrically connected by a second signal line (11b) of the signal lines.
8. The method of manufacturing a display panel according to claim 7, wherein, on a side of the gate layer (7) away from the substrate (5), an insulating layer is manufactured including:
preparing a second gate insulating layer (9) on the side of the gate layer (7) away from the substrate (5);
an interlayer dielectric layer (10) is prepared on the side of the second gate insulating layer (9) away from the substrate (5).
9. The method for manufacturing a display panel according to claim 8, wherein via holes are respectively formed in the insulating layer corresponding to the first gate region (7a), the third gate region (7c) and the active layer (6), and the method comprises:
respectively forming through holes in the interlayer dielectric layer (10) and the second gate insulating layer (9) corresponding to the first gate region (7a) and the third gate region (7 c);
through holes are respectively formed in the interlayer dielectric layer (10), the second grid electrode insulating layer (9) and the first grid electrode insulating layer (8) corresponding to the active layer (6); and the number of the first and second groups,
preparing a signal line on a side of each of the via holes and the insulating layer away from the substrate (5) such that the first gate region (7a) and the active layer (6) are electrically connected by a first one (11a) of the signal lines and the third gate region (7c) and the active layer (6) are electrically connected by a second one (11b) of the signal lines, comprising:
and filling metal materials in the through holes, and correspondingly connecting the metal materials in the two through holes through the metal materials on one side of the insulating layer far away from the substrate (5) so as to form the first signal line (11a) and the second signal line (11 b).
10. A display device, comprising: the display panel of any one of claims 1-5.
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