CN111220897A - Power calibration method, device and system and test system - Google Patents
Power calibration method, device and system and test system Download PDFInfo
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Abstract
The invention provides a power calibration method, a device, a system and a test system, comprising the following steps: the vector signal transceiver outputs at least two first input powers so that the vector signal transceiver transmits the at least two first input powers to the driver amplifier; acquiring second input power corresponding to each first input power, and generating a corresponding relation between the first input power and the second input power, wherein the power of the first input power, which is amplified by the driving amplifier and transmitted to the chip to be tested through the transmission line, is the second input power corresponding to the first input power; determining at least two target second input powers according to preset values, wherein after the at least two target second input powers are arranged according to the sizes, the difference value between any two adjacent target second input powers is a preset value; and determining target first input power corresponding to each target second input power according to the corresponding relation between the first input power and the second input power. The scheme can reduce the calibration error.
Description
Technical Field
The present invention relates to the field of computer technologies, and in particular, to a power calibration method, device, system, and test system.
Background
In many application fields such as communication and radar, a radio frequency power amplifier is a main component of a radio frequency transmitting system. Currently, transceiver systems of wireless communication and radar are developing towards high integration and microminiaturization, and radio frequency power amplifier chips are widely applied to transceiver systems of wireless communication, internet of things, radar and the like.
In the prior art, a vector network analyzer is generally adopted to detect the performance of a radio frequency power amplifier chip, and a set of calibration kit is used for calibrating related devices. The vector network analyzer uses a separate calibration to calibrate each device in the system individually, and then determines the degree of calibration comprehensively.
As can be seen from the above description, the devices need to be connected into the system to work together as a whole, and since the devices have mutual influence, the precision of the devices working together cannot be optimized to the best precision in the individual calibration, so that a large calibration error exists.
Disclosure of Invention
The embodiment of the invention provides a power calibration method, a device, a system and a test system, which can reduce calibration errors.
In a first aspect, an embodiment of the present invention provides a power calibration method, including:
outputting at least two first input powers by a vector signal transceiver so that the vector signal transceiver transmits the at least two first input powers to a driver amplifier, wherein the at least two first input powers are the first input powers of at least two single-tone signals emitted by the vector signal transceiver;
acquiring second input power corresponding to each first input power, and generating a corresponding relation between the first input power and the second input power, wherein the power of the first input power, which is amplified by the driving amplifier and transmitted to the chip to be tested through the transmission line, is the second input power corresponding to the first input power;
determining at least two target second input powers according to a preset value, wherein after the at least two target second input powers are arranged according to the size, the difference value between any two adjacent target second input powers is the preset value;
and determining target first input power corresponding to each target second input power according to the corresponding relation between the first input power and the second input power.
Preferably, the first and second electrodes are formed of a metal,
determining a target first input power corresponding to each target second input power according to the corresponding relationship between the first input power and the second input power, including:
establishing a rectangular coordinate system, wherein the abscissa is the first input power, and the ordinate is the second input power;
drawing a characteristic curve according to the corresponding relation between the first input power and the second input power;
and determining the target first input power corresponding to each target second input power from the characteristic curve.
Preferably, the first and second electrodes are formed of a metal,
the determining, from the characteristic curve, a target first input power corresponding to each target second input power includes:
for each of the target second input powers, performing:
when the current target second input power is not in the correspondence,
determining two nearest second input powers with the minimum absolute value of the difference value with the current target second input power from the corresponding relation;
determining a first input power corresponding to each nearest second input power according to the corresponding relation;
determining the target first input power corresponding to the current target second input power according to the following formula:
wherein, y0And y1For two of said nearest second input powers, x0Is y0Corresponding first input power, x1Is y1And y is the current target second input power, and x is the target first input power corresponding to the current target second input power.
Preferably, the first and second electrodes are formed of a metal,
determining a target first input power corresponding to each target second input power according to the corresponding relationship between the first input power and the second input power, including:
s1, putting each second input power in the corresponding relation into a preset set;
s2, determining the minimum second input power from the preset set, and taking the minimum second input power as an intermediate parameter;
s3: judging whether the sum of the intermediate parameter and the preset value is in the preset set, if so, executing S4, otherwise, executing S5;
s4: recording a second input power corresponding to the sum of the intermediate parameter and the preset value, taking the second input power corresponding to the sum of the intermediate parameter and the preset value as the intermediate parameter, and returning to the step S3;
s5: judging whether the intermediate parameter is the minimum value in the preset set, if so, executing S6, otherwise, executing S7;
s6: deleting the second input power corresponding to the intermediate parameter from the preset set, and returning to the step S2;
s7: performing S8 with the recorded second input power as the target second input power;
s8: and taking the first input power corresponding to each target second input power in the corresponding relation as the target first input power.
In a second aspect, the present invention provides a power calibration apparatus, comprising:
an input module, configured to output at least two first input powers by a vector signal transceiver, so that the vector signal transceiver transmits the at least two first input powers to a driver amplifier, where the at least two first input powers are the first input powers of at least two tone signals transmitted by the vector signal transceiver;
the processing module is configured to obtain a second input power corresponding to each first input power received by the input module, and generate a corresponding relationship between the first input power and the second input power, where the power that the first input power is amplified by the driver amplifier and transmitted to the chip to be tested through the transmission line is the second input power corresponding to the first input power;
a first determining module, configured to determine, according to a preset value, at least two target second input powers from the second input powers acquired by the processing module, where after the at least two target second input powers are arranged according to sizes, a difference between any two adjacent target second input powers is the preset value;
and a second determining module, configured to determine, according to a correspondence between the first input power and the second input power generated by the processing module, a target first input power corresponding to the target second input power determined by each of the first determining modules.
Preferably, the first and second electrodes are formed of a metal,
the second determining module includes:
the establishing unit is used for establishing a rectangular coordinate system, wherein the abscissa is the first input power, and the ordinate is the second input power;
the drawing unit is used for drawing a characteristic curve according to the corresponding relation between the first input power and the second input power generated by the processing module;
and the determining unit is used for determining the target first input power corresponding to each target second input power from the characteristic curve drawn by the drawing unit.
Preferably, the first and second electrodes are formed of a metal,
the second determining module is configured to, for each target second input power, perform:
when the current target second input power is not in the correspondence,
determining two nearest second input powers with the minimum absolute value of the difference value with the current target second input power from the corresponding relation;
determining a first input power corresponding to the second input power of each closest point according to the corresponding relation;
determining the target first input power corresponding to the current target second input power according to the following formula:
wherein, y0And y1For two of said nearest second input powers, x0Is y0Corresponding first input power, x1Is y1And y is the current target second input power, and x is the target first input power corresponding to the current target second input power.
Preferably, the first and second electrodes are formed of a metal,
the second determining module is configured to perform:
s1, putting each second input power in the corresponding relation into a preset set;
s2, determining the minimum second input power from the preset set, and taking the minimum second input power as an intermediate parameter;
s3: judging whether the sum of the intermediate parameter and the preset value is in the preset set, if so, executing S4, otherwise, executing S5;
s4: recording a second input power corresponding to the sum of the intermediate parameter and the preset value, taking the second input power corresponding to the sum of the intermediate parameter and the preset value as the intermediate parameter, and returning to the step S3;
s5: judging whether the intermediate parameter is the minimum value in the preset set, if so, executing S6, otherwise, executing S7;
s6: deleting the second input power corresponding to the intermediate parameter from the preset set, and returning to S2;
s7: performing S8 with the recorded second input power as the target second input power;
s8: and taking the first input power corresponding to each target second input power in the corresponding relation as the target first input power.
In a third aspect, the present invention provides a power calibration system comprising: a vector signal transceiver, a driver amplifier and the power calibration apparatus of any of the second aspect;
the vector signal transceiver is used for receiving at least two first input powers input by the power calibration device and sending the at least two first input powers to the drive amplifier;
the driving amplifier is used for amplifying the at least two first input powers sent by the vector signal transceiver, outputting the amplified powers, and transmitting the amplified powers to a chip to be tested through a transmission line.
In a fourth aspect, the present invention provides a test system comprising: a vector signal transceiver and a driver amplifier;
the vector signal transceiver is used for receiving at least two target first input powers input by external equipment and sending the at least two target first input powers to the driving amplifier;
the driving amplifier is used for amplifying the at least two target first input powers sent by the vector signal transceiver, outputting the amplified powers, and transmitting the amplified powers to a chip to be tested through a transmission line.
The embodiment of the invention provides a power calibration method, a device, a system and a test system, in view of the test requirement of a chip to be tested, after the input power of a vector signal transceiver is amplified by a drive amplifier, the power measured at a port before entering the chip to be tested is linear power, however, due to the influence caused by the nonlinearity of the vector signal transceiver and the drive amplifier and the nonlinearity of a transmission line, the power measured at the port before entering the chip to be tested cannot completely meet the test requirement of the chip to be tested, and therefore, the second input power before entering the chip to be tested needs to be calibrated. Because the chip to be tested is a power amplifier chip of the base station and has larger power, a drive amplifier is added behind a transmission line of the vector signal transceiver for adjustment in order to achieve the test effect, so that the high power required by the chip to be tested is obtained. At least two first input powers are input to the vector signal transceiver, after the first input powers are amplified by the driving amplifier, a second input power of each first input power, which enters the chip to be tested, is obtained by a power meter, the second input power is not necessarily linear at the moment, so that the target second output power is determined according to a preset value, each target second input power is linear, each corresponding target first input power is determined according to the corresponding relation between the first input power and the second input power, each target first input power is input to the vector signal transceiver, and the measured second input power entering the chip to be tested is also linear, so that the second input power before entering the chip to be tested can be calibrated, and the test requirement of the chip to be tested is met. The invention can avoid the calibration error caused by the mutual influence of each device to be calibrated and the nonlinear influence of the transmission line after the vector network analyzer is calibrated independently, thereby improving the calibration precision.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a flowchart of a power calibration method according to an embodiment of the present invention;
FIG. 2 is a flow chart of another power calibration method provided by an embodiment of the invention;
FIG. 3 is a flow chart of another power calibration method according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a power calibration apparatus according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of another power calibration apparatus according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a power calibration system according to an embodiment of the present invention;
fig. 7 is a schematic diagram of a test system according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer and more complete, the technical solutions in the embodiments of the present invention will be described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention, and based on the embodiments of the present invention, all other embodiments obtained by a person of ordinary skill in the art without creative efforts belong to the scope of the present invention.
In the test system of the radio frequency power amplifier chip, the output end of a vector signal transceiver is connected with the input end of a drive amplifier through a transmission line, the output end of the drive amplifier is connected with the input end of a chip to be tested through the transmission line, the output end of the chip to be tested is connected with the input end of an attenuator through the transmission line, and the output end of the attenuator is connected with the input end of the vector signal transceiver through the transmission line. Because the output power of the chip to be tested is larger, in order to improve the service performance of the vector transceiver, an attenuator is connected to the output end of the chip to be tested. In the prior art, a vector network analyzer is generally adopted to detect the performance of a radio frequency power amplifier chip, and a set of calibration kit is used for calibrating related devices. The vector network analyzer needs to be connected with each device to be calibrated independently, so that the error of each device to be calibrated is the minimum, however, because transmission lines need to be connected among the devices and are arranged in the system to participate in the work as a whole, the devices have mutual influence, the working error of the system cannot reach the optimal effect of independent calibration of the devices, and the transmission lines among the devices also have nonlinear influence, so that larger error exists. Compared with a vector signal transceiver, the vector network analyzer is higher in cost, indexes for testing the chip to be tested are limited, and some indexes cannot be tested. The vector network analyzer reads data slower than the vector signal transceiver. The scheme can reduce the error of calibration, reduce the cost and improve the data reading speed on the basis of not changing the original system circuit.
As shown in fig. 1, an embodiment of the present invention provides a power calibration method, which may include the following steps:
a vector signal transceiver outputs at least two first input powers so that the vector signal transceiver sends the at least two first input powers to a drive amplifier, wherein the at least two first input powers are the first input powers of at least two single-tone signals sent by the vector signal transceiver;
102, acquiring second input power corresponding to each first input power, and generating a corresponding relation between the first input power and the second input power, wherein the power of the first input power, which is amplified by the driving amplifier and transmitted to the chip to be tested through the transmission line, is the second input power corresponding to the first input power;
103, determining at least two target second input powers according to preset values, wherein after the at least two target second input powers are arranged according to sizes, the difference value between any two adjacent target second input powers is a preset value;
and 104, determining target first input power corresponding to each target second input power according to the corresponding relation between the first input power and the second input power.
In the embodiment of the present invention, in view of the requirement of the chip to be tested, after the input power of the vector signal transceiver is amplified by the driving amplifier, the power measured at the port before entering the chip to be tested should be a linear power, however, due to the influence caused by the nonlinearity of the vector signal transceiver and the driving amplifier and the nonlinearity of the transmission line, the power measured at the port before entering the chip to be tested cannot completely meet the requirement of the chip to be tested, so that the second input power before entering the chip to be tested needs to be calibrated. Because the chip to be tested is a power amplifier chip of the base station and has larger power, a drive amplifier is added behind a transmission line of the vector signal transceiver for adjustment in order to achieve the test effect, so that the high power required by the chip to be tested is obtained. At least two first input powers are input to the vector signal transceiver, after the first input powers are amplified by the driving amplifier, a second input power of each first input power, which enters the chip to be tested, is obtained by a power meter, the second input power is not necessarily linear at the moment, so that the target second output power is determined according to a preset value, each target second input power is linear, each corresponding target first input power is determined according to the corresponding relation between the first input power and the second input power, each target first input power is input to the vector signal transceiver, and the measured second input power entering the chip to be tested is also linear, so that the second input power before entering the chip to be tested can be calibrated, and the test requirement of the chip to be tested is met. The invention can avoid the calibration error caused by the mutual influence of each device to be calibrated and the nonlinear influence of the transmission line after the vector network analyzer is calibrated independently, thereby improving the calibration precision.
In order to determine a target first input power meeting a test requirement of a chip to be tested, in an embodiment of the present invention, determining a target first input power corresponding to each target second input power according to a corresponding relationship between the first input power and the second input power includes:
establishing a rectangular coordinate system, wherein the abscissa is the first input power, and the ordinate is the second input power;
drawing a characteristic curve according to the corresponding relation between the first input power and the second input power;
and determining the target first input power corresponding to each target second input power from the characteristic curve.
In the embodiment of the present invention, since each of the first input powers and the second input powers is in a one-to-one correspondence relationship, a characteristic curve that can represent the correspondence relationship between each of the first input powers and the second input powers can be plotted with the first input power as an abscissa and the second input power as an ordinate. In view of the test requirement of the chip to be tested, the second input power required to be input into the chip to be tested is linear, so that the corresponding target first input power can be determined according to the determined target second input power and the drawn characteristic curve, namely the target first input power meeting the test requirement.
In order to determine the target first input power corresponding to the target second input power that is not in the corresponding relationship, in an embodiment of the present invention, the determining the target first input power corresponding to each target second input power from the characteristic curve includes:
for each of the target second input powers, performing:
when the current target second input power is not in the correspondence,
determining two nearest second input powers with the minimum absolute value of the difference value with the current target second input power from the corresponding relation;
determining a first input power corresponding to the second input power of each closest point according to the corresponding relation;
determining the target first input power corresponding to the current target second input power according to the following formula:
wherein, y0And y1For two of said nearest second input powers, x0Is y0Corresponding first input power, x1Is y1And y is the current target second input power, and x is the target first input power corresponding to the current target second input power.
In the embodiment of the present invention, when the target second input power is not in the one-to-one correspondence relationship defined between the first input power and the second input power, the target first power corresponding to the current target second input power to be defined needs to be calculated by using the one-dimensional linear difference method. First, two nearest second input powers with the minimum absolute value of the difference value with the current target second input power are determined, first input powers corresponding to the two nearest second input powers can be determined according to the corresponding relation between the first input powers and the second input powers, the first input powers are substituted into the formula, and then the target first input power corresponding to the current target second input power to be determined can be obtained.
In order to determine a target first input power corresponding to a target second input power that is not in a corresponding relationship, in an embodiment of the present invention, the determining a target first input power corresponding to each target second input power according to a corresponding relationship between the first input power and the second input power includes:
s1, putting each second input power in the corresponding relation into a preset set;
s2, determining the minimum second input power from the preset set, and taking the minimum second input power as an intermediate parameter;
s3: judging whether the sum of the intermediate parameter and the preset value is in the preset set, if so, executing S4, otherwise, executing S5;
s4: recording a second input power corresponding to the sum of the intermediate parameter and the preset value, taking the second input power corresponding to the sum of the intermediate parameter and the preset value as the intermediate parameter, and returning to the step S3;
s5: judging whether the intermediate parameter is the minimum value in the preset set, if so, executing S6, otherwise, executing S7;
s6: deleting the second input power corresponding to the intermediate parameter from the preset set, and returning to S2;
s7: performing S8 with the recorded second input power as the target second input power;
s8: and taking the first input power corresponding to each target second input power in the corresponding relation as the target first input power.
In the embodiment of the present invention, since the first input power and the second input power are in one-to-one correspondence, the respective corresponding first input power and second input power can be put into a preset set as a combination. Since the second input power input to the chip to be tested needs to be linear, a target second input power meeting the test requirement needs to be determined. And determining the minimum value of the second input power as an intermediate parameter from a preset set, and determining whether the second input power with the value of the sum of the intermediate parameter and the preset value exists in the preset set or not according to the size of the preset value. If the intermediate parameter exists, the current second input power is the current target second input power, the intermediate parameter and the target first input power corresponding to the current target second input power can be determined according to the corresponding relation, if the intermediate parameter does not exist, the minimum value is deleted, the minimum value in the preset set is determined again to be used as the intermediate parameter, and the second input power with the numerical value in the preset set being the sum of the intermediate parameter and the preset value is found to be used as the target second input power.
As shown in fig. 2, in order to more clearly illustrate the technical solution and the advantages of the present invention, the following detailed description of the power calibration method provided in the embodiment of the present invention may specifically include the following steps:
step 201: outputting at least two first input powers by a vector signal transceiver so that the vector signal transceiver transmits the at least two first input powers to a driver amplifier, wherein the at least two first input powers are the first input powers of at least two single-tone signals emitted by the vector signal transceiver;
step 202: acquiring second input power corresponding to each first input power, and generating a corresponding relation between the first input power and the second input power, wherein the power of the first input power, which is amplified by the driving amplifier and transmitted to the chip to be tested through the transmission line, is the second input power corresponding to the first input power;
specifically, after first input power input to the vector signal transceiver is amplified by the driving amplifier, the power before the first input power enters the chip to be tested is second input power, and each corresponding first input power has a second input power corresponding to the first input power.
For example, assuming that the gain of the driver amplifier is 20dB, the driver amplifier can amplify the power entering the driver amplifier by 100 times, assuming that the first input power inputted to the vector signal transceiver is 10dBm and 20dBm, the power amplified by the driver amplifier is 30dBm and 40dBm, which is the second input power, and the second input power 30dBm corresponds to the first input power of 10dBm, and the second input power 40dBm corresponds to the first input power of 20 dBm.
Step 203: determining at least two target second input powers according to preset values, wherein after the at least two target second input powers are arranged according to the sizes, the difference value between any two adjacent target second input powers is a preset value;
specifically, in view of the test requirement of the chip to be tested, the second input power before being input to the chip to be tested must be linear, so at least two linear target second input powers need to be determined to be input to the chip to be tested, so as to implement the test of the chip to be tested.
For example, if the preset value is 1dBm, the target second input powers may be 10dBm, 11dBm, 12dBm, 13dBm, etc., and the difference between any two adjacent target second input powers is 1dBm, the target second input powers may be input to the chip to be tested, so as to meet the test requirement of the chip to be tested.
Step 204: establishing a rectangular coordinate system, wherein the abscissa is the first input power, and the ordinate is the second input power;
step 205: drawing a characteristic curve according to the corresponding relation between the first input power and the second input power;
specifically, since there is a one-to-one correspondence between the respective first input powers and the respective second input powers, a characteristic curve representing the correspondence between the first input powers and the second input powers may be plotted.
Step 206: and determining the target first input power corresponding to each target second input power according to the characteristic curve.
Specifically, since each first input power and each second input power are in a corresponding relationship, the target first input power corresponding to each target second input power can be determined according to the characteristic curve.
Step 207: when the current target second input power is not in the corresponding relation, determining two nearest second input powers with the minimum absolute value of the difference value with the current target second input power from the corresponding relation;
step 208: determining a first input power corresponding to the second input power of each closest point according to the corresponding relation;
step 209: determining the target first input power corresponding to the current target second input power according to the following formula:
wherein, y0And y1For two of said nearest second input powers, x0Is y0Corresponding first input power, x1Is y1And y is the current target second input power, and x is the target first input power corresponding to the current target second input power.
For example, assuming that the current target second input power y is 24.7dBm, two nearest second input powers y having the smallest absolute value of the difference from the current target second input power y0Is 24dBm, y1At 25dBm, the corresponding first input power x can be determined from the characteristic curve0Is 10dBm, x1Is 20dBm and x can be calculated to be 17dBm by the above formula, i.e. 17dBm is the target first input power corresponding to 24.7 dBm.
As shown in fig. 3, another power calibration method is provided in the embodiment of the present invention, and the method includes the following steps:
step 301: outputting at least two first input powers by a vector signal transceiver so that the vector signal transceiver transmits the at least two first input powers to a driver amplifier, wherein the at least two first input powers are the first input powers of at least two single-tone signals emitted by the vector signal transceiver;
step 302: acquiring second input power corresponding to each first input power, and generating a corresponding relation between the first input power and the second input power, wherein the power of the first input power, which is amplified by the driving amplifier and transmitted to the chip to be tested through the transmission line, is the second input power corresponding to the first input power;
303, putting each second input power in the corresponding relation into a preset set;
305, judging whether the sum of the intermediate parameter and the preset value is in a preset set, if so, executing 306, otherwise, executing 307;
307, judging whether the intermediate parameter is the minimum value in a preset set, if so, executing a step 308, otherwise, executing a step 309;
step 308: deleting the second input power corresponding to the intermediate parameter from the preset set, and returning to the step 304;
step 309: taking the recorded second input power as the target second input power, executing step 310;
step 310: and taking the first input power corresponding to each target second input power in the corresponding relation as the target first input power.
For example, assuming that the second input powers in the preset set are 10dBm, 11dBm, 11.1dBm, 11.2dBm, 12dBm, 12.1dBm, 13dBm, and 14dBm, assuming that the preset value is 1dBm, the determined minimum second input power is 10dBm, and taking 10dBm as a middle parameter, it may be determined that the next second input power should be 11dBm of the sum of the middle 10dBm and the preset value 1dBm, and so on, the determined target second input powers are 10dBm, 11dBm, 12dBm, 13dBm, and 14dBm, and the corresponding target first input power may be determined according to the corresponding relationship between the first input power and the second input power.
Assuming that the preset value is 0.1dBm, the determined minimum second input power is still 10dBm, and 10dBm is taken as a middle parameter, 10.1dBm of the sum of the middle parameter 10dBm and the preset value 0.1dBm is not in the preset set, so 10dBm is deleted from the preset set, the next minimum second input power 11dBm is re-determined as the middle parameter, it can be known that the requirement is met, 11.1dBm of the sum of the middle parameter 11dBm and the preset value 0.1dBm is in the preset set, 11.1dBm is taken as the middle parameter, 11.2dBm of the sum of the middle parameter 11.1dBm and the preset value 0.1dBm is in the preset set, and in conclusion, the target second input powers can be determined to be 11dBm, 11.1dBm, and 11.2 dBm.
As shown in fig. 4, an embodiment of the present invention provides a power calibration apparatus, including:
an input module 401, configured to output at least two first input powers by a vector signal transceiver, so that the vector signal transceiver transmits the at least two first input powers to a driver amplifier, where the at least two first input powers are the first input powers of at least two single-tone signals transmitted by the vector signal transceiver;
a processing module 402, configured to obtain a second input power corresponding to each first input power received by the input module 401, and generate a corresponding relationship between the first input power and the second input power, where a power that the first input power is amplified by the driver amplifier and transmitted to the chip to be tested through the transmission line is the second input power corresponding to the first input power;
a first determining module 403, configured to determine at least two target second input powers from the second input powers obtained by the processing module 402 according to preset values, where after the at least two target second input powers are arranged according to sizes, a difference between any two adjacent target second input powers is the preset value;
a second determining module 404, configured to determine, according to the correspondence between the first input power generated by the processing module 402 and the second input power, a target first input power corresponding to the target second input power determined by each of the first determining modules 403.
In the embodiment of the present invention, in view of the requirement of the chip to be tested for testing, after the input power of the vector signal transceiver is amplified by the driving amplifier, the power measured at the port before entering the chip to be tested should be linear power, however, due to the influence caused by the nonlinearity of the vector signal transceiver and the driving amplifier and the nonlinearity of the transmission line, the power measured at the port before entering the chip to be tested cannot completely meet the requirement of the chip to be tested for testing, and therefore, the second input power before entering the chip to be tested needs to be calibrated. Because the chip to be tested is a power amplifier chip of the base station and has larger power, a drive amplifier is added behind a transmission line of the vector signal transceiver for adjustment in order to achieve the test effect, so that the high power required by the chip to be tested is obtained. The input module inputs at least two first input powers to the vector signal transceiver, after the input powers are processed by the processing module, the available power meter can obtain a second input power of each first input power, which enters the chip to be tested, corresponding to the second input power, at the moment, the second input power is not necessarily linear, therefore, a first determining module is needed to determine a target second output power according to a preset value, each target second input power is made to be linear, and according to the corresponding relation between the first input power and the second input power, a second determining module determines each corresponding target first input power, at the moment, each target first input power is input to the vector signal transceiver, the measured second input power entering the chip to be tested is also linear, so that the second input power before entering the chip to be tested can be calibrated, and the test requirements of the chip to be tested are met.
Based on the power calibration apparatus of fig. 4, as shown in fig. 5, in an embodiment of the invention, the second determining module 404 includes:
the establishing unit 4041 is configured to establish a rectangular coordinate system, where an abscissa is the first input power and an ordinate is the second input power;
a drawing unit 4042, configured to draw a characteristic curve according to a correspondence between the first input power and the second input power generated by the processing module;
a determining unit 4043, configured to determine, from the characteristic curve drawn by the drawing unit, a target first input power corresponding to each target second input power.
In an embodiment of the present invention, the second determining module 404 is configured to, for each target second input power, perform:
when the current target second input power is not in the correspondence,
determining two nearest second input powers with the minimum absolute value of the difference value with the current target second input power from the corresponding relation;
determining a first input power corresponding to the second input power of each closest point according to the corresponding relation;
determining the target first input power corresponding to the current target second input power according to the following formula:
wherein, y0And y1For two of said nearest second input powers, x0Is y0Corresponding first input power, x1Is y1And y is the current target second input power, and x is the target first input power corresponding to the current target second input power.
In an embodiment of the present invention, the second determining module 404 is configured to perform:
s1, putting each second input power in the corresponding relation into a preset set;
s2, determining the minimum second input power from the preset set, and taking the minimum second input power as an intermediate parameter;
s3: judging whether the sum of the intermediate parameter and the preset value is in the preset set, if so, executing S4, otherwise, executing S5;
s4: recording a second input power corresponding to the sum of the intermediate parameter and the preset value, taking the second input power corresponding to the sum of the intermediate parameter and the preset value as the intermediate parameter, and returning to the step S3;
s5: judging whether the intermediate parameter is the minimum value in the preset set, if so, executing S6, otherwise, executing S7;
s6: deleting the second input power corresponding to the intermediate parameter from the preset set, and returning to S2;
s7: performing S8 with the recorded second input power as the target second input power;
s8: and taking the first input power corresponding to each target second input power in the corresponding relation as the target first input power.
As shown in fig. 6, an embodiment of the present invention further provides a power calibration system, including: a vector signal transceiver 601, a driver amplifier 602, and a power calibration device 603;
the vector signal transceiver 601 is configured to receive at least two first input powers input by the power calibration apparatus 603, and send the at least two first input powers to a driver amplifier;
the driver amplifier 602 is configured to amplify the at least two first input powers sent by the vector signal transceiver, output the amplified powers, and transmit the amplified powers to a chip to be tested through a transmission line.
In the embodiment of the invention, the vector signal transceiver receives at least two input first input powers and sends the first input powers to the driving amplifier, and the driving amplifier can amplify the first input powers and send the amplified powers to the chip to be tested so as to meet the test requirement of the chip to be tested.
As shown in fig. 7, an embodiment of the present invention further provides a test system, including: a vector signal transceiver 601 and a driver amplifier 602;
the vector signal transceiver 601 is configured to receive at least two target first input powers input by an external device, and send the at least two target first input powers to a driver amplifier;
the driver amplifier 602 is configured to amplify the at least two target first input powers sent by the vector signal transceiver, output the amplified powers, and transmit the amplified powers to a chip to be tested through a transmission line. The target first input power in the test system is generated by the power calibration apparatus in the embodiment of the present invention.
In the embodiment of the present invention, in view of the test requirement of the chip to be tested, the second input power before entering the chip to be tested should be linear, so that a target second input power meeting the test requirement of the chip to be tested needs to be determined, and the target first input power is determined according to the corresponding relationship between the first input power and the second input power, and the power obtained by inputting the target first power into the vector signal transceiver and amplifying the target first power by the driving amplifier is the target second input power.
It is to be understood that the illustrated structure of the embodiment of the present invention does not constitute a specific limitation to the power calibration apparatus. In other embodiments of the invention, the power calibration means may comprise more or fewer components than shown, or some components may be combined, some components may be split, or a different arrangement of components. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.
Because the information interaction, execution process, and other contents between the units in the device are based on the same concept as the method embodiment of the present invention, specific contents may refer to the description in the method embodiment of the present invention, and are not described herein again.
An embodiment of the present invention further provides a power calibration apparatus, including: at least one memory and at least one processor;
the at least one memory to store a machine readable program;
the at least one processor is configured to invoke the machine readable program to perform the power calibration method of any embodiment of the invention.
Embodiments of the present invention further provide a computer-readable medium, on which computer instructions are stored, and when executed by a processor, the computer instructions cause the processor to execute the power calibration method in any embodiment of the present invention. Specifically, a system or an apparatus equipped with a storage medium on which software program codes that realize the functions of any of the above-described embodiments are stored may be provided, and a computer (or a CPU or MPU) of the system or the apparatus is caused to read out and execute the program codes stored in the storage medium.
In this case, the program code itself read from the storage medium can realize the functions of any of the above-described embodiments, and thus the program code and the storage medium storing the program code constitute a part of the present invention.
Examples of the storage medium for supplying the program code include a floppy disk, a hard disk, a magneto-optical disk, an optical disk (e.g., CD-ROM, CD-R, CD-RW, DVD-ROM, DVD-RAM, DVD-RW, DVD + RW), a magnetic tape, a nonvolatile memory card, and a ROM. Alternatively, the program code may be downloaded from a server computer via a communications network.
Further, it should be clear that the functions of any one of the above-described embodiments may be implemented not only by executing the program code read out by the computer, but also by causing an operating system or the like operating on the computer to perform a part or all of the actual operations based on instructions of the program code.
Further, it is to be understood that the program code read out from the storage medium is written to a memory provided in an expansion board inserted into the computer or to a memory provided in an expansion unit connected to the computer, and then causes a CPU or the like mounted on the expansion board or the expansion unit to perform part or all of the actual operations based on instructions of the program code, thereby realizing the functions of any of the above-described embodiments.
The embodiments of the invention have at least the following beneficial effects:
1. in an embodiment of the present invention, in view of the requirement of the chip to be tested, after the input power of the vector signal transceiver is amplified by the driving amplifier, the power measured at the port before entering the chip to be tested should be a linear power, however, due to the influence caused by the nonlinearity of the vector signal transceiver and the driving amplifier and the nonlinearity of the transmission line, the power measured at the port before entering the chip to be tested cannot completely meet the requirement of the chip to be tested, so that the second input power before entering the chip to be tested needs to be calibrated. Because the chip to be tested is a power amplifier chip of the base station and has larger power, a drive amplifier is added behind a transmission line of the vector signal transceiver for adjustment in order to achieve the test effect, so that the high power required by the chip to be tested is obtained. At least two first input powers are input to the vector signal transceiver, after the first input powers are amplified by the driving amplifier, a second input power of each first input power, which enters the chip to be tested, is obtained by a power meter, the second input power is not necessarily linear at the moment, so that the target second output power is determined according to a preset value, each target second input power is linear, each corresponding target first input power is determined according to the corresponding relation between the first input power and the second input power, each target first input power is input to the vector signal transceiver, and the measured second input power entering the chip to be tested is also linear, so that the second input power before entering the chip to be tested can be calibrated, and the test requirement of the chip to be tested is met. The invention can avoid the calibration error caused by the mutual influence of each device to be calibrated and the nonlinear influence of the transmission line after the vector network analyzer is calibrated independently, thereby improving the calibration precision.
2. In an embodiment of the present invention, since each of the first input powers and the second input powers is in a one-to-one correspondence relationship, a characteristic curve representing the correspondence relationship between each of the first input powers and the second input powers may be plotted with the first input power as an abscissa and the second input power as an ordinate. In view of the test requirement of the chip to be tested, the second input power required to be input into the chip to be tested is linear, so that the corresponding target first input power can be determined according to the determined target second input power and the drawn characteristic curve, namely the target first input power meeting the test requirement.
3. In the embodiment of the present invention, when the target second input power is not in the one-to-one correspondence relationship defined between the first input power and the second input power, the target first power corresponding to the current target second input power to be defined needs to be calculated by using the one-dimensional linear difference method. First, two nearest second input powers with the minimum absolute value of the difference value with the current target second input power are determined, first input powers corresponding to the two nearest second input powers can be determined according to the corresponding relation between the first input powers and the second input powers, the first input powers are substituted into the formula, and then the target first input power corresponding to the current target second input power to be determined can be obtained.
It should be noted that not all steps and modules in the above flows and system structure diagrams are necessary, and some steps or modules may be omitted according to actual needs. The execution order of the steps is not fixed and can be adjusted as required. The system structure described in the above embodiments may be a physical structure or a logical structure, that is, some modules may be implemented by the same physical entity, or some modules may be implemented by a plurality of physical entities, or some components in a plurality of independent devices may be implemented together.
In the above embodiments, the hardware unit may be implemented mechanically or electrically. For example, a hardware element may comprise permanently dedicated circuitry or logic (such as a dedicated processor, FPGA or ASIC) to perform the corresponding operations. The hardware elements may also comprise programmable logic or circuitry, such as a general purpose processor or other programmable processor, that may be temporarily configured by software to perform the corresponding operations. The specific implementation (mechanical, or dedicated permanent, or temporarily set) may be determined based on cost and time considerations.
While the invention has been shown and described in detail in the drawings and in the preferred embodiments, it is not intended to limit the invention to the embodiments disclosed, and it will be apparent to those skilled in the art that various combinations of the code auditing means in the various embodiments described above may be used to obtain further embodiments of the invention, which are also within the scope of the invention.
Claims (10)
1. A method of power calibration, comprising:
outputting at least two first input powers by a vector signal transceiver so that the vector signal transceiver transmits the at least two first input powers to a driver amplifier, wherein the at least two first input powers are the first input powers of at least two single-tone signals emitted by the vector signal transceiver;
acquiring second input power corresponding to each first input power, and generating a corresponding relation between the first input power and the second input power, wherein the power of the first input power, which is amplified by the driving amplifier and transmitted to the chip to be tested through the transmission line, is the second input power corresponding to the first input power;
determining at least two target second input powers according to a preset value, wherein after the at least two target second input powers are arranged according to the size, the difference value between any two adjacent target second input powers is the preset value;
and determining target first input power corresponding to each target second input power according to the corresponding relation between the first input power and the second input power.
2. The method of claim 1,
determining a target first input power corresponding to each target second input power according to the corresponding relationship between the first input power and the second input power, including:
establishing a rectangular coordinate system, wherein the abscissa is the first input power, and the ordinate is the second input power;
drawing a characteristic curve according to the corresponding relation between the first input power and the second input power;
and determining the target first input power corresponding to each target second input power from the characteristic curve.
3. The method of claim 2,
the determining, from the characteristic curve, a target first input power corresponding to each target second input power includes:
for each of the target second input powers, performing:
when the current target second input power is not in the correspondence,
determining two nearest second input powers with the minimum absolute value of the difference value with the current target second input power from the corresponding relation;
determining a first input power corresponding to each nearest second input power according to the corresponding relation;
determining the target first input power corresponding to the current target second input power according to the following formula:
wherein, y0And y1For two of said nearest second input powers, x0Is y0Corresponding first input power, x1Is y1And y is the current target second input power, and x is the target first input power corresponding to the current target second input power.
4. The method of claim 1,
determining a target first input power corresponding to each target second input power according to the corresponding relationship between the first input power and the second input power, including:
s1, putting each second input power in the corresponding relation into a preset set;
s2, determining the minimum second input power from the preset set, and taking the minimum second input power as an intermediate parameter;
s3: judging whether the sum of the intermediate parameter and the preset value is in the preset set, if so, executing S4, otherwise, executing S5;
s4: recording a second input power corresponding to the sum of the intermediate parameter and the preset value, taking the second input power corresponding to the sum of the intermediate parameter and the preset value as the intermediate parameter, and returning to the step S3;
s5: judging whether the intermediate parameter is the minimum value in the preset set, if so, executing S6, otherwise, executing S7;
s6: deleting the second input power corresponding to the intermediate parameter from the preset set, and returning to the step S2;
s7: performing S8 with the recorded second input power as the target second input power;
s8: and taking the first input power corresponding to each target second input power in the corresponding relation as the target first input power.
5. A power calibration device, comprising:
an input module, configured to output at least two first input powers by a vector signal transceiver, so that the vector signal transceiver transmits the at least two first input powers to a driver amplifier, where the at least two first input powers are the first input powers of at least two tone signals transmitted by the vector signal transceiver;
the processing module is configured to obtain a second input power corresponding to each first input power received by the input module, and generate a corresponding relationship between the first input power and the second input power, where the power that the first input power is amplified by the driver amplifier and transmitted to the chip to be tested through the transmission line is the second input power corresponding to the first input power;
a first determining module, configured to determine, according to a preset value, at least two target second input powers from the second input powers acquired by the processing module, where after the at least two target second input powers are arranged according to sizes, a difference between any two adjacent target second input powers is the preset value;
and a second determining module, configured to determine, according to a correspondence between the first input power and the second input power generated by the processing module, a target first input power corresponding to the target second input power determined by each of the first determining modules.
6. The power calibration device of claim 5,
the second determining module includes:
the establishing unit is used for establishing a rectangular coordinate system, wherein the abscissa is the first input power, and the ordinate is the second input power;
the drawing unit is used for drawing a characteristic curve according to the corresponding relation between the first input power and the second input power generated by the processing module;
and the determining unit is used for determining the target first input power corresponding to each target second input power from the characteristic curve drawn by the drawing unit.
7. The power calibration device of claim 6,
the second determining module is configured to, for each target second input power, perform:
when the current target second input power is not in the correspondence,
determining two nearest second input powers with the minimum absolute value of the difference value with the current target second input power from the corresponding relation;
determining a first input power corresponding to the second input power of each closest point according to the corresponding relation;
determining the target first input power corresponding to the current target second input power according to the following formula:
wherein, y0And y1For two of said nearest second input powers, x0Is y0Corresponding first input power, x1Is y1And y is the current target second input power, and x is the target first input power corresponding to the current target second input power.
8. The power calibration device of claim 5,
the second determining module is configured to perform:
s1, putting each second input power in the corresponding relation into a preset set;
s2, determining the minimum second input power from the preset set, and taking the minimum second input power as an intermediate parameter;
s3: judging whether the sum of the intermediate parameter and the preset value is in the preset set, if so, executing S4, otherwise, executing S5;
s4: recording a second input power corresponding to the sum of the intermediate parameter and the preset value, taking the second input power corresponding to the sum of the intermediate parameter and the preset value as the intermediate parameter, and returning to the step S3;
s5: judging whether the intermediate parameter is the minimum value in the preset set, if so, executing S6, otherwise, executing S7;
s6: deleting the second input power corresponding to the intermediate parameter from the preset set, and returning to S2;
s7: performing S8 with the recorded second input power as the target second input power;
s8: and taking the first input power corresponding to each target second input power in the corresponding relation as the target first input power.
9. A power calibration system, comprising: a vector signal transceiver, a driver amplifier and a power calibration device as claimed in any one of claims 5 to 8;
the vector signal transceiver is used for receiving at least two first input powers input by the power calibration device and sending the at least two first input powers to the driving amplifier;
the driving amplifier is used for amplifying the at least two first input powers sent by the vector signal transceiver, outputting the amplified powers, and transmitting the amplified powers to a chip to be tested through a transmission line.
10. A test system, comprising: a vector signal transceiver and a driver amplifier;
the vector signal transceiver is used for receiving at least two target first input powers input by external equipment and sending the at least two target first input powers to the driving amplifier;
the driving amplifier is used for amplifying the at least two target first input powers sent by the vector signal transceiver, outputting the amplified powers, and transmitting the amplified powers to a chip to be tested through a transmission line.
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