CN111220862A - Method for monitoring residual life of direct current capacitor of three-phase uncontrolled rectification alternating current-direct current-alternating current system - Google Patents

Abstract

The invention provides a method for monitoring the residual service life of a direct current capacitor of a three-phase uncontrolled rectification alternating current-direct current-alternating current system, which does not need to add a new sensor and does not influence the normal working state of the system. The method is characterized in that a discrete Fourier algorithm is adopted to extract voltage and current components with specified frequency aiming at sampled voltage and current signals, and an equivalent capacitance value and an equivalent resistance value are calculated by combining a capacitor first-order equivalent circuit. And deducing the residual life of the capacitor by using the equivalent capacitance value and the equivalent resistance value change trend during the life of the capacitor.

Description

Method for monitoring residual life of direct current capacitor of three-phase uncontrolled rectification alternating current-direct current-alternating current system

Technical Field

The invention relates to a method for monitoring the residual life of a direct current capacitor, in particular to a method for monitoring the residual life of a direct current capacitor of a three-phase uncontrolled rectification alternating current-direct current-alternating current system.

Background

An AC-DC-AC converter system adopting three-bridge-arm six-diode uncontrolled rectification as a front stage is widely applied in many occasions due to undisputed high performance, and as a capacitor with the highest failure rate in the system, health management and fault prediction attract more and more attention. The existing capacitor residual life monitoring technology mostly adopts an off-line implementation scheme, and a capacitor is detached from a system to measure under the condition that a converter system is shut down, or other measurement technologies are adopted to measure the parameters of the capacitor representing the residual life. For practical converter systems, most of application occasions such as motor drive, uninterruptible power supplies, photovoltaic systems and the like do not allow system components to be dismantled or shut down after the system is built, and therefore, many scholars put forward online measurement schemes. Conventional on-line measurement schemes require the addition of specially-made voltage-current sensors or other measurement elements, which may adversely affect stray parameters of the system while increasing cost. Also, some residual life monitoring systems require additional control strategies to bring the system out of normal operation.

Disclosure of Invention

Aiming at the defects in the prior art, the invention aims to provide a capacitance residual life monitoring scheme which is convenient to implement, does not need to be additionally provided with a special sensor (only a voltage and current sensor for control in a variable current system), does not need to change the state of the system and can be carried out at any time in real time. The monitoring scheme has strong anti-interference capability and can realize the residual life prediction capability with enough precision so as to meet the high requirement of a three-phase uncontrolled rectification AC-DC-AC converter system on the reliability of the capacitor.

In order to achieve the above purposes, the technical scheme adopted by the invention is as follows:

the utility model provides a PWM converter direct current supports electric capacity remaining life on-line monitoring system, adopts DSP + FPGA framework, includes: the system comprises a core board, a bottom board, an AD7656 sampling module, a W5300 communication module and an upper computer; the core board comprises a DSP system and an FPGA minimum system; the DSP system comprises: a DSP minimum system and a plug-in storage unit; the plug-in storage unit includes: the device comprises a FLASH chip and a RAM chip, the AD7656 sampling module comprises 3 AD7656 chips and a low-pass filter, the W5300 communication module comprises a WIZnet W5300 chip and an Ethernet transformer,

a data address bus, a PWM output signal line, a BOOT guide signal line and a general input/output signal line of the DSP chip are all connected with the FPGA chip; the EM1CS2 pin of the DSP chip is connected with the FLASH chip and is used for selecting the FLASH chip; the EM1CS3 pin of the DSP chip is connected with the RAM chip and is used for chip selection of the RAM chip; the EM1OE pin and the EM1WE pin of the DSP chip are respectively connected with the read pin and the write pin of the FLASH chip; the EM1OE pin and the EM1WE pin of the DSP chip are respectively connected with the read pin and the write pin of the RAM chip; a 19-bit address bus and a 16-bit data bus of the DSP chip are respectively connected with an address pin and a data pin of the FLASH chip; a 19-bit address bus and a 16-bit data bus of the DSP chip are respectively connected with an address pin and a data pin of the RAM chip;

the EM1CS4 pin of the DSP chip is connected with the pin CS of the WIZnet W5300 chip, the EM1OE pin and the EM1WE pin of the DSP chip are respectively connected with the read pin and the write pin of the WIZnet W5300 chip, the 8-bit address bus of the DSP chip is connected with the address line input pin of the WIZnet W5300 chip, and the 16-bit data bus of the DSP chip is connected with the data input pin of the WIZnet W5300 chip;

12 GPIO pins of the FPGA chip are respectively connected with a chip selection pin CS, a RESET signal pin RESET, a feedback signal pin BUSY and a start conversion signal pin CONVST of the 3 AD7656 chips, and data pins of the 3 AD7656 chips are all connected with a 16 data bus of the DSP chip; the 6-path sampling input pins of the AD7656 chip are connected with the output end of a low-pass filter, the input end of one low-pass filter is connected with a voltage sensor, and the input end of the other low-pass filter is connected with a current sensor;

the bottom plate is connected with the core board and provides a power supply for the control chip of the core board; the expansion interface of the core board comprises: the device comprises a multi-protocol serial communication interface, an ADC sampling input interface, a data address bus interface, a PWM output interface and a plurality of digital input and output interfaces.

On the basis of the scheme, the online monitoring system adopts an expandable connector design, and the expandable connector design allows a user to freely design the base plate aiming at the functions and the target functions of the core plate.

On the basis of the scheme, the DSP system adopts a window voltage detection chip to design an over-voltage and under-voltage protection circuit, and performs protection and reset operations on the DSP system; the DSP minimum system unit comprises a crystal oscillator circuit, a reset circuit, a power supply circuit, a boot mode setting circuit and a JTAG interface circuit; the model of the DSP chip is TMS320F28377 d; the DSP system also includes a plurality of data communication protocols including I²C, SCI, SPI, CAN, USB; the DSP system is provided with an ADC sampling module and is used for realizing 16-bit-precision differential input signal sampling and 12-bit-precision single-ended input signal sampling.

On the basis of the scheme, the FLASH chip adopts an SST39VF822 chip, and the RAM chip adopts an IS61LV25616AL-10TLI chip; the W5300 communication module is connected and communicated with an upper computer through an Ethernet transformer HR 911103A.

On the basis of the scheme, the communication interface of the upper computer comprises an oscilloscope part, a capacitor equivalent circuit, a capacitor service life and a capacitor state; the oscilloscope part comprises an oscilloscope control box, a waveform display frame and an oscilloscope setting part and is used for observing the waveform of the capacitor voltage and the capacitor current obtained by sampling; the capacitance equivalent circuit adopts a first-order series resistance-capacitance equivalent circuit, and different algorithms are selected to calculate the actual capacitance value.

On the basis of the scheme, the FPGA minimum system comprises a power supply circuit, a clock circuit, a JTAG circuit, a programming configuration circuit and an input/output circuit, wherein the power supply circuit is used for supplying power to an FPGA chip and an inner core and providing a reference level for the FPGA inner core; the clock circuit comprises a 50MHz clock signal input provided by an external active crystal oscillator circuit and a synchronous clock signal input output by the DSP chip; the JTAG circuit is used for burning programs and debugging chips on line; the programming configuration circuit adopts a four-way serial configuration chip EPCQ64, and the programming mode is selected to be an active serial mode and is used for solidifying a program circuit when the FPGA chip is electrified and started; the input-output circuit comprises digital input and output, and can be freely designed.

A three-phase uncontrolled rectification AC-DC-AC converter system DC capacitor remaining life monitoring method applies the online monitoring system and comprises the following steps:

s1, initializing a DSP chip and an FPGA chip;

s2, initializing an AD7656 chip and a W5300 chip;

s3, setting the interrupt frequency of the DSP system to be 25kHz, triggering sampling once when the DSP system is interrupted, and setting the sampling frequency to be 25 kHz;

s4, collecting voltage analog signals by a voltage sensor VT and collecting current analog signals by a current sensor CT1, processing the collected voltage and current analog signals by a low-pass filter, and transmitting the processed signals to an AD7656 chip, wherein the AD7656 chip converts the voltage and current analog signals into 16-bit-precision voltage and current digital signals;

s5, sampling: the DSP chip sends a sampling instruction to the FPGA chip, the FPGA chip controls the AD7656 chip to sample, the AD7656 chip transmits voltage and current digital signals to the FPGA chip, and the FPGA chip transmits the voltage and current digital signals to the DSP chip through a bus;

s6, after the DSP chip receives the voltage and current digital signals:

adopting a discrete Fourier algorithm, selecting the fundamental frequency as 100Hz, and solving 3 harmonics: the amplitude and the phase angle of the harmonic component of the voltage and the current at 300Hz are solved according to the formula (1), the equivalent modulus value and the equivalent phase angle of the first-order equivalent resistance-capacitance circuit are solved according to the formula (2), the equivalent capacitance value C and the equivalent resistance value ESR of the first-order equivalent resistance-capacitance circuit are solved according to the formula (2), and the solved equivalent capacitance value and the solved equivalent resistance value are transmitted to an upper computer through a WIZnet W5300 chip and an Ethernet transformer;

or the voltage and current digital signals are transmitted to an upper computer through a WIZnet W5300 chip and an Ethernet transformer, MATLAB software in the upper computer respectively carries out band-pass filtering on the voltage and current digital signals by adopting an equal ripple FIR band-pass filter, the band-pass frequency is set to be 300Hz, the pass-band width is 10Hz, the order is 395, and the 300Hz capacitance voltage and current waveforms are obtained through filtering; calculating an equivalent modulus value and an equivalent phase angle of the first-order equivalent resistance-capacitance circuit according to the obtained 300Hz capacitor voltage and current waveforms, and then calculating an equivalent capacitance value C and an equivalent resistance value ESR of the first-order equivalent resistance-capacitance circuit according to a formula (2);

or the voltage and current digital signals are transmitted to an upper computer through a WIZnet W5300 chip and an Ethernet transformer, MATLAB software in the upper computer respectively carries out band-pass filtering on the voltage and current digital signals by adopting a Butterworth IIR band-pass filter, the band-pass frequency is 295-300 Hz, the order is 4, and the 300Hz capacitance voltage and current waveforms are obtained through filtering; calculating an equivalent modulus value and an equivalent phase angle of the first-order equivalent resistance-capacitance circuit according to the obtained 300Hz capacitor voltage and current waveforms, and then calculating an equivalent capacitance value C and an equivalent resistance value ESR of the first-order equivalent resistance-capacitance circuit according to a formula (2);

in the formula (1, | U₃₀₀|、∠U₃₀₀Respectively representing the amplitude and phase angle, | I, of the harmonic component of the voltage at 300Hz₃₀₀|、∠I₃₀₀respectively representing the amplitude and phase angle of the harmonic component of 300Hz current, | Z | representing the equivalent module value of the first-order equivalent RC circuit, ∠ Z representing the first-order equivalent RC circuitThe equivalent phase angle of (a) is,

and S7, judging the current capacitance state and the residual life according to the equivalent capacitance value and the equivalent resistance value of the first-order equivalent resistance-capacitance circuit and the initial capacitance value and the initial resistance value input by the user.

Drawings

The invention has the following drawings:

FIG. 1 is a circuit topology diagram of a three-phase uncontrolled rectification AC-DC-AC converter system.

FIG. 2 is a block diagram of a system for online monitoring of the residual life of a DC support capacitor of a PWM converter.

Fig. 3 is a software schematic diagram of the capacitor remaining life online monitoring system.

Detailed Description

The present invention is described in further detail below with reference to figures 1-3.

The scheme for calculating the residual life of the capacitor on line is suitable for the circuit topology shown in figure 1, and the circuit topology has the following characteristics:

(1) the rectifying side consists of six diodes with three bridge arms;

(2) the direct current side is provided with a supporting capacitor which is shown in the form of a first-order resistance-capacitance equivalent circuit, and the capacitor is a monitored object of the monitoring system;

(3) the inverter side forms a three-phase alternating current system by six IGBTs of a three-bridge arm or forms a single-phase alternating current system by four IGBTs of a double-bridge arm;

(4) the load is a three-phase symmetrical load or a single-phase load;

(5) CT1 and VT are a dc-side current sensor and a voltage sensor, respectively, and CT2, CT3, and CT4 are ac-side current sensors. The solid line frame sensor is used for the monitoring system, and the dotted line frame sensor is not used for the monitoring system.

Based on the above circuit topology, there are the following theoretical facts:

(1) for an uncontrolled rectifying circuit with six diodes of a three-phase three-bridge arm, under the condition that the amplitudes of three-phase input power supplies are equal and the phase angles are different by 120 degrees, the direct current side of the uncontrolled rectifying circuit presents the basic characteristic of six pulses, namely, the harmonic wave with the maximum amplitude is a 300Hz alternating current component which is six times of a 50Hz fundamental frequency except a direct current component in direct current voltage;

(2) for a three-phase inverter circuit with six three-phase three-bridge-arm IGBTs, under the condition that three-phase loads are symmetrical and no input source exists, an alternating current component of 300Hz is hardly generated in direct-current side current;

(3) according to the two theoretical bases, the 300Hz alternating current component generated by the voltage fluctuation with the frequency of 300Hz on the direct current side almost flows through the capacitor;

(4) therefore, the 300Hz AC voltage and current components measured by the voltage sensor and the current sensor installed on the DC side of the circuit can be approximated to the 300Hz voltage component across the capacitor and the 300Hz current component flowing through the capacitor.

The scheme for online calculating the residual life of the capacitor provided by the invention adopts an online monitoring hardware system shown in FIG. 2. The hardware system consists of a DSP + FPGA double-digital processing chip, an Ethernet template based on a WIZnet W5300 chip and a sampling module based on an AD7656 chip are configured, and other expansion functions such as serial passing of the DSP chip are reserved. The hardware system takes a DSP chip as a main control chip, realizes parallel communication of data among different chips through the EMIF function of the DSP, and has the functions of high-precision sampling and high-speed communication.

Based on the hardware system, the method comprises the following operation steps:

1. installing a sensor at a designated position of the system; generally, a three-phase uncontrolled rectifying ac-dc-ac converter system has a voltage sensor installed on a dc side to detect voltage fluctuation on the dc side, and a current sensor installed to calculate output power of an inverter system. Therefore, the voltage and current sensors required by an online monitoring system are usually included in the converter system, and step 1 can be omitted.

2. Configuring a DSP + FPGA hardware system: (1) initializing a DSP chip and an FPGA chip; (2) initializing AD7656 and W5300 chips; (3) the DSP system interrupt frequency is set to 25kHz and one sample is triggered in each interrupt routine so that the sample rate is also 25 kHz. In the sampling process, a DSP chip sends a sampling instruction to the FPGA, the FPGA controls the AD7656 to finish signal sampling once, and data are returned to the DSP system.

3. Based on the DSP + FPGA hardware system which is configured, the DSP is used as a main control chip, voltage and current analog signals are collected through a sensor, the voltage and current analog signals are converted into digital quantity in an AD7656 chip after passing through a low-pass filter and then are transmitted to an FPGA (field programmable gate array) chip, the FPGA transmits the data to a DSP (digital signal processing) chip through a bus, and the DSP obtains a voltage and current digital quantity signal with 16-bit precision;

4. after the DSP chip collects the voltage and current digital signals, three schemes shown in figure 3 can be selected:

scheme 1: and finishing data processing inside the DSP: selecting a fundamental wave frequency as 100Hz by adopting a discrete Fourier algorithm, solving the amplitude and the phase angle of a voltage and current harmonic component of 3-order harmonic waves, namely 300Hz, solving an equivalent modulus value and an equivalent phase angle of a first-order equivalent resistance-capacitance circuit according to a formula (1), solving an equivalent capacitance value and an equivalent resistance value of the first-order equivalent resistance-capacitance circuit according to a formula (2), and transmitting the solved data to an upper computer through an Ethernet template based on a WIZnet W5300 chip;

scheme 2: data processing in MATLAB: and transmitting the acquired voltage and current data to an upper computer through an Ethernet template based on a WIZnetW5300 chip, and installing MATLAB software in the upper computer to respectively perform band-pass filtering on the voltage and current signals. Selecting an equal-ripple FIR band-pass filter, setting the band-pass frequency to be 300Hz, the pass band width to be 100Hz and the order to be 395, and filtering to obtain 300Hz capacitor voltage and current waveforms; calculating an equivalent modulus value and an equivalent phase angle of the first-order equivalent resistance-capacitance circuit according to the obtained 300Hz capacitor voltage and current waveforms, and then calculating an equivalent capacitance value and an equivalent resistance value of the first-order equivalent resistance-capacitance circuit according to a formula (2);

scheme 3: data processing in MATLAB: and transmitting the acquired voltage and current data to an upper computer through an Ethernet template based on a WIZnetW5300 chip, and installing MATLAB software in the upper computer to respectively perform band-pass filtering on the voltage and current signals. Selecting a Butterworth IIR band-pass filter, wherein the frequency of a pass band is 295-300 Hz, the order is 4, and filtering is carried out to obtain 300Hz capacitance voltage and current waveforms; calculating an equivalent modulus value and an equivalent phase angle of the first-order equivalent resistance-capacitance circuit according to the obtained 300Hz capacitor voltage and current waveforms, and then calculating an equivalent capacitance value and an equivalent resistance value of the first-order equivalent resistance-capacitance circuit according to a formula (2);

5. according to the three schemes, the actual capacitance value and the equivalent resistance value of the capacitor can be calculated, and the current capacitance state and the residual life can be judged according to the initial capacitance value and the initial resistance value input by a user.

In the formula (1, | U₃₀₀|、∠U₃₀₀Respectively representing the amplitude and phase angle, | I, of the harmonic component of the voltage at 300Hz₃₀₀|、∠I₃₀₀Respectively representing the magnitude and phase angle of the harmonic component of the 300Hz current,

those not described in detail in this specification are within the skill of the art.

Claims (7)

1. The utility model provides a PWM converter direct current supports electric capacity remaining life on-line monitoring system which characterized in that adopts DSP + FPGA framework, includes: the system comprises a core board, a bottom board, an AD7656 sampling module, a W5300 communication module and an upper computer; the core board comprises a DSP system and an FPGA minimum system; the DSP system comprises: a DSP minimum system and a plug-in storage unit; the plug-in storage unit includes: the device comprises a FLASH chip and a RAM chip, the AD7656 sampling module comprises 3 AD7656 chips and a low-pass filter, the W5300 communication module comprises a WIZnet W5300 chip and an Ethernet transformer,

a data address bus, a PWM output signal line, a BOOT guide signal line and a general input/output signal line of the DSP chip are all connected with the FPGA chip; the EM1CS2 pin of the DSP chip is connected with the FLASH chip and is used for selecting the FLASH chip; the EM1CS3 pin of the DSP chip is connected with the RAM chip and is used for chip selection of the RAM chip; the EM1OE pin and the EM1WE pin of the DSP chip are respectively connected with the read pin and the write pin of the FLASH chip; the EM1OE pin and the EM1WE pin of the DSP chip are respectively connected with the read pin and the write pin of the RAM chip; a 19-bit address bus and a 16-bit data bus of the DSP chip are respectively connected with an address pin and a data pin of the FLASH chip; a 19-bit address bus and a 16-bit data bus of the DSP chip are respectively connected with an address pin and a data pin of the RAM chip;

the EM1CS4 pin of the DSP chip is connected with the pin CS of the WIZnet W5300 chip, the EM1OE pin and the EM1WE pin of the DSP chip are respectively connected with the read pin and the write pin of the WIZnet W5300 chip, the 8-bit address bus of the DSP chip is connected with the address line input pin of the WIZnet W5300 chip, and the 16-bit data bus of the DSP chip is connected with the data input pin of the WIZnet W5300 chip;

12 GPIO pins of the FPGA chip are respectively connected with a chip selection pin CS, a RESET signal pin RESET, a feedback signal pin BUSY and a start conversion signal pin CONVST of the 3 AD7656 chips, and data pins of the 3 AD7656 chips are all connected with a 16 data bus of the DSP chip; the 6-path sampling input pins of the AD7656 chip are connected with the output end of a low-pass filter, the input end of one low-pass filter is connected with a voltage sensor, and the input end of the other low-pass filter is connected with a current sensor;

the bottom plate is connected with the core board and provides a power supply for the control chip of the core board; the expansion interface of the core board comprises: the device comprises a multi-protocol serial communication interface, an ADC sampling input interface, a data address bus interface, a PWM output interface and a plurality of digital input and output interfaces.

2. The PWM converter dc support capacitor remaining life on-line monitoring system according to claim 1, wherein said on-line monitoring system employs an expandable connector design that allows a user to freely design a backplane for core board functions and target functions.

3. The PWM converter DC support capacitor remaining life on-line monitoring system of claim 1, wherein the DSP system adoptsCarrying out over-voltage and under-voltage protection circuit design by using a window voltage detection chip, and carrying out protection and reset operation on a DSP system; the DSP minimum system unit comprises a crystal oscillator circuit, a reset circuit, a power supply circuit, a boot mode setting circuit and a JTAG interface circuit; the model of the DSP chip is TMS320F28377 d; the DSP system also includes a plurality of data communication protocols including I²C, SCI, SPI, CAN, USB; the DSP system is provided with an ADC sampling module and is used for realizing 16-bit-precision differential input signal sampling and 12-bit-precision single-ended input signal sampling.

4. The PWM converter direct-current support capacitor residual life online monitoring system of claim 1, wherein the FLASH chip adopts SST39VF822 chip, and the RAM chip adopts IS61LV25616AL-10TLI chip; the W5300 communication module is connected and communicated with an upper computer through an Ethernet transformer HR 911103A.

5. The PWM converter direct current support capacitor residual life online monitoring system of claim 1, wherein the communication interface of the upper computer comprises an oscilloscope part, a capacitor equivalent circuit, a capacitor life and a capacitor state; the oscilloscope part comprises an oscilloscope control box, a waveform display frame and an oscilloscope setting part and is used for observing the waveform of the capacitor voltage and the capacitor current obtained by sampling; the capacitance equivalent circuit adopts a first-order series resistance-capacitance equivalent circuit, and different algorithms are selected to calculate the actual capacitance value.

6. The PWM converter direct current support capacitor residual life online monitoring system of claim 1, wherein the FPGA minimum system comprises a power supply circuit, a clock circuit, a JTAG circuit, a programming configuration circuit and an input-output circuit, wherein the power supply circuit is used for supplying power to an FPGA chip and a kernel and providing a reference level for the FPGA kernel; the clock circuit comprises a 50MHz clock signal input provided by an external active crystal oscillator circuit and a synchronous clock signal input output by the DSP chip; the JTAG circuit is used for burning programs and debugging chips on line; the programming configuration circuit adopts a four-way serial configuration chip EPCQ64, and the programming mode is selected to be an active serial mode and is used for solidifying a program circuit when the FPGA chip is electrified and started; the input/output circuit includes digital input and output, and can be freely designed.

7. A method for monitoring the residual life of a direct current capacitor of a three-phase uncontrolled rectification alternating current-direct current-alternating current system applies the PWM converter direct current support capacitor on-line monitoring system of any one of claims 1 to 6, and is characterized by comprising the following steps:

s1, initializing a DSP chip and an FPGA chip;

s2, initializing an AD7656 chip and a W5300 chip;

s3, setting the interrupt frequency of the DSP system to be 25kHz, triggering sampling once when the DSP system is interrupted, and setting the sampling frequency to be 25 kHz;

s4, collecting voltage analog signals by a voltage sensor VT and collecting current analog signals by a current sensor CT1, processing the collected voltage and current analog signals by a low-pass filter, and transmitting the processed signals to an AD7656 chip, wherein the AD7656 chip converts the voltage and current analog signals into 16-bit-precision voltage and current digital signals;

s5, sampling: the DSP chip sends a sampling instruction to the FPGA chip, the FPGA chip controls the AD7656 chip to sample, the AD7656 chip transmits voltage and current digital signals to the FPGA chip, and the FPGA chip transmits the voltage and current digital signals to the DSP chip through a bus;

s6, after the DSP chip receives the voltage and current digital signals:

adopting a discrete Fourier algorithm, selecting the fundamental frequency as 100Hz, and solving 3 harmonics: the amplitude and the phase angle of the harmonic component of the voltage and the current at 300Hz are solved according to the formula (1), the equivalent modulus value and the equivalent phase angle of the first-order equivalent resistance-capacitance circuit are solved according to the formula (2), the equivalent capacitance value C and the equivalent resistance value ESR of the first-order equivalent resistance-capacitance circuit are solved according to the formula (2), and the solved equivalent capacitance value and the solved equivalent resistance value are transmitted to an upper computer through a WIZnet W5300 chip and an Ethernet transformer;

or the voltage and current digital signals are transmitted to an upper computer through a WIZnet W5300 chip and an Ethernet transformer, MATLAB software in the upper computer respectively carries out band-pass filtering on the voltage and current digital signals by adopting an equal ripple FIR band-pass filter, the band-pass frequency is set to be 300Hz, the pass-band width is 10Hz, the order is 395, and the 300Hz capacitance voltage and current waveforms are obtained through filtering; calculating an equivalent modulus value and an equivalent phase angle of the first-order equivalent resistance-capacitance circuit according to the obtained 300Hz capacitor voltage and current waveforms, and then calculating an equivalent capacitance value C and an equivalent resistance value ESR of the first-order equivalent resistance-capacitance circuit according to a formula (2);

or the voltage and current digital signals are transmitted to an upper computer through a WIZnet W5300 chip and an Ethernet transformer, MATLAB software in the upper computer respectively carries out band-pass filtering on the voltage and current digital signals by adopting a Butterworth IIR band-pass filter, the band-pass frequency is 295-300 Hz, the order is 4, and the 300Hz capacitance voltage and current waveforms are obtained through filtering; calculating an equivalent modulus value and an equivalent phase angle of the first-order equivalent resistance-capacitance circuit according to the obtained 300Hz capacitor voltage and current waveforms, and then calculating an equivalent capacitance value C and an equivalent resistance value ESR of the first-order equivalent resistance-capacitance circuit according to a formula (2);

in the formula (1, | U₃₀₀|、∠U₃₀₀Respectively representing the amplitude and phase angle, | I, of the harmonic component of the voltage at 300Hz₃₀₀|、∠I₃₀₀respectively representing the amplitude and phase angle of the harmonic component of the 300Hz current, ∠ Z ∠ representing the equivalent module value of the first-order equivalent RC circuit, ∠ Z representing the equivalent phase angle of the first-order equivalent RC circuit,

and S7, judging the current capacitance state and the residual life according to the equivalent capacitance value and the equivalent resistance value of the first-order equivalent resistance-capacitance circuit and the initial capacitance value and the initial resistance value input by the user.

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