CN111211750B - Automatic gain control circuit and method for controlling gain adjustment speed in AGC system - Google Patents
Automatic gain control circuit and method for controlling gain adjustment speed in AGC system Download PDFInfo
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Abstract
The invention discloses an automatic gain control circuit and a method for controlling gain adjustment speed in an AGC system, wherein the automatic gain control circuit comprises: the operational amplifier output monitoring module comprises a first comparator and a second comparator, and the clock signal transmitter is used for receiving a clock signal output by the oscillator and outputting a control signal to the forward counter and the backward counter according to output results of the first comparator and the second comparator; the forward counter and the backward counter are used for generating a gain amplitude adjusting signal according to the control signal and sending the gain amplitude adjusting signal to the decoder; the decoder controls the size of the feedback resistor of the front-stage operational amplifier according to the gain amplitude adjusting signal. The invention determines the speed of adjusting gain in the AGC system according to the time that the output waveform of the operational amplifier exceeds the detection threshold.
Description
Technical Field
The invention relates to an automatic gain control circuit and a method for controlling gain adjustment speed in an AGC system.
Background
The automatic gain control function is already adopted by most audio power amplifiers at present. The AGC system (automatic gain control system (automatic gain control, AGC)) detects that the input signal exceeds the rated threshold voltage, and the AGC system actively reduces the gain of the operational amplifier; when the input signal is reduced and is lower than the set release threshold, the AGC system actively recovers the operational amplifier gain, and the output signal power is ensured to be maintained near the rated value.
In the prior art, the method for reducing the gain has the defects that the gain adjustment mode is too hard, the adjustment speed is consistent and is not soft by detecting the peak voltage of the output of the operational amplifier and then adjusting the feedback resistance of the operational amplifier. The listening effect of music files is directly affected in the field of audio applications.
Disclosure of Invention
The invention aims to overcome the defects that in the prior art, a gain adjusting mode is single, adjusting speed cannot be changed and music listening effect can be influenced when the gain adjusting mode acts on audio equipment, and provides an automatic gain control circuit and a method for controlling the gain adjusting speed in an AGC system.
The invention solves the technical problems by the following technical proposal:
an automatic gain control circuit, comprising: the device comprises a front-stage operational amplifier, an operational amplifier output monitoring module, a forward counter, a backward counter, a decoder, an oscillator and a clock signal transmitter, wherein,
the output of the front-stage operational amplifier is connected with the input of the front-stage operational amplifier through a feedback resistor, the input of the front-stage operational amplifier is connected with the input resistor, and the output of the front-stage operational amplifier is connected with the operational amplifier output monitoring module;
the operational amplifier output monitoring module comprises a first comparator and a second comparator, wherein the positive input end of the first comparator is connected with the front-stage operational amplifier output, the negative input end of the first comparator receives a first detection threshold value, and the output end of the first comparator is connected with the clock signal transmitter; the positive input end of the second comparator is connected with the output of the front-stage operational amplifier, the negative input end of the second comparator receives a second detection threshold value, and the output end of the second comparator is connected with the clock signal transmitter;
the clock signal transmitter is used for receiving the clock signal output by the oscillator and outputting a control signal to the forward counter and the reverse counter according to the output results of the first comparator and the second comparator;
the forward counter and the reverse counter are used for receiving the control signal output by the clock signal transmitter, generating a gain amplitude adjusting signal according to the control signal and transmitting the gain amplitude adjusting signal to the decoder;
the input end of the decoder receives the gain amplitude regulating signal output by the forward counter and the backward counter, the output end of the decoder is connected with the feedback resistor of the front-stage operational amplifier, and the magnitude of the feedback resistor of the front-stage operational amplifier is controlled according to the gain amplitude regulating signal.
Preferably, the first comparator and the second comparator compare the op-amp output signal with a first detection threshold and a second detection threshold respectively,
if the operational amplifier output signal is between the first detection threshold value and the second detection threshold value, the clock signal transmitter cuts off the square wave signal of the oscillator, so that the forward counter and the reverse counter cannot count, and the gain of the front-stage operational amplifier keeps the current state unchanged;
if the operational amplifier output signal is higher than the first detection threshold, the clock signal transmitter transmits an oscillator square wave signal to the forward counter and the backward counter to count forward, and generates a gain amplitude adjusting signal for reducing the gain of the front-stage operational amplifier;
if the operational amplifier output signal is lower than the second detection threshold, the clock signal transmitter transmits the oscillator square wave signal to the forward counter and the backward counter is made to count reversely, and a gain amplitude adjusting signal for increasing the gain of the preceding operational amplifier is generated.
Preferably, the first comparator and the second comparator are both voltage comparators.
Preferably, the first detection threshold is:
wherein Pout is output power, vin is input signal voltage, AV1 is front-stage operational amplifier gain, AV2 is integrator gain, R L Is the load resistance.
Preferably, the gain amplitude adjusting signal output by the forward and reverse counter is a five-bit digital signal, and the gain amplitude adjusting signal comprises the step number required for adjusting the feedback resistance of the front-stage operational amplifier.
Preferably, the decoder is used for generating a 31-bit digital code, acting on an on-off transmission gate of a feedback resistor between the output and the input of the front-stage operational amplifier, and adjusting the magnitude of the feedback resistor by controlling the switch of the transmission gate.
The invention also provides a method for controlling gain adjusting speed in an AGC system, which is characterized in that the method is realized by adopting the automatic gain control circuit, and comprises the following steps:
the first comparator and the second comparator compare the op amp output signal with a first detection threshold and a second detection threshold respectively,
if the operational amplifier output signal is between the first detection threshold value and the second detection threshold value, the clock signal transmitter cuts off the square wave signal of the oscillator, so that the forward counter and the reverse counter cannot count, the gain of the front-stage operational amplifier keeps the current state unchanged, and the resistance value of the feedback resistor is not changed;
if the operational amplifier output signal is higher than the first detection threshold, the clock signal transmitter transmits an oscillator square wave signal to the forward counter and the backward counter to count forward, and generates a gain amplitude adjusting signal for reducing the gain of the front operational amplifier, and the decoder reduces the resistance of the feedback resistor;
if the operational amplifier output signal is lower than the second detection threshold, the clock signal transmitter transmits the oscillator square wave signal to the forward counter and the backward counter to count reversely, and generates a gain amplitude adjusting signal for increasing the gain of the preceding operational amplifier, and the decoder increases the resistance of the feedback resistor.
In particular, the forward counter counts forward, the output of the operational amplifier is reduced, the time exceeding the first detection threshold value in one signal period is gradually shortened, and the square wave signal received by the forward counter is reduced. Accordingly, more signal cycles are required to adjust the same gain, so the early adjustment speed is high and the later adjustment speed is low. The gain adjustment is gradually slowed down and the waveform is softer.
On the basis of conforming to the common knowledge in the field, the above preferred conditions can be arbitrarily combined to obtain the preferred examples of the invention.
The invention has the positive progress effects that: and determining the step number of gain adjustment of the operational amplifier by detecting that the operational amplifier output exceeds the comparison threshold time, thereby controlling the speed of the gain adjustment. When the output signal of the early operational amplifier is larger, the gain adjustment steps in each signal period are more, and the speed is high; the output signal of the later operational amplifier is reduced, the step number of gain adjustment in each signal period is correspondingly reduced, and the speed is slowed down. Therefore, the speed of the gain adjustment of the operational amplifier is firstly fast and then slow.
The operational amplifier gain is regulated fast and then slow, and the operational amplifier gain tends to be soft. In the field of audio application, the phenomenon that the playing of music files suddenly rises and falls is avoided, and the playing effect is improved.
Drawings
Fig. 1 is a schematic diagram of an automatic gain control circuit according to an embodiment of the invention.
Fig. 2 is a schematic diagram of comparison between an operational amplifier output waveform and a detection threshold and comparison between the operational amplifier output waveform and the operational amplifier output waveform before and after adjustment.
Fig. 3 is a schematic diagram of an output waveform after automatic gain adjustment.
Detailed Description
The invention is further illustrated by means of the following examples, which are not intended to limit the scope of the invention.
Referring to fig. 1, the automatic gain control circuit according to the present embodiment includes: the front-stage operational amplifier 1, an operational amplifier output monitoring module, a forward counter 5, a decoder 6, an oscillator 3 and a clock signal transmitter 4, wherein,
a feedback resistor R is connected between the output of the front-stage operational amplifier and the input of the front-stage operational amplifier FB The input of the front-stage operational amplifier is connected with an input resistor R IN The front-stage operational amplifier output is connected with an operational amplifier output monitoring module;
the operational amplifier output monitoring module comprises a first comparator 21 and a second comparator 22, wherein the positive input end of the first comparator 21 is connected with the front-stage operational amplifier output, the negative input end of the first comparator 21 receives a first detection threshold value, and the output end of the first comparator 21 is connected with the clock signal transmitter 4; the positive input end of the second comparator 22 is connected with the output of the front-stage operational amplifier, the negative input end of the second comparator 22 receives a second detection threshold value, and the output end of the second comparator 22 is connected with the clock signal transmitter 4;
the clock signal transmitter 4 is configured to receive the clock signal output by the oscillator 3, and output a control signal to the forward/reverse counter 5 according to the output results of the first comparator 21 and the second comparator 22;
the forward counter 5 is used for receiving the control signal output by the clock signal transmitter, generating a gain amplitude adjusting signal according to the control signal and transmitting the gain amplitude adjusting signal to the decoder 6;
the input end of the decoder 6 receives the gain amplitude regulating signal output by the forward counter 5, and the output end of the decoder 6 is connected with the feedback resistor R of the front-stage operational amplifier FB And control the feedback circuit of the front-stage operational amplifier according to the gain amplitude adjusting signalR resistance FB Is of a size of (a) and (b).
Specifically the first comparator and the second comparator compare the op amp output signal with a first detection threshold and a second detection threshold respectively,
if the operational amplifier output signal is between the first detection threshold value and the second detection threshold value, the clock signal transmitter cuts off the square wave signal of the oscillator, so that the forward counter and the reverse counter cannot count, and the gain of the front-stage operational amplifier keeps the current state unchanged;
if the operational amplifier output signal is higher than the first detection threshold, the clock signal transmitter transmits an oscillator square wave signal to the forward counter and the backward counter to count forward, and generates a gain amplitude adjusting signal for reducing the gain of the front-stage operational amplifier;
if the operational amplifier output signal is lower than the second detection threshold, the clock signal transmitter transmits the oscillator square wave signal to the forward counter and the backward counter is made to count reversely, and a gain amplitude adjusting signal for increasing the gain of the preceding operational amplifier is generated.
In this embodiment, the first comparator and the second comparator are both voltage comparators.
The first detection threshold is:
wherein Pout is output power, vin is input signal voltage, AV1 is front-stage operational amplifier gain, AV2 is integrator gain, R L Is the load resistance. The second detection threshold is equal to the first detection threshold minus 100mV.
The gain amplitude adjusting signal output by the forward counter and the backward counter is a five-bit digital signal, and the gain amplitude adjusting signal comprises the step number which needs to be adjusted to the feedback resistor of the front-stage operational amplifier. The decoder is used for generating a 31-bit digital code, acting on an on-off transmission gate of a feedback resistor between the output and the input of the front-stage operational amplifier, and adjusting the size of the feedback resistor by controlling the switch of the transmission gate.
The method for controlling the gain adjustment speed in the AGC system is realized by adopting the automatic gain control circuit, and comprises the following steps:
the first comparator and the second comparator compare the op amp output signal with a first detection threshold and a second detection threshold respectively,
if the operational amplifier output signal is between the first detection threshold value and the second detection threshold value, the clock signal transmitter cuts off the square wave signal of the oscillator, so that the forward counter and the reverse counter cannot count, the gain of the front-stage operational amplifier keeps the current state unchanged, and the resistance value of the feedback resistor is not changed;
if the operational amplifier output signal is higher than the first detection threshold, the clock signal transmitter transmits an oscillator square wave signal to the forward counter and the backward counter to count forward, and generates a gain amplitude adjusting signal for reducing the gain of the front operational amplifier, and the decoder reduces the resistance of the feedback resistor;
if the operational amplifier output signal is lower than the second detection threshold, the clock signal transmitter transmits the oscillator square wave signal to the forward counter and the backward counter to count reversely, and generates a gain amplitude adjusting signal for increasing the gain of the preceding operational amplifier, and the decoder increases the resistance of the feedback resistor.
The relation between the gain adjustment speed and time of the invention is explained in a formula deduction way by taking sin wave as a front-stage operational amplifier input signal in combination with fig. 2 and 3, and the technical scheme of the invention is further explained in detail.
The sin wave is used as an input signal of the front-stage operational amplifier. Setting: the input signal of the operational amplifier is VIN
V IN ＝A sin(2πft)。
The operational amplifier amplifies the input sin wave, and the operational amplifier gain is AV1
The instantaneous value of the operational amplifier output is V
Therefore, the CLASS D op-amp (CLASS D op-amp) outputs a peak voltage:
the first comparator and the second comparator compare the output of the operational amplifier with the first detection threshold and the second detection threshold in real time. When the instantaneous value of the operational amplifier output exceeds the first detection threshold, the clock signal transmitter allows the oscillator output signal to be transmitted to a forward-reverse counter (hereinafter referred to as counter), and the counter starts to count forward.
The output of the counter is a five-bit digital signal containing the number of steps that need to be adjusted for the feedback resistance of the preceding op-amp. The counter outputs to the decoder, the decoder generates a 31-bit digital code, the 31-bit digital code acts on the on-off transmission gate of the feedback resistor between the output and the input of the front-stage operational amplifier, and the resistance value of the feedback resistor is gradually reduced by controlling the switch of the transmission gate, so that the purpose of reducing the operational amplifier gain is achieved.
As shown in fig. 2, the first detection threshold is calculated from the output constant power target value:
for a given P out 、R L AV2, a first detection threshold is:
setting: the output of the pre-stage operational amplifier before adjustment is equal to the first detection threshold moment tx.
There is a first detection threshold:
the second detection threshold is equal to the first detection threshold minus 100mV.
The automatic gain control system adjusts the operational amplifier feedback resistor so that the peak value of the operational amplifier output waveform is between the first detection threshold value and the second detection threshold value. Since the two differ by 100mV, they are approximately equal. Therefore, the operational amplifier output peak value takes the first detection threshold value for the convenience of calculation.
So that:
so the time when the op-amp output is above the first detection threshold is:
namely:
AGC adjusts CLASS D operational amplifier feedback resistor R FB Is fixed, set:
the clock signal is TCLK1, and the number of steps of which the operational amplifier feedback resistor is adjusted in one sin wave period is:
since the arcsine function is a monotonically increasing function, the current-stage operational amplifier feedback resistor R FB When gradually decreasing, the time "t" is decreased beyond the first detection threshold. Thus, the feedback resistance adjustment times "X" gradually decrease in each sin wave period. The number of cycles required for the gain to drop by the same value increases gradually. So, as shown in fig. 3, the operational amplifier output waveform shows a phenomenon that the adjusting speed is slower and slower for the input signal with a fixed period.
While specific embodiments of the invention have been described above, it will be appreciated by those skilled in the art that these are by way of example only, and the scope of the invention is defined by the appended claims. Various changes and modifications to these embodiments may be made by those skilled in the art without departing from the principles and spirit of the invention, but such changes and modifications fall within the scope of the invention.
Claims (6)
1. An automatic gain control circuit, comprising: the device comprises a front-stage operational amplifier, an operational amplifier output monitoring module, a forward counter, a backward counter, a decoder, an oscillator and a clock signal transmitter, wherein,
the output of the front-stage operational amplifier is connected with the input of the front-stage operational amplifier through a feedback resistor, the input of the front-stage operational amplifier is connected with the input resistor, and the output of the front-stage operational amplifier is connected with the operational amplifier output monitoring module;
the operational amplifier output monitoring module comprises a first comparator and a second comparator, wherein the positive input end of the first comparator is connected with the front-stage operational amplifier output, the negative input end of the first comparator receives a first detection threshold value, and the output end of the first comparator is connected with the clock signal transmitter; the positive input end of the second comparator is connected with the output of the front-stage operational amplifier, the negative input end of the second comparator receives a second detection threshold value, and the output end of the second comparator is connected with the clock signal transmitter;
the clock signal transmitter is used for receiving the clock signal output by the oscillator and outputting a control signal to the forward counter and the reverse counter according to the output results of the first comparator and the second comparator;
the forward counter and the reverse counter are used for receiving the control signal output by the clock signal transmitter, generating a gain amplitude adjusting signal according to the control signal and transmitting the gain amplitude adjusting signal to the decoder;
the input end of the decoder receives the gain amplitude adjusting signal output by the forward counter and the backward counter, the output end of the decoder is connected with the feedback resistor of the front-stage operational amplifier, and the magnitude of the feedback resistor of the front-stage operational amplifier is controlled according to the gain amplitude adjusting signal;
the first comparator and the second comparator compare the op amp output signal with a first detection threshold and a second detection threshold respectively,
if the operational amplifier output signal is between the first detection threshold value and the second detection threshold value, the clock signal transmitter cuts off the square wave signal of the oscillator, so that the forward counter and the reverse counter cannot count, and the gain of the front-stage operational amplifier keeps the current state unchanged;
if the operational amplifier output signal is higher than the first detection threshold, the clock signal transmitter transmits an oscillator square wave signal to the forward counter and the backward counter to count forward, and generates a gain amplitude adjusting signal for reducing the gain of the front-stage operational amplifier;
if the operational amplifier output signal is lower than the second detection threshold, the clock signal transmitter transmits the oscillator square wave signal to the forward counter and the backward counter is made to count reversely, and a gain amplitude adjusting signal for increasing the gain of the preceding operational amplifier is generated.
2. The automatic gain control circuit of claim 1 wherein the first comparator and the second comparator are voltage comparators.
3. The automatic gain control circuit of any one of claims 1-2 wherein the first detection threshold is:
where Pout is the output power, vin is the input signal voltage, AV1 is the pre-op gain, AV2 is the integrator gain, and RL is the load resistor.
4. The automatic gain control circuit of any one of claims 1-2 wherein the gain amplitude adjustment signal output by the forward counter is a five-bit digital signal comprising the number of steps required to adjust the feedback resistance of the preceding op-amp.
5. An automatic gain control circuit according to any one of claims 1-2, wherein the decoder is adapted to generate a 31-bit digital code, and to act on the on-off transmission gate of the feedback resistor between the output and input of the preceding operational amplifier, the magnitude of the feedback resistor being adjusted by controlling the switching of the transmission gate.
6. A method of controlling gain adjustment speed in an AGC system, realized by using an automatic gain control circuit according to any one of claims 1-5, comprising the steps of:
the first comparator and the second comparator compare the op amp output signal with a first detection threshold and a second detection threshold respectively,
if the operational amplifier output signal is between the first detection threshold value and the second detection threshold value, the clock signal transmitter cuts off the square wave signal of the oscillator, so that the forward counter and the reverse counter cannot count, the gain of the front-stage operational amplifier keeps the current state unchanged, and the resistance value of the feedback resistor is not changed;
if the operational amplifier output signal is higher than the first detection threshold, the clock signal transmitter transmits an oscillator square wave signal to the forward counter and the backward counter to count forward, and generates a gain amplitude adjusting signal for reducing the gain of the front operational amplifier, and the decoder reduces the resistance of the feedback resistor;
if the operational amplifier output signal is lower than the second detection threshold, the clock signal transmitter transmits the oscillator square wave signal to the forward counter and the backward counter to count reversely, and generates a gain amplitude adjusting signal for increasing the gain of the preceding operational amplifier, and the decoder increases the resistance of the feedback resistor.
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| CN1812384A (en) * | 2005-01-26 | 2006-08-02 | 中兴通讯股份有限公司 | Apparatus for realizing automatic gain control in wideband wireless switch-in system terminal station |
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| CN1812384A (en) * | 2005-01-26 | 2006-08-02 | 中兴通讯股份有限公司 | Apparatus for realizing automatic gain control in wideband wireless switch-in system terminal station |
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| 王明轩 ; 李冬梅 ; .一种低电压、低噪声、低失真度的语音信号自动增益控制电路.微电子学与计算机.2016,(11),全文. * |
| 陈铖颖 ; 黑勇 ; 戴澜 ; 胡晓宇 ; .面向助听器应用的低功耗自动增益控制环路.微电子学.2013,(04),全文. * |
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