CN111209720A - Thermal stress damage simulation method for surface mounting process of electronic component - Google Patents
Thermal stress damage simulation method for surface mounting process of electronic component Download PDFInfo
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Abstract
The invention relates to a thermal stress damage simulation method for an electronic component surface mounting process, which comprises the following steps: the method comprises the following steps: analyzing the surface mounting process flow; step two: selecting the severity, the occurrence degree and the detection degree; step three: PFMECA analysis in the surface mounting process; step four: theoretical derivation of a welding spot form model; step five: establishing a simulation entity model; step six: simulating a thermal stress finite element of a surface mounting process; step seven: and (4) analyzing a simulation result and identifying thermal stress damage. The invention takes a product undergoing a surface mounting process as a research object, establishes relevant models at welding points and board levels of electronic components, explores sources of thermal stress introduced by the process, finds out the causes of thermal stress damage of the surface mounting process, and summarizes to obtain the method for the thermal stress simulation analysis of the surface mounting process of the electronic components. The method belongs to the technical field of thermal stress damage simulation of the surface mounting process of the electronic component.
Description
The technical field is as follows:
the invention relates to a simulation method for thermal stress damage of an electronic component surface mounting process, which takes a surface mounting process as a research object, analyzes the generation source of stress and corresponding solving measures in the surface mounting process, and utilizes a PFMECA analysis method to research the surface mounting process and analyze main influencing factors on the process thermal stress. Meanwhile, a corresponding computer simulation method is researched, the stress in the surface mounting process is analyzed and researched, and from the mechanical point of view, a relevant model is established to determine the morphological characteristics of the welding spot. The thermal stress distribution introduced from the technological process at the welding spot and the plate level of the electronic component is analyzed by a computer-aided and finite element analysis method, so that the simulation analysis method for the thermal stress damage of the surface mounting technology of the electronic component is formed. The method belongs to the technical field of thermal stress damage simulation of the surface mounting process of the electronic component.
(II) background technology:
with the continuous expansion of the information technology field and the coming of the intelligent era, electronic products are continuously developed towards integration, densification and lightweight. The application of a large number of high-density electronic devices leads to higher and higher packaging density of electronic components, and also puts higher requirements on electronic packaging technology. The electronic assembly process is more complex due to various electronic components, and meanwhile, the process level of equipment manufacturing enterprises in China and China has a larger gap compared with that of advanced enterprises in China, and the assembly process of the electronic components, particularly the assembly process of military electronic components, has more serious process defects and reliability problems. A large number of process defects such as welding spot holes, poor wetting, poor welding spot mechanical strength and short fatigue life seriously affect the quality and the service life of military electronic component equipment, affect the readiness integrity and simultaneously restrict the development of weapon equipment.
The surface mount technology is the most popular electronic assembly technology at present, and the technology brings high assembly density, and electronic products have small volume and light weight and are widely used. The surface mounting process is to mount and weld relevant components on the printed circuit board at corresponding positions on the surface of the printed circuit board, on which the soldering paste is printed. The process does not need to carry out the traditional related process of drilling and inserting holes, thereby simplifying the assembly process of electronic products, realizing the miniaturization and automation of the assembly of the electronic products, obviously improving the production efficiency of electronic components and the product quality of electronic components, being widely applied and having great positive influence on the development and progress of the electronic assembly industry. The surface mount technology is the most widely used electronic assembly technology at present, and plays an important role in the existing assembly technology, but the process still has problems caused by the process, which causes the phenomenon of quality reduction of electronic components.
In the surface mounting process, due to the condition problem of loading of the process procedure, the electronic device generates stress in the assembling process, the stress introduced in the process can exist in the electronic assembly, and especially the thermal stress introduced by temperature change is not negligible for the reliability of the electronic assembly. Therefore, it is necessary to start with the surface mounting process of the electronic component, analyze the region where stress damage is likely to occur during the process, and evaluate the surface mounting quality of different devices, so as to provide a part of idea for improving the process level of surface mounting, thereby improving the quality and reliability of the electronic component.
(III) the invention content:
1. the purpose is as follows: the invention aims to provide a thermal stress damage simulation method for an electronic component surface mounting process, which takes a surface mounting process as a research object, analyzes failure modes and failure mechanisms in the surface mounting process, simultaneously establishes a stress related simulation model aiming at welding spots and a printed circuit board, and analyzes the stress strain and related damage of an electronic component in the process, thereby carrying out simulation analysis on the thermal stress damage of the electronic component surface mounting process. The method is simple to operate, low in cost and convenient to implement, can be used for determining influence factors influencing stress damage in the surface mounting process, accurately analyzing thermal stress distribution generated in the process, and estimating the quality of the surface mounting process, thereby providing a basis for accurately evaluating the reliability and predicting the service life of the electronic component.
2. The technical scheme is as follows: the invention relates to a thermal stress damage simulation method for a surface mounting process of an electronic component, which comprises the following steps:
the method comprises the following steps: surface mount process flow analysis
The process flow in the surface mounting process is investigated, and the general flow of the surface mounting process is summarized to obtain a surface mounting process flow table. And further refining and analyzing the process flow which has great influence on the quality of the surface mounting process to obtain a specific process flow table.
Step two: severity, degree of occurrence and degree of detection
In order to measure the size of the process defect, a risk priority coefficient is introduced, and the higher the risk priority coefficient is, the more serious the potential problem is, and the higher the probability of causing the process defect is. The risk priority coefficient is the product of the severity, the occurrence degree and the detection degree, so that a proper criterion needs to be selected to quantitatively measure the severity, the occurrence degree and the detection degree.
Step three: PFMECA analysis of surface mount process
Aiming at the Process flow of typical electronic surface mounting, failure mode and effect Analysis (PFMECA) Analysis is carried out, and the PFMECA Analysis table of the surface mounting Process is completed. And determining key technological processes and relevant important technological parameters according to the analysis table, extracting key factors with high importance and providing a basis for the next scheme.
Step four: theoretical derivation of solder joint morphological model
And obtaining a model mathematical expression of the liquid welding spot based on the liquid bridge theory, the influence of the welding spot form on the stress, the Young-Laplace equation and other theoretical bases. And classifying the welding points according to different characteristics, and further deducing differential equations of the welding points in two common forms. And solving the obtained differential equation set by using Surface observer software to obtain a coordinate result of the welding spot in the Z-axis direction, thereby determining the form of the welding spot.
Step five: simulation entity model building
And obtaining the shape parameters of the PCB, the shape position parameters of the bonding pad, the types of the soldering paste and the related parameters required by modeling according to information such as a device manual, a device design file, a design experience value, related standards and the like. Because the PCB and the bonding pad are not changed in material before and after undergoing the surface mounting process flow, the solid modeling can be directly carried out on the PCB and the bonding pad subjected to surface mounting by utilizing Solidworks software. The shape of the welding spot greatly influences the magnitude of the residual stress at the welding spot, so the shape of the welding spot is solved by using the welding spot shape model, and then the result solved by the Surface resolver software is input into the solid modeling software to establish the solid model of the welding spot.
Step six: surface mount technology thermal stress finite element simulation
The method adopts a finite element analysis method, considers the material, the PCB board, the key components and the possible component and structure change in the electronic surface mounting process and the environmental temperature change in the surface mounting process, and utilizes ANSYSTEMWerknench software to carry out finite element simulation.
Step seven: simulation result analysis and thermal stress damage identification
And analyzing the stress-strain distribution condition of the finite element simulation model, and identifying stress-strain damage prone areas of the plate-level components and the key components in the process of surface mounting of the electronic component, so as to research the stress damage caused by the surface mounting process.
(IV) description of the drawings:
FIG. 1 is a schematic flow chart of the implementation steps
FIG. 2 is a three-dimensional schematic view of a first type of solder joint
FIG. 3 is a three-dimensional schematic diagram of a second type of welding spot
FIG. 4 is a graph of a stress analysis of a first type of solder joint
FIG. 5 is a diagram illustrating a stress analysis of a second type of solder joint
FIG. 6 Surface Everv solving flow chart
FIG. 7 is a schematic diagram of a PCB
FIG. 8 PCB grid division
FIG. 9L2(LQFP) solder joint morphology map
FIG. 10 surface mount capacitor (0402) solder joint morphology
FIG. 11 is a solder joint diagram of a surface mount resistor (0603)
FIG. 12 is a mesh division diagram at the solder points of the surface mount capacitor
FIG. 13 is a mesh division diagram at the surface mount resistance welding point
FIG. 14 surface mount chip L2Grid division diagram at welding spot
FIG. 15 reflow temperature control graph
FIG. 16 is a diagram showing a simulation result of a PCB
FIG. 17 surface mount capacitor simulated stress plot
FIG. 18 is a partial enlarged view of simulated stress of surface mount capacitor
FIG. 19 surface mount resistor simulated stress map
FIG. 20 is a partial enlarged view of simulated stress of surface mount resistor
FIG. 21 surface mount chip solder joint simulated stress map
FIG. 22 is an enlarged view of simulated stress of solder joint of surface-mounted chip
(V) specific embodiment:
the thermal stress damage simulation method of the surface mounting process of the electronic component is further described in detail with reference to the accompanying drawings, and specifically comprises the following steps:
the method comprises the following steps: surface mount process flow analysis
Firstly, the general process flow of the surface mounting process is investigated, and the general surface mounting process comprises the following six processes: printing, mounting, curing, reflow soldering, cleaning and detecting. Depending on the process requirements, the steps associated with curing and cleaning may be omitted, and the specific process flow and process requirements for each process step are shown in table 1.
Table 1 surface mounting process flow chart
Among all the processes of the surface mounting process, four processes which have a great influence on the quality of the surface mounting process are respectively as follows: printing, mounting, reflow soldering and cleaning. The four important processes are then refined and analyzed to obtain corresponding specific process flow tables (tables 2-5).
TABLE 2 printing Process flow sheet
Table 3 mounting process flow chart
TABLE 4 reflow soldering Process flow sheet
TABLE 5 cleaning Process flow sheet
| Code | Process/procedure name | Process requirements |
| 005-1 | Selection of solvents | And selecting proper solvent according to the materials of different components and substrates. |
| 005-2 | Cleaning of | And cleaning the welded substrate by using a cleaning machine to remove parts harmful to human bodies. |
| 005-3 | End of cleaning | After cleaning for a certain time, the next procedure is carried out. |
Step two: severity, degree of occurrence and degree of detection
In order to measure the size of the process defect when filling in the surface mounting process analysis table, the concept of the risk priority coefficient is introduced. The higher the risk priority coefficient, the more serious its potential problem, and the higher the probability of causing a process defect. And the risk priority coefficient is the product of the severity, the occurrence and the detection. Therefore, proper criteria are selected to quantitatively measure the severity, the occurrence degree and the detection degree, so as to fill an analysis table for completing the technological process. The following is the selection criteria of the severity occurrence and detection degree.
(1) Severity selection criteria
Severity refers to the severity of the effect of the failure mode on the product. The severity values are given in Table 6.
TABLE 6 severity value-taking table
(2) Degree of occurrence selection criterion
The occurrence degree is the probability of the fault, and the value standard is shown in table 7.
TABLE 7 Generation degree value-taking table
(3) Selection criterion of detection degree
The detection degree is the detectable degree of the fault, and the value standard is shown in the table 8.
Table 8 table for measuring value
Step three: PFMECA analysis of surface mount process
Based on the investigation and analysis, each important process is analyzed, and the influence of each important process on each aspect of the product, including the influence degree on the product, the manufacturing period, the manufacturing cost, the tooling equipment, personnel and the environment, corresponding to each fault mode is found out. According to the actual investigation condition, the appropriate degree of occurrence, degree of inspection and severity are selected, the risk priority coefficient is calculated, and the PFMECA analysis table of the surface mounting process is obtained, as shown in Table 9. When the risk priority coefficient is larger, the process fault mode is an object needing to be solved with emphasis. Necessary improvements are needed to reduce the risk priority of this process failure mode. Meanwhile, for a process failure mode with a smaller risk priority coefficient, the improvement can be ignored or not carried out under certain balance.
Through analysis of the PFMECA table, it can be found that the magnitude of thermal stress induced by the surface mount process is mainly related to the following factors. First, the design of the product itself is related to the pad size, the size of the PCB board, the volume of solder paste used, etc. Secondly, the selection of welding materials, and different materials have different wettability, which influences the magnitude of stress. And finally, controlling the reflow soldering temperature, wherein a reasonable temperature control curve can greatly reduce the stress accumulation. These factors are the key factors required for subsequent simulation modeling.
TABLE 9 PFMECA analysis Table
Step four: theoretical derivation of solder joint morphological model
To solve the morphology of the weld spot, a differential equation of the weld spot needs to be established first. The solder joints can be classified into two types according to the common solder joint morphology. The first type of solder joint is solder-bonded to the bottom of the device and to the pad, and the side of the device is free of solder, and a three-dimensional schematic diagram is shown in fig. 2. The second type of solder joint is the form where the device is not only in bottom contact with solder, but also has solder on its sides, i.e. has a solder fillet, and is shown in three-dimensional schematic in fig. 3. In order to establish a differential equation at the welding point, one half of the welding points are selected for stress analysis because the welding points are symmetrical. And defining the direction perpendicular to the paper surface inwards as an X axis, establishing a space coordinate system, selecting a section in the Z direction, and carrying out stress analysis on the welding points. Wherein, the force analysis graph of the first type welding point is shown in figure 4, and the force analysis graph of the second type welding point is shown in figure 5.
For an ideal solder joint, the liquid solder joint follows the principle of energy minimization, while assuming an ideal situation where the liquid solder joint is uniformly distributed over the pad and the boundary of the distribution is the boundary of the pad. Wherein P isdIs the pressure at the bottom of the liquid, AxThe difference between the length of the bottom pad and the length of the component, a represents the length of the pad, WzRepresenting the holding force, gamma representing the surface tension, thetadRepresents wetting angle, ρ represents density, g represents acceleration of gravity, V0Representing the volume of solder paste. The force along the Z-axis direction is defined to be positive, and because the shape of the welding spot is symmetrical and the stress conditions at two sides are the same, only half of the stress conditions of the welding spot need to be analyzed, so the mathematical expression of the model of the liquid welding spot is as follows:
Pd(2Ax+a)2+Wz-4γ(2Ax+a)sinθd-ρgV0＝0
pressure at the bottom of the liquid bridge:
for the first type of weld the static equilibrium equation is:
Pd(2yi(0)+Ly)Lx-2γ(2yi(0)+Ly)sinθj(0)-2γLxsinθi(0)+Wz-ρgV0＝0
the pressure at the bottom of the liquid bridge is:
for the second type of weld statics equilibrium equation:
Pd(2y(0)+Ly)Lx-2γ(2y(0)+Ly)sinθj(0)-2γLxsinθi(0)+Wz-ρgV0＝0
the pressure at the bottom of the liquid bridge is:
an ovalized approximation is made to the intersection of the two adjacent interfaces based on the liquid solder joint formed under the constraint of the solder pad.
(1) Differential equation at the first kind of weld
Principal curvature equation of liquid-vapor interfaces at two ends:
so another principal curvature can be obtained according to Young-Laplace equation:
differential equation of morphological parameters:
(2) differential equation at the second type of weld
When the outer welding point generates a solder wrap angle, the external volume is:
main curvature radius of solder fillet:
another principal radius of curvature can be obtained from the Young-laplace equation as follows:
taking y as an independent variable, the differential equation of the morphological parameters at the corner of the solder package is as follows:
after the differential equation is established, the solution is performed by using Surface observer software, and a flow chart is shown in fig. 6. Firstly, according to different simulation objects, relevant parameters including wetting angles, surface tension and the like, relevant boundary condition constraints and the magnitude of energy are input, then corresponding basic elements are defined and input in software, and a relevant circulation method is determined. And when the solved value does not meet the boundary condition, substituting the initially defined stored value for circular calculation until the circular condition is met. When the constraint condition of solving is met, recording as a one-time evolution process. Obviously, one evolution process cannot meet the requirement, and multiple evolutions need to be performed until the system is in a balanced state, that is, the result after the evolutions does not change along with the increase of the number of cycles, and the number of cycles at this time is recorded as m. And outputting the result of obtaining the differential equation, thereby obtaining the coordinate result of the welding spot in the Z-axis direction and further determining the shape of the welding spot.
Step five: simulation entity model building
Firstly, establishing a PCB and a pad solid model. The surface mount technology involves a wide variety of devices and sizes, and the shape and material of different devices can affect the stress, so the first step needs to determine the simulation object. Then, basic information of the simulation object, which mainly includes shape parameters of the PCB board, shape position parameters of the pads, and kinds and related parameters of the solder paste, is obtained from the known simulation object by referring to a device manual, related standards, and the like. Because the PCB and the bonding pad are not changed in material before and after undergoing the surface mounting process flow, the surface mounted PCB and the bonding pad can be subjected to solid modeling by directly utilizing a solid modeling method. Taking a surface-mounted PCB sample with a size of 60mm x 70mm and typical chip capacitors, resistors and chips as an example, a solid three-dimensional model is obtained by using SolidWorks software according to the size of the PCB and the packaging form of electronic components, as shown in fig. 7. The specification and model details of the specific resistor and capacitor are shown in table 10.
TABLE 10 device List
| Name (R) | Package form | Reference numerals | Specification of |
| Chip resistor | 0603 | R1-R6 | 1k、1v |
| Paster capacitor | 0402 | C1-C6 | 0.1μF,10v |
| Arm single-chip microcomputer | LQFP100 | L2 | STM32FL03 |
| 74 logic single chip microcomputer | DIP20 | L1 | SN74HC373N |
| Plug-in capacitor | RAD0.1 | C7-C12 | 332 |
| Chip and method for manufacturing the same | BGA484 | L3 | EP3C16F484C8N |
And the model file generated by the SolidWorks is imported into ANSYS software, the built entity model can be subjected to grid division, and the surface of the bonding pad and the surface of the PCB can be combined into a whole because the bonding pad and the PCB are positioned on the same plane. And generating related grids by using the face mesh in ANSYS, refining the places which are not finely divided automatically, and improving the precision of the simulation result. In the area near the PCB contacted with the bonding pad, the stress state of the PCB is complex, and the grid at the position needs to be further refined. The result of the grid division of the PCB panel is shown in fig. 8.
And then, establishing a solid model of the welding spot. Since the shape of the welding spot greatly affects the magnitude of the residual stress at the welding spot, the shape of the welding spot needs to be solved first. According to the correlation theory of the liquid bridge, the Young-Laplace equation is utilized, and the morphological characteristics of the welding point can be solved by means of the auxiliary calculation of the correlation software. And then inputting the morphological characteristics of the welding spot into an entity modeling software ANSYS, so as to establish an entity model of the welding spot. For the surface mount chip L in the case2In other words, the soldered pins have no solder wrap angle, and therefore belong to the first type of solder joint model, and a schematic diagram of a simulation model of the solder joint morphology is shown in fig. 9. For surface mount capacitors and resistors, there will be solder residue on the side of the mounted device, which belongs to the second type of solder joint model, and the simulation models of the solder joint morphology are shown in fig. 10 and fig. 11, respectively.
And generating related grids by using the face mesh in ANSYS, dividing the grids, and further refining the positions which are not fine enough for automatic division and the edges and the bottoms of welding points, so that the precision of a simulation result is improved. FIG. 12 shows the result of gridding the surface-mounted capacitor solder joints, FIG. 13 shows the result of gridding the surface-mounted resistor solder joints, and FIG. 14 shows the surface-mounted chip L2And dividing the result by one welding spot grid.
Step six: surface mount technology thermal stress finite element simulation
A reflow soldering temperature control curve of the surface mounting process is shown in fig. 15, the temperature curve is used as a temperature load to be applied to an established simulation model, and a thermal stress finite element simulation is carried out by using a thermal analysis module in ANSYS software. A stress-strain diagram of the electronic component can be obtained through simulation, and meanwhile, the position and the size of the maximum stress-strain point are output.
Step seven: simulation result analysis and thermal stress damage identification
By further analyzing the stress-strain result of the finite element simulation model, the stress-strain damage susceptibility area and the relative probability of the plate-level component and the key component thereof in the surface mounting process can be determined, so that the stress damage caused by the surface mounting process can be researched.
The simulation result diagram of the PCB in the case is shown in fig. 16, and it can be obtained from the diagram analysis that after the whole process thermal process, the maximum stress concentration on the PCB is in the vicinity of the pad, where the maximum stress is 0.136MPa, and is located at the sharp corner of the pad of the surface mount resistor, which is the weak link of the PCB. Meanwhile, the stress at the four corners of the PCB is relatively large, and punching treatment is recommended to be carried out at the four corners of the PCB so as to reduce the stress concentration. From the distribution range of the stress, it can be concluded that the probability of generating stress damage is higher at the place where the PCB contacts the pad than at other places.
The simulation results of the surface mount capacitor (0402) type solder joint are shown in fig. 17 and 18. As can be seen, the stress concentration at the welding point of the type is mainly distributed at the edge connected with the welding pad, and the maximum value is 0.01463 MPa. At the same time, there is also a large stress concentration at the portion connected to the device. Therefore, the weak link of the welding spot is arranged at the edge connected with the welding pad, and after the weak link is excited under certain use conditions, the link can bear larger stress damage risks.
The distribution diagrams of the simulated stress-strain of the solder joints of the surface mount resistor (0603) are shown in fig. 19 and 20. As can be seen, the stress concentration points of the surface mount resistor solder joints are still located at the portion connected with the device and the portion connected with the bonding pad. The maximum stress is 0.12843MPa, which is obviously increased compared with the maximum value of the surface mounted capacitor. Meanwhile, the stress distribution of the capacitor is greatly different from that of the surface-mounted capacitor. The range of stress concentration is significantly enlarged at the portion connected to the device, and the stress concentration at the portion connected to the pad is expanded inward. Under the same conditions, the solder joints of the surface mount resistor will have larger stress damage compared with the surface mount capacitor. Meanwhile, the range influenced by the stress damage of the surface-mounted resistor is larger than that of the surface-mounted capacitor.
Surface mount chip L2The weld point model belongs to a model of a first type of weld point, and simulation results are shown in fig. 21 and 22. From the analysis of the graph, the stress concentration portions are distributed at the connection with the bonding pad and the connection with the device. The weak link of welding is at the thinnest part connected with the bonding pad and the thinnest part connected with the device, and the maximum value of stress is 0.13991 MPa. When the connection portion is excited by an external condition, the probability of stress damage is higher than that of other portions.
Claims (8)
1. A thermal stress damage simulation method for an electronic component surface mounting process is characterized by comprising the following steps: the surface mounting process is taken as a research object, the generation source and corresponding solving measures of the stress in the surface mounting process are analyzed, the PFMECA analysis method is utilized to research the surface mounting process, and the main influence factors on the process thermal stress are analyzed. Meanwhile, a corresponding computer simulation method is researched, the stress in the surface mounting process is analyzed and researched, and from the mechanical point of view, a relevant model is established to determine the morphological characteristics of the welding spot. The thermal stress distribution introduced from the technological process at the welding spot and the plate level of the electronic component is analyzed by a computer-aided and finite element analysis method, so that the simulation analysis method for the thermal stress damage of the surface mounting technology of the electronic component is formed. The method comprises the following specific steps:
the method comprises the following steps: surface mount process flow analysis
Step two: severity, degree of occurrence and degree of detection
Step three: PFMECA analysis of surface mount process
Step four: theoretical derivation of solder joint morphological model
Step five: simulation entity model building
Step six: surface mount technology thermal stress finite element simulation
Step seven: simulation result analysis and thermal stress damage identification
And seventhly, identifying stress strain damage prone areas of the plate-level components and key components in the process of surface mounting of the electronic component by using the thermal stress finite element simulation result of the surface mounting process obtained in the step seven, and evaluating the surface mounting quality of different components, so that the process stress damage caused by the surface mounting process is researched.
2. The method for simulating the thermal stress damage of the surface mounting process of the electronic component as claimed in claim 1, wherein: the Analysis of the Process flow in the surface mounting Process in the step one lays a foundation for subsequent Failure Mode and Effects Analysis (PFMECA). The specific process is as follows:
firstly, the general process flow of the surface mounting process is investigated, and the general surface mounting process comprises the following six processes: printing, mounting, curing, reflow soldering, cleaning and detecting. Depending on the process requirements, the associated steps of curing and cleaning may be omitted.
Among all the processes of the surface mounting process, four processes which have a great influence on the quality of the surface mounting process are respectively as follows: printing, mounting, reflow soldering and cleaning. And carrying out detailed analysis on the four important working procedures to obtain a corresponding specific process flow table.
3. The method for simulating the thermal stress damage of the surface mounting process of the electronic component as claimed in claim 1, wherein: and in the step two, quantitative measurement is carried out on the severity, the occurrence degree and the detection degree of the process defects in the surface mounting process, and preparation is made for filling the process analysis table. The specific process is as follows:
in order to measure the size of the process defect when filling in the surface mounting process analysis table, the concept of the risk priority coefficient is introduced. The higher the risk priority coefficient, the more serious its potential problem, and the higher the probability of causing a process defect. And the risk priority coefficient is the product of the severity, the occurrence and the detection. Therefore, proper criteria are selected to quantitatively measure the severity, the occurrence degree and the detection degree, so as to fill an analysis table for completing the technological process.
4. The method for simulating the thermal stress damage of the surface mounting process of the electronic component as claimed in claim 1, wherein: in the third step, PFMECA analysis is performed for the process flow of typical electronic surface mounting, a PFMECA analysis table of the surface mounting process is completed, and the key process and parameters are determined. The specific process is as follows:
based on the investigation and analysis, each important process is analyzed, and the influence of each important process on each aspect of the product, including the influence degree on the product, the manufacturing period, the manufacturing cost, the tooling equipment, personnel and the environment, corresponding to each fault mode is found out. And selecting proper occurrence degree, detection degree and severity according to the actual investigation condition, and calculating to obtain a risk priority coefficient so as to obtain a PFMECA analysis table in the surface mounting process. When the risk priority coefficient is larger, the process fault mode is an object needing to be solved with emphasis. Necessary improvements are needed to reduce the risk priority of this process failure mode. Meanwhile, for a process failure mode with a smaller risk priority coefficient, the improvement can be ignored or not carried out under certain balance.
5. The method for simulating the thermal stress damage of the surface mounting process of the electronic component as claimed in claim 1, wherein: and in the fourth step, based on the liquid bridge theory, the influence of the welding spot shape on the stress and the Young-Laplace equation, deriving differential equations of the welding spots in two common shapes, and solving by using Surface observer software to determine the shape of the welding spot. The specific process is as follows:
to solve the morphology of the weld spot, a differential equation of the weld spot needs to be established first. The solder joints can be classified into two types according to the common solder joint morphology. The first type of solder joint is that the bottom of the device is connected with the pad through solder, and the side of the device is free of solder. The second type of solder joint is a form in which not only the bottom of the device is in contact with the solder, but also the side of the device is provided with the solder, i.e., the solder wrap angle is present. In order to establish a differential equation at the welding point, one half of the welding points are selected for stress analysis because the welding points are symmetrical. And defining the direction perpendicular to the paper surface inwards as an X axis, establishing a space coordinate system, selecting a section in the Z direction, and carrying out stress analysis on the welding points.
For an ideal solder joint, the liquid solder joint follows the principle of energy minimization, while assuming an ideal situation where the liquid solder joint is uniformly distributed over the pad and the boundary of the distribution is the boundary of the pad. Wherein P isdIs the pressure at the bottom of the liquid, AxThe difference between the length of the bottom pad and the length of the component, a represents the length of the pad, WzRepresenting the holding force, gamma representing the surface tension, thetadRepresents wetting angle, ρ represents density, g represents acceleration of gravity, V0Representing the volume of solder paste. The force along the Z-axis direction is defined to be positive, and because the shape of the welding spot is symmetrical and the stress conditions at two sides are the same, only half of the stress conditions of the welding spot need to be analyzed, so the mathematical expression of the model of the liquid welding spot is as follows:
Pd(2Ax+a)2+Wz-4γ(2Ax+a)sinθd-ρgV0＝0
pressure at the bottom of the liquid bridge:
for the first type of weld the static equilibrium equation is:
Pd(2yi(0)+Ly)Lx-2γ(2yi(0)+Ly)sinθj(0)-2γLxsinθi(0)+Wz-ρgV0＝0
the pressure at the bottom of the liquid bridge is:
for the second type of weld statics equilibrium equation:
Pd(2y(0)+Ly)Lx-2γ(2y(0)+Ly)sinθj(0)-2γLxsinθi(0)+Wz-ρgV0＝0
the pressure at the bottom of the liquid bridge is:
an ovalized approximation is made to the intersection of the two adjacent interfaces based on the liquid solder joint formed under the constraint of the solder pad.
(1) Differential equation at the first kind of weld
Principal curvature equation of liquid-vapor interfaces at two ends:
so another principal curvature can be obtained according to Young-Laplace equation:
differential equation of morphological parameters:
(2) differential equation at the second type of weld
When the outer welding point generates a solder wrap angle, the external volume is:
main curvature radius of solder fillet:
another principal radius of curvature can be obtained from the Young-laplace equation as follows:
taking y as an independent variable, the differential equation of the morphological parameters at the corner of the solder package is as follows:
after the differential equation is established, the solution is carried out by using Surface observer software. Firstly, according to different simulation objects, relevant parameters including wetting angles, surface tension and the like, relevant boundary condition constraints and the magnitude of energy are input, then corresponding basic elements are defined and input in software, and a relevant circulation method is determined. And when the solved value does not meet the boundary condition, substituting the initially defined stored value for circular calculation until the circular condition is met. When the constraint condition of solving is met, recording as a one-time evolution process. Obviously, one evolution process cannot meet the requirement, and multiple evolutions need to be performed until the system is in a balanced state, that is, the result after the evolutions does not change along with the increase of the number of cycles, and the number of cycles at this time is recorded as m. And outputting the result of obtaining the differential equation, thereby obtaining the coordinate result of the welding spot in the Z-axis direction and further determining the shape of the welding spot.
6. The method for simulating the thermal stress damage of the surface mounting process of the electronic component as claimed in claim 1, wherein: in the fifth step, the simulation entity model establishment is carried out on the PCB, the welding pad and the welding spot, and the concrete process is as follows:
firstly, establishing a PCB and a pad solid model. The surface mount technology involves a wide variety of devices and sizes, and the shape and material of different devices can affect the stress, so the first step needs to determine the simulation object. Then, basic information of the simulation object, which mainly includes shape parameters of the PCB board, shape position parameters of the pads, and kinds and related parameters of the solder paste, is obtained from the known simulation object by referring to a device manual, related standards, and the like. Because the PCB and the bonding pad are not changed in material before and after undergoing the surface mounting process flow, the surface mounted PCB and the bonding pad can be subjected to solid modeling by directly utilizing a solid modeling method. Taking a surface-mounted PCB sample with the size of 60mm x 70mm and typical chip capacitors, resistors and chips as an example, a solid three-dimensional model of the sample is obtained by utilizing SolidWorks software according to the size of the PCB and the packaging form of electronic components.
And the model file generated by the SolidWorks is imported into ANSYS software, the built entity model can be subjected to grid division, and the surface of the bonding pad and the surface of the PCB can be combined into a whole because the bonding pad and the PCB are positioned on the same plane. Related grids are generated by using facemesh in ANSYS, and places which are not fine enough in automatic division are refined, so that the precision of a simulation result is improved. In the area near the PCB contacted with the bonding pad, the stress state of the PCB is complex, and the grid at the position needs to be further refined.
And then, establishing a solid model of the welding spot. Since the shape of the welding spot greatly affects the magnitude of the residual stress at the welding spot, the shape of the welding spot needs to be solved first. According to the correlation theory of the liquid bridge, the Young-Laplace equation is utilized, and the morphological characteristics of the welding point can be solved by means of the auxiliary calculation of the correlation software. And then inputting the morphological characteristics of the welding spot into an entity modeling software ANSYS, so as to establish an entity model of the welding spot. For the surface mount chip L in the case2In other words, the soldered pins do not have solder wrap angle, and thus belong to the first type of solder joint model. For surface mount capacitors and resistors, the side of the mounted device may have solder residue, which belongs to the second type of solder joint model.
And generating related grids by using the face mesh in ANSYS, dividing the grids, and further refining the positions which are not fine enough for automatic division and the edges and the bottoms of welding points, so that the precision of a simulation result is improved.
7. The method for simulating the thermal stress damage of the surface mounting process of the electronic component as claimed in claim 1, wherein: and in the sixth step, the thermal stress of the surface mounting process is subjected to finite element simulation by adopting a finite element analysis method. The specific process is as follows:
and applying the reflow soldering temperature control curve of the surface mounting process as a temperature load to the established simulation model, and performing thermal stress finite element simulation by using a thermal analysis module in ANSYS software. A stress-strain diagram of the electronic component can be obtained through simulation, and meanwhile, the position and the size of the maximum stress-strain point are output.
8. The method for simulating the thermal stress damage of the surface mounting process of the electronic component as claimed in claim 1, wherein: and seventhly, analyzing the finite element simulation result, and identifying the stress damage caused by the surface mounting process of the electronic product. The specific process is as follows:
by further analyzing the stress-strain result of the finite element simulation model, the stress-strain damage susceptibility area and the relative probability of the plate-level component and the key component thereof in the surface mounting process can be determined, so that the stress damage caused by the surface mounting process can be researched.
The analysis of the simulation result diagram of the PCB in the case can be used for obtaining that after the whole process thermal process, the maximum stress concentration on the PCB is positioned near the bonding pad, wherein the maximum stress is 0.136MPa, and the maximum stress is positioned at the sharp corner of the bonding pad of the surface-mounted resistor and is a weak link of the PCB. Meanwhile, the stress at the four corners of the PCB is relatively large, and punching treatment is recommended to be carried out at the four corners of the PCB so as to reduce the stress concentration. From the distribution range of the stress, it can be concluded that the probability of generating stress damage is higher at the place where the PCB contacts the pad than at other places.
As can be seen from the simulation result diagram of the surface mount capacitor (0402) type welding spot, the stress concentration at the welding spot is mainly distributed at the edge connected with the welding spot, and the maximum value is 0.01463 MPa. At the same time, there is also a large stress concentration at the portion connected to the device. Therefore, the weak link of the welding spot is arranged at the edge connected with the welding pad, and after the weak link is excited under certain use conditions, the link can bear larger stress damage risks.
As can be seen from the simulated stress-strain distribution diagram of the solder joint of the surface mount resistor (0603), the stress concentration point of the solder joint of the surface mount resistor is still at the part connected with the device and the part connected with the bonding pad. The maximum stress is 0.12843MPa, which is obviously increased compared with the maximum value of the surface mounted capacitor. Meanwhile, the stress distribution of the capacitor is greatly different from that of the surface-mounted capacitor. The range of stress concentration is significantly enlarged at the portion connected to the device, and the stress concentration at the portion connected to the pad is expanded inward. Under the same conditions, the solder joints of the surface mount resistor will have larger stress damage compared with the surface mount capacitor. Meanwhile, the range influenced by the stress damage of the surface-mounted resistor is larger than that of the surface-mounted capacitor.
Mounting of chip L by surface2The simulation result graph of the welding spot model is analyzed, and stress concentration parts are distributed at the connection part with the welding disc and the connection part with the device. The weak link of welding is at the thinnest part connected with the bonding pad and the thinnest part connected with the device, and the maximum value of stress is 0.13991 MPa. When the connection portion is excited by an external condition, the probability of stress damage is higher than that of other portions.
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