CN111208415A - Distributed ring oscillator network layout filling hardware Trojan horse detection method and circuit - Google Patents
Distributed ring oscillator network layout filling hardware Trojan horse detection method and circuit Download PDFInfo
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- G—PHYSICS
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- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
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- G01R31/318328—Generation of test inputs, e.g. test vectors, patterns or sequences for delay tests
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31704—Design for test; Design verification
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- G—PHYSICS
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
- G01R31/318307—Generation of test inputs, e.g. test vectors, patterns or sequences computer-aided, e.g. automatic test program generator [ATPG], program translations, test program debugging
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Abstract
The invention belongs to the technical field of integrated circuit detection, and particularly relates to a distributed ring oscillator network layout filling hardware Trojan horse detection method and a circuit, wherein the distributed ring oscillator network layout filling hardware Trojan horse detection method comprises the following steps: acquiring a fragile node in a carrier circuit; adding an initial detection circuit on a carrier circuit to obtain the carrier circuit added with the initial detection circuit; setting a process deviation fluctuation range, and establishing a process library with process deviation fluctuation; filling a ring oscillator network to obtain a first security chip and a second security chip; implanting a preset hardware Trojan into the second safety chip to obtain a chip to be tested; dynamic simulation is carried out to construct a safe chip path delay information data set and a chip path delay information data set to be tested; extracting main characteristic components, and respectively performing dimensionality reduction processing to obtain safe low-dimensional data and low-dimensional data to be detected; and carrying out comparative analysis to obtain an analysis result. The method has the advantages of improving the chip delay information precision, improving the detection accuracy, reducing the chip area consumption and realizing the hardware Trojan horse positioning.
Description
Technical Field
The invention belongs to the technical field of integrated circuit detection, and particularly relates to a distributed ring oscillator network layout filling hardware Trojan horse detection method and circuit.
Background
As integrated circuit technology advances to the submicron level, the complexity and cost of integrated circuits increases dramatically, with only a few companies having the ability to maintain the entire supply chain from design to fabrication. To reduce costs, design companies have moved the manufacturing process of some chips to third party companies or manufacturing plants that have lower production costs, which are not completely trusted. An attacker may maliciously insert a circuit, i.e. a hardware trojan, in the chip to implement a certain function. Hardware trojans may cause leakage of critical information, circuit malfunction, and reduced chip reliability, even destroying the system under specific design conditions.
The safety problem of the integrated circuit is widely concerned, the independent credibility of the chip becomes an urgent need, and the detection theory and method of the hardware Trojan horse become the leading edge and hot research subject of the field of the integrated circuit at home and abroad. At present, hardware Trojan horse detection methods are multiple, and mainly comprise a reverse-cut chip, bypass information analysis and Trojan horse activation. The detection method based on the side channel information mainly judges whether the chip to be detected contains the hardware Trojan horse or not by comparing the side channel information difference between the security chip and the chip to be detected. The method has the advantages that the circuit does not need to be damaged (failure analysis), the Trojan horse circuit does not need to be completely activated (logic test technology), and the method has a good detection effect, a high detection rate and low detection cost.
However, the present detection method based on side channel information, which uses the delay information of the chip as a fingerprint to determine whether there is a hardware Trojan in the chip to be tested, can only detect the hardware Trojan greatly affecting the critical path, and if it is necessary to detect the hardware Trojan only changing the delay of the non-critical path, it is necessary to do a lot of test cases; however, in order to keep the concealment of the Trojan horse, the Trojan horse mostly exists on a non-critical path, so that the influence of the existence of the Trojan horse on the time delay and the power consumption is reduced; meanwhile, most of the hardware trojans of the combinational logic type do not have connection with a clock network, so that the existence of the hardware trojans of the combinational logic type is difficult to detect.
In addition, in the manufacturing process of the integrated circuit, when a gate is formed, different processes can be used at different positions by using a mask plate, so that important parameters of the actual device, such as gate length, gate width, gate oxide thickness and the like, drift to a certain extent, and some important performance parameters of the device generate irreversible deviation. Due to the existence of the process deviation, when the delay information of the comparison circuit after the hardware trojan is inserted is changed, the process deviation has different degrees of covering effect on the change of the delay characteristic caused by the insertion of the hardware trojan, and the influence of the hardware trojan on the circuit even can be submerged in the process deviation, namely, the process deviation and the influence of the hardware trojan on the circuit cannot be thoroughly distinguished and shown.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a distributed ring oscillator network layout filling hardware Trojan horse detection method and a circuit. The technical problem to be solved by the invention is realized by the following technical scheme:
a distributed ring oscillator network layout filling hardware Trojan horse detection method and a circuit thereof comprise:
acquiring a plurality of fragile nodes in a carrier circuit;
adding an initial detection circuit on the carrier circuit to obtain the carrier circuit added with the initial detection circuit;
setting a process deviation fluctuation range on the carrier circuit added with the initial detection circuit, and establishing a process library with process deviation fluctuation;
filling a ring oscillator network into the carrier circuit added with the initial detection circuit according to the fragile nodes to obtain a carrier circuit added with the detection circuit, and obtaining a first safety chip and a second safety chip according to the carrier circuit added with the detection circuit;
implanting a preset hardware trojan into the second safety chip to obtain a chip to be tested;
respectively carrying out dynamic simulation on the first security chip and the chip to be tested according to the process library with process deviation fluctuation to respectively obtain a security dynamic simulation result and a Trojan dynamic simulation result, and respectively constructing a security chip path delay information data set and a chip path delay information data set to be tested according to the security dynamic simulation result and the Trojan dynamic simulation result;
respectively extracting main characteristic components in the safe chip path delay information data set and the chip path delay information data set to be detected, and respectively performing dimensionality reduction on the main characteristic components to obtain safe low-dimensional data and low-dimensional data to be detected;
and carrying out comparative analysis on the safe low-dimensional data and the low-dimensional data to be detected to obtain an analysis result.
In one embodiment of the invention, acquiring a number of fragile nodes in a carrier circuit comprises:
generating a test vector by using Tetramax to perform dynamic simulation on the carrier circuit to obtain a dynamic simulation result;
obtaining a plurality of node turnover rates in the carrier circuit according to the dynamic simulation result;
and obtaining a plurality of fragile nodes according to the node turnover rates and a preset node turnover rate threshold value.
In an embodiment of the present invention, respectively performing dynamic simulation on the first secure chip and the chip to be tested according to the process library with process deviation fluctuation to obtain a secure dynamic simulation result and a Trojan dynamic simulation result, and respectively constructing a secure chip path delay information data set and a chip path delay information data set to be tested according to the secure dynamic simulation result and the Trojan dynamic simulation result, including:
the process library with the process deviation fluctuation is used for simulating the process deviation, and the first safety chip is dynamically simulated through test excitation to obtain a safety dynamic simulation result;
simulating the process deviation by using the process library with the process deviation fluctuation, and carrying out dynamic simulation on the chip to be tested through test excitation to obtain a Trojan dynamic simulation result;
constructing a safety chip path delay information data set according to the safety dynamic simulation result;
and constructing a path delay information data set of the chip to be tested according to the Trojan dynamic simulation result.
The invention also provides a distributed ring oscillator network layout filling hardware Trojan horse detection circuit, which comprises: the system comprises a linear shift register, a decoder, a data selector, a counter and a ring oscillator network;
a test excitation output end of the linear shift register sends test excitation to the ring oscillator network through a signal input end of the ring oscillator network;
the selection signal input end of the decoder inputs an external selection signal, and the signal output end of the decoder is connected with the enable ends of the ring oscillator networks to input an enable signal;
the external selection signal is also input to a selection signal input end of the data selector, the signal input end of the data selector is connected with the signal output ends of the ring oscillator networks, and the output end of the data selector is connected with the input end of the counter;
and the output end of the counter outputs a dynamic simulation result.
In one embodiment of the invention, the ring oscillator network comprises a number of ring oscillators, the ring oscillators comprising a nand gate, four inverters (I1, I2, I3, I4);
a first signal input end of the NAND gate is used as an enabling end of the ring oscillator network and connected with a signal output end of the decoder, and a second signal input end of the NAND gate is used as a signal input end of the ring oscillator network and connected with a test excitation output end of the linear shift register;
the signal output end of the nand gate is connected with the signal input end of the inverter I1, the signal output end of the inverter I1 is connected with the signal input end of the inverter I2, the signal output end of the inverter I2 is used as the signal output end of the ring oscillator network and is connected with the signal input end of the data selector, the signal input end of the inverter I3 is connected with the signal output end of the inverter I2, the signal input end of the inverter I4 is connected with the signal output end of the inverter I3, and the signal output end of the inverter I4 is connected with the second signal input end of the nand gate.
The invention has the beneficial effects that:
the method mainly detects the fragile nodes in the circuit, the ring oscillator network can be adjusted according to the specific circuit, the influence of process deviation on path delay information is considered, the precision and the detection accuracy of chip delay information are improved, and meanwhile, the positioning function of the hardware Trojan horse can be realized; the invention adopts a non-destructive method to detect the Trojan horse of the hardware on the chip; the ring oscillator network in the invention fills the blank area of the layout in the layout stage, thereby reducing the consumption of chip area.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
Fig. 1 is a block diagram of a step of a distributed ring oscillator network layout filling hardware Trojan horse detection method according to an embodiment of the present invention;
fig. 2 is a circuit diagram of a distributed ring oscillator network layout filling hardware Trojan horse detection circuit provided in the embodiment of the present invention;
fig. 3 is a circuit diagram of a ring oscillator in another distributed ring oscillator network layout filling hardware Trojan horse detection circuit according to an embodiment of the present invention;
fig. 4 is a schematic diagram of another distributed ring oscillator network layout filling hardware Trojan horse detection circuit provided in the embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Referring to fig. 1, fig. 1 is a block diagram of a method for detecting a Trojan horse in a distributed ring oscillator network layout filling hardware provided in an embodiment of the present invention, including:
acquiring a plurality of fragile nodes in a carrier circuit;
adding an initial detection circuit on the carrier circuit to obtain the carrier circuit added with the initial detection circuit;
setting a process deviation fluctuation range on the carrier circuit added with the initial detection circuit, and establishing a process library with process deviation fluctuation;
filling a ring oscillator network into the carrier circuit added with the initial detection circuit according to the fragile nodes to obtain a carrier circuit added with the detection circuit, and obtaining a first safety chip and a second safety chip according to the carrier circuit added with the detection circuit;
implanting a preset hardware trojan into the second safety chip to obtain a chip to be tested;
respectively carrying out dynamic simulation on the first security chip and the chip to be tested according to the process library with process deviation fluctuation to respectively obtain a security dynamic simulation result and a Trojan dynamic simulation result, and respectively constructing a security chip path delay information data set and a chip path delay information data set to be tested according to the security dynamic simulation result and the Trojan dynamic simulation result;
respectively extracting main characteristic components in the safe chip path delay information data set and the chip path delay information data set to be detected, and respectively performing dimensionality reduction on the main characteristic components to obtain safe low-dimensional data and low-dimensional data to be detected;
and carrying out comparative analysis on the safe low-dimensional data and the low-dimensional data to be detected to obtain an analysis result.
Further, the safety dynamic simulation result can be obtained in a simulation mode, and further a safety chip path delay information data set is obtained.
The path delay information data set of the security chip is obtained without actually producing the first security chip, so that the whole detection can be completed only by testing the chip to be detected, and the detection cost and the complexity are reduced.
Furthermore, when a plurality of ring oscillator networks are filled in the carrier circuit added with the initial detection circuit, the ring oscillator filled in the blank area of the layout can be searched in the area where the fragile nodes are densely distributed according to the distribution of the fragile nodes on the carrier circuit added with the initial detection circuit.
The method mainly detects the fragile nodes in the circuit, the ring oscillator network can be adjusted according to the specific circuit, the influence of process deviation on path delay information is considered, the precision and the detection accuracy of chip delay information are improved, and meanwhile, the positioning function of the hardware Trojan horse can be realized; the invention adopts a non-destructive method to detect the Trojan horse of the hardware on the chip; the ring oscillator network in the invention fills the blank area of the layout in the layout stage, thereby reducing the consumption of chip area.
In one embodiment of the invention, acquiring a number of fragile nodes in a carrier circuit comprises:
generating a test vector by using a Tetramax (automatic test excitation generation tool) to perform dynamic simulation on the carrier circuit to obtain a dynamic simulation result;
obtaining a plurality of node turnover rates in the carrier circuit according to the dynamic simulation result;
and obtaining a plurality of fragile nodes according to the node turnover rates and a preset node turnover rate threshold value.
In an embodiment of the present invention, respectively performing dynamic simulation on the first secure chip and the chip to be tested according to the process library with process deviation fluctuation to obtain a secure dynamic simulation result and a Trojan dynamic simulation result, and respectively constructing a secure chip path delay information data set and a chip path delay information data set to be tested according to the secure dynamic simulation result and the Trojan dynamic simulation result, including:
the process library with the process deviation fluctuation is used for simulating the process deviation, and the first security chip is dynamically simulated through test excitation patterns to obtain a security dynamic simulation result;
simulating the process deviation by using the process library with the process deviation fluctuation, and performing dynamic simulation on the chip to be tested through test excitation patterns to obtain a Trojan dynamic simulation result;
constructing a safety chip path delay information data set according to the safety dynamic simulation result;
and constructing a path delay information data set of the chip to be tested according to the Trojan dynamic simulation result.
Specifically, the process library of the process variation is used for simulating the influence of the change of the PVT (process, voltage and temperature) on the chip on the circuit delay
Referring to fig. 2, fig. 2 is a circuit diagram of a distributed ring oscillator network layout filling hardware Trojan detection circuit according to an embodiment of the present invention, including: the linear shift register LFSR, the Decoder Decoder, the data selector MUX, the Counter and the ring oscillator network;
a test excitation pattern output end of the linear shift register LFSR sends a test excitation pattern to the ring oscillator network through a signal input end of the ring oscillator network;
the selection signal input end of the Decoder inputs an external selection signal Select Bits, and the signal output end of the Decoder is connected with the enable end input enable signals of the ring oscillator networks;
the selection signal input end of the data selector MUX also inputs the external selection signal Select Bits, the signal input end of the data selector MUX is connected with the signal output ends of the ring oscillator networks, and the output end of the data selector MUX is connected with the input end of the Counter;
and the output end of the Counter outputs a dynamic simulation result and performs Data Analysis.
In an embodiment of the present invention, the ring oscillator network includes a plurality of ring oscillators, please refer to fig. 3, fig. 3 is a circuit diagram of a ring oscillator in another distributed ring oscillator network layout filling hardware Trojan detection circuit provided in the embodiment of the present invention, the ring oscillator includes a nand gate, four inverters (I1, I2, I3, I4);
a first signal input end of the nand gate is used as an enabling end of the ring oscillator network and connected with a signal output end of the Decoder, and a second signal input end of the nand gate is used as a signal input end of the ring oscillator network and connected with a test excitation pattern output end of the linear shift register LFSR;
the signal output end of the nand gate is connected with the signal input end of the inverter I1, the signal output end of the inverter I1 is connected with the signal input end of the inverter I2, the signal output end of the inverter I2 is used as the signal output end of the ring oscillator network and is connected with the signal input end of the data selector MUX, the signal input end of the inverter I3 is connected with the signal output end of the inverter I2, the signal input end of the inverter I4 is connected with the signal output end of the inverter I3, and the signal output end of the inverter I4 is connected with the second signal input end of the nand gate.
Specifically, in the detection process, it is ensured that the first security chip and the chip to be tested provide the same test excitation patterns; the Decoder and the data selector MUX are used for enabling a single ring oscillator network to be effective and correspondingly outputting the effective and corresponding output to the Counter at the same time, and selecting the next ring oscillator after the counting time is over until all ring oscillators are traversed; the Counter is used to count the output frequency of the ring oscillator network.
Further, referring to fig. 4, fig. 4 is a schematic diagram of another layout filling hardware Trojan horse detection circuit of a distributed Ring oscillator network according to an embodiment of the present invention, where the number of Power bars in the horizontal direction of a carrier circuit is 3, the number of Power bars in the vertical direction is 2, and the layout encloses a Ring of Power rings, the Power networks divide the layout into 12 regions, and each region is provided with a 5-stage Ring oscillator network, the number of Ring oscillator networks ROi (i ═ 1,2,3 …,12) is 12, and the number of Ring oscillator networks ROi (i ═ 1,2, …, N ═ 12), the enable end ENi (i ═ 1,2,3 …,12) of the Ring oscillator network, the signal output end OUTi (i ═ 1,2,3 …,12) of the Ring oscillator network, and the output oscillation frequency is fi (i ═ 1,2,3 …, 12).
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (5)
1. The distributed ring oscillator network layout filling hardware Trojan horse detection method is characterized by comprising the following steps:
acquiring a plurality of fragile nodes in a carrier circuit;
adding an initial detection circuit on the carrier circuit to obtain the carrier circuit added with the initial detection circuit;
setting a process deviation fluctuation range on the carrier circuit added with the initial detection circuit, and establishing a process library with process deviation fluctuation;
filling a ring oscillator network into the carrier circuit added with the initial detection circuit according to the fragile nodes to obtain a carrier circuit added with the detection circuit, and obtaining a first safety chip and a second safety chip according to the carrier circuit added with the detection circuit;
implanting a preset hardware trojan into the second safety chip to obtain a chip to be tested;
respectively carrying out dynamic simulation on the first security chip and the chip to be tested according to the process library with process deviation fluctuation to respectively obtain a security dynamic simulation result and a Trojan dynamic simulation result, and respectively constructing a security chip path delay information data set and a chip path delay information data set to be tested according to the security dynamic simulation result and the Trojan dynamic simulation result;
respectively extracting main characteristic components in the safe chip path delay information data set and the chip path delay information data set to be detected, and respectively performing dimensionality reduction on the main characteristic components to obtain safe low-dimensional data and low-dimensional data to be detected;
and carrying out comparative analysis on the safe low-dimensional data and the low-dimensional data to be detected to obtain an analysis result.
2. The distributed ring oscillator network layout filling hardware Trojan horse detection method according to claim 1, wherein obtaining a plurality of vulnerable nodes in a carrier circuit comprises:
generating a test vector by using Tetramax to perform dynamic simulation on the carrier circuit to obtain a dynamic simulation result;
obtaining a plurality of node turnover rates in the carrier circuit according to the dynamic simulation result;
and obtaining a plurality of fragile nodes according to the node turnover rates and a preset node turnover rate threshold value.
3. The distributed ring oscillator network layout hardware-filled Trojan detection method according to claim 1, wherein the dynamic simulation is respectively performed on the first secure chip and the chip to be detected according to the process library with process deviation fluctuation to obtain a secure dynamic simulation result and a Trojan dynamic simulation result, and a secure chip path delay information data set and a chip path delay information data set to be detected are respectively constructed according to the secure dynamic simulation result and the Trojan dynamic simulation result, comprising:
the process library with the process deviation fluctuation is used for simulating the process deviation, and the first safety chip is dynamically simulated through test excitation to obtain a safety dynamic simulation result;
simulating the process deviation by using the process library with the process deviation fluctuation, and carrying out dynamic simulation on the chip to be tested through test excitation to obtain a Trojan dynamic simulation result;
constructing a safety chip path delay information data set according to the safety dynamic simulation result;
and constructing a path delay information data set of the chip to be tested according to the Trojan dynamic simulation result.
4. Distributed ring oscillator network layout fills hardware trojan detection circuitry, its characterized in that includes: the system comprises a linear shift register, a decoder, a data selector, a counter and a ring oscillator network;
a test excitation output end of the linear shift register sends test excitation to the ring oscillator network through a signal input end of the ring oscillator network;
the selection signal input end of the decoder inputs an external selection signal, and the signal output end of the decoder is connected with the enable ends of the ring oscillator networks to input an enable signal;
the external selection signal is also input to a selection signal input end of the data selector, the signal input end of the data selector is connected with the signal output ends of the ring oscillator networks, and the output end of the data selector is connected with the input end of the counter;
and the output end of the counter outputs a dynamic simulation result.
5. The distributed ring oscillator network layout filling hardware Trojan detection circuit of claim 4, wherein the ring oscillator network comprises a number of ring oscillators, the ring oscillators comprising a NAND gate, four inverters (I1, I2, I3, I4);
a first signal input end of the NAND gate is used as an enabling end of the ring oscillator network and connected with a signal output end of the decoder, and a second signal input end of the NAND gate is used as a signal input end of the ring oscillator network and connected with a test excitation output end of the linear shift register;
the signal output end of the nand gate is connected with the signal input end of the inverter I1, the signal output end of the inverter I1 is connected with the signal input end of the inverter I2, the signal output end of the inverter I2 is used as the signal output end of the ring oscillator network and is connected with the signal input end of the data selector, the signal input end of the inverter I3 is connected with the signal output end of the inverter I2, the signal input end of the inverter I4 is connected with the signal output end of the inverter I3, and the signal output end of the inverter I4 is connected with the second signal input end of the nand gate.
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Application publication date: 20200529 |