CN111207659A - Chip parameter detection method and device based on capacitor array - Google Patents

Chip parameter detection method and device based on capacitor array Download PDF

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Publication number
CN111207659A
CN111207659A CN202010013541.3A CN202010013541A CN111207659A CN 111207659 A CN111207659 A CN 111207659A CN 202010013541 A CN202010013541 A CN 202010013541A CN 111207659 A CN111207659 A CN 111207659A
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matrix
sub
chip
corner
characteristic information
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霍彦明
李争
张路成
李晓伟
谷存江
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Shijiazhuang Fuke Electronic Technology Co ltd
Hebei University of Science and Technology
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Shijiazhuang Fuke Electronic Technology Co ltd
Hebei University of Science and Technology
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01B—MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
    • G01B7/00—Measuring arrangements characterised by the use of electric or magnetic techniques
    • G01B7/003—Measuring arrangements characterised by the use of electric or magnetic techniques for measuring position, not involving coordinate determination
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01B—MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
    • G01B7/00—Measuring arrangements characterised by the use of electric or magnetic techniques
    • G01B7/02—Measuring arrangements characterised by the use of electric or magnetic techniques for measuring length, width or thickness
    • G01B7/06—Measuring arrangements characterised by the use of electric or magnetic techniques for measuring length, width or thickness for measuring thickness
    • G01B7/08—Measuring arrangements characterised by the use of electric or magnetic techniques for measuring length, width or thickness for measuring thickness using capacitive means
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01B—MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
    • G01B7/00—Measuring arrangements characterised by the use of electric or magnetic techniques
    • G01B7/30—Measuring arrangements characterised by the use of electric or magnetic techniques for measuring angles or tapers; for testing the alignment of axes
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01B—MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
    • G01B7/00—Measuring arrangements characterised by the use of electric or magnetic techniques
    • G01B7/30—Measuring arrangements characterised by the use of electric or magnetic techniques for measuring angles or tapers; for testing the alignment of axes
    • G01B7/31—Measuring arrangements characterised by the use of electric or magnetic techniques for measuring angles or tapers; for testing the alignment of axes for testing the alignment of axes
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01D—MEASURING NOT SPECIALLY ADAPTED FOR A SPECIFIC VARIABLE; ARRANGEMENTS FOR MEASURING TWO OR MORE VARIABLES NOT COVERED IN A SINGLE OTHER SUBCLASS; TARIFF METERING APPARATUS; MEASURING OR TESTING NOT OTHERWISE PROVIDED FOR
    • G01D5/00—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable
    • G01D5/12—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means
    • G01D5/14—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage
    • G01D5/24—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage by varying capacitance
    • G01D5/2405—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage by varying capacitance by varying dielectric

Abstract

The application discloses a chip parameter detection method and device based on a capacitor array, and relates to the field of electronic component detection. According to the chip parameter detection method and device, the chip to be detected is placed between the upper pole plate array and the lower pole plate array of the capacitor array, the capacitance values of all capacitors are respectively collected to obtain the capacitance value matrix, the central axis of the chip to be detected is determined based on the position of the target element in the capacitance value matrix, and the offset angle of the chip to be detected is determined and output based on the central axis and the preset 0-degree reference line, so that the chip to be detected can be favorably subjected to targeted operation by a chip mounter according to the offset angle, the use of a limiting device is avoided, and the chip mounting operation efficiency is improved.

Description

Chip parameter detection method and device based on capacitor array
Technical Field
The application relates to the field of electronic component detection, in particular to a chip parameter detection method and device based on a capacitor array.
Background
With the development of the times, the development of the chip mounting technology is faster and faster, and how to ensure the accuracy and the high efficiency of the chip mounting technology gradually becomes the key point of research of people.
In the existing chip mounting technology, the chip often can produce the skew of certain angle at the in-process of placing, and the chip mounter discerns the chip of skew, the effect of paster is not good, so can adopt limiting device to restrict the position of chip before the chip mounter operates the chip, even so, the chip still can produce the skew of certain angle, and adopt limiting device can reduce the efficiency of chip paster operation.
Disclosure of Invention
The application provides a chip parameter detection method and device based on a capacitor array, which can be beneficial to improving the efficiency of chip surface mounting operation.
In order to achieve the above technical effect, a first aspect of the present application provides a chip parameter detection method based on a capacitor array, where the capacitor array includes: m by N capacitors, wherein M and N are not less than 2;
the chip parameter detection method comprises the following steps:
placing a chip to be detected between an upper plate array and a lower plate array of the capacitor array, wherein the upper plate array is composed of upper plates of the M × N capacitors, and the lower plate array is composed of lower plates of the M × N capacitors;
respectively collecting capacitance values of each capacitor in the M x N capacitors to obtain a capacitance value matrix with the size of M x N, wherein the elements in the ith row and the jth column in the capacitance value matrix are the capacitance values of the capacitors in the ith row and the jth column in the M x N capacitors, i belongs to [1, M ], and j belongs to [1, N ];
determining the central axis of the chip to be detected based on the position of a target element in the capacitance matrix, wherein the target element is an element with a capacitance value larger than a capacitance threshold value;
and determining and outputting the offset angle of the chip to be detected based on the central axis and a preset 0-degree reference line, wherein the offset angle is the offset angle of the central axis relative to the 0-degree reference line.
Based on the first aspect of the present application, in a first possible implementation manner, the determining a central axis of the chip to be detected based on a position of a target element in the capacitance matrix includes:
determining the positions of four corner points of the chip to be detected based on the positions of the target elements in the capacitance matrix;
and determining the central axis of the chip to be detected based on the positions of the four corner points.
Based on the first possible implementation manner of the first aspect of the present application, in a second possible implementation manner, the determining the positions of the four corner points of the chip to be detected based on the position of the target element in the capacitance matrix specifically includes:
extracting all sub-matrixes of the capacitance matrix by using a preset matrix window, and multiplying each sub-matrix by a preset angular point operator matrix to obtain a Hadamard product matrix, wherein the angular point operator matrix and the matrix window have the same row number and column number;
determining an upper left sub-matrix, an upper right sub-matrix, a lower left sub-matrix and a lower right sub-matrix based on the Hadamard product matrixes and preset angular point matrix characteristic information; wherein, the angular point matrix characteristic information includes: the information comprises upper left corner matrix characteristic information, upper right corner matrix characteristic information, lower left corner matrix characteristic information and lower right corner matrix characteristic information, wherein the upper left corner sub-matrix is a sub-matrix corresponding to a Hadamard product matrix matched with the upper left corner matrix characteristic information, the upper right corner sub-matrix is a sub-matrix corresponding to a Hadamard product matrix matched with the upper right corner matrix characteristic information, and the lower left corner sub-matrix is a sub-matrix corresponding to a Hadamard product matrix matched with the lower left corner matrix characteristic information; the lower left sub-matrix is a sub-matrix corresponding to a Hadamard product matrix matched with the characteristic information of the lower left sub-matrix;
and respectively determining the position of the upper left corner point of the upper left corner sub-matrix, the position of the upper right corner point of the upper right corner sub-matrix, the position of the lower left corner point of the lower left corner sub-matrix and the position of the lower right corner point of the lower right corner sub-matrix as the positions of the four corner points of the chip to be detected.
Based on the first possible implementation manner of the first aspect of the present application, in a third possible implementation manner, the determining the positions of the four corner points of the chip to be detected based on the position of the target element in the capacitance matrix specifically includes:
carrying out overall feature recognition on the region where the target element is located in the capacitance matrix;
and determining the positions of the four corner points of the chip to be detected based on the overall feature recognition result.
Based on the first aspect of the present application or the first, second, or third possible implementation manner of the first aspect of the present application, in a fourth possible implementation manner, the chip parameter detection method further includes:
and measuring and calculating the thickness of the chip to be detected based on the relation parameters of the plate area, the capacitance value and the thickness of a target capacitor, wherein the target capacitor is a capacitor corresponding to a target element, and the plate area is the opposite area of an upper plate and a lower plate of the target capacitor.
The second aspect of the present application provides a chip parameter detection apparatus based on a capacitor array, where the capacitor array includes: m by N capacitors, wherein M and N are not less than 2;
the chip parameter detection device comprises:
the chip to be detected is placed between an upper plate array and a lower plate array of the capacitor array, wherein the upper plate array is composed of upper plates of the M × N capacitors, and the lower plate array is composed of lower plates of the M × N capacitors;
an acquisition unit, configured to acquire capacitance values of each capacitor in the M × N capacitors, respectively, to obtain a capacitance value matrix of M × N size, where an element in an ith row and a jth column in the capacitance value matrix is a capacitance value of a capacitor in an ith row and a jth column in the M × N capacitors, i belongs to [1, M ], and j belongs to [1, N ];
the first determining unit is used for determining the central axis of the chip to be detected based on the position of a target element in the capacitance matrix, wherein the target element is an element of which the capacitance value is greater than a capacitance threshold value;
and the second determining unit is used for determining and outputting the offset angle of the chip to be detected based on the central axis and a preset 0-degree reference line, wherein the offset angle is the offset angle of the central axis relative to the 0-degree reference line.
Based on the second aspect of the present application, in a first possible implementation manner, the first determining unit is specifically configured to:
determining the positions of four corner points of the chip to be detected based on the positions of the target elements in the capacitance matrix;
and determining the central axis of the chip to be detected based on the positions of the four corner points.
Based on the first possible implementation manner of the second aspect of the present application, in a second possible implementation manner, the first determining unit is further specifically configured to:
extracting all sub-matrixes of the capacitance matrix by using a preset matrix window, and multiplying each sub-matrix by a preset angular point operator matrix to obtain a Hadamard product matrix, wherein the angular point operator matrix and the matrix window have the same row number and column number;
determining an upper left sub-matrix, an upper right sub-matrix, a lower left sub-matrix and a lower right sub-matrix based on the Hadamard product matrixes and preset angular point matrix characteristic information; wherein, the angular point matrix characteristic information includes: the information comprises upper left corner matrix characteristic information, upper right corner matrix characteristic information, lower left corner matrix characteristic information and lower right corner matrix characteristic information, wherein the upper left corner sub-matrix is a sub-matrix corresponding to a Hadamard product matrix matched with the upper left corner matrix characteristic information, the upper right corner sub-matrix is a sub-matrix corresponding to a Hadamard product matrix matched with the upper right corner matrix characteristic information, and the lower left corner sub-matrix is a sub-matrix corresponding to a Hadamard product matrix matched with the lower left corner matrix characteristic information; the lower left sub-matrix is a sub-matrix corresponding to a Hadamard product matrix matched with the characteristic information of the lower left sub-matrix;
and respectively determining the position of the upper left corner point of the upper left corner sub-matrix, the position of the upper right corner point of the upper right corner sub-matrix, the position of the lower left corner point of the lower left corner sub-matrix and the position of the lower right corner point of the lower right corner sub-matrix as the positions of the four corner points of the chip to be detected.
A third aspect of the present application provides a chip parameter detecting apparatus, including a memory, a processor, and a capacitor array, where the memory stores a computer program, and the capacitor array includes: m by N capacitors, wherein M and N are not less than 2;
the processor, when executing the computer program, implements the steps of the chip parameter detection method of the first aspect or any possible implementation manner of the first aspect.
A fourth aspect of the present application provides a computer-readable storage medium, which stores a computer program, and the computer program, when executed by a processor, implements the steps of the chip parameter detection method mentioned in the first aspect or any of the possible implementation manners of the first aspect.
Therefore, according to the scheme, the chip to be detected is placed between the upper pole plate array and the lower pole plate array of the capacitor array, then the capacitance values of the capacitors are collected respectively, a capacitance value matrix is obtained, the central axis of the chip to be detected is determined based on the position of the target element in the capacitance value matrix, and the offset angle of the chip to be detected is determined and output based on the central axis and the preset 0-degree reference line. When chips to be detected with different thicknesses are arranged between the upper electrode plate array and the lower electrode plate array of the capacitor array, capacitance values of capacitors in the capacitor array are changed differently, so that on one hand, the deflection angle reliability of the chips to be detected is determined to be high through a scheme of detecting the capacitance values and performing algorithm processing; on the other hand, after the deflection angle of the chip to be detected is obtained, the chip to be detected is favorably subjected to targeted operation by the chip mounter according to the obtained deflection angle, the use of a limiting device is avoided, and the chip mounting operation efficiency is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
Fig. 1 is a schematic flowchart of an embodiment of a method for detecting chip parameters based on a capacitor array according to the present disclosure;
FIG. 2-a is a schematic structural diagram of a chip placement device to be tested according to the present application;
fig. 2-b is a second schematic structural diagram of a device for placing a chip to be tested according to the present application;
fig. 2-c is a third schematic structural view of a chip placement device to be tested according to the present application;
fig. 3 is a schematic structural diagram of an embodiment of a chip parameter detection device based on a capacitor array according to the present application;
fig. 4 is a schematic structural diagram of an embodiment of a chip parameter detection apparatus provided in the present application.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. However, it will be apparent to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.
It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It is also to be understood that the terminology used in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in the specification of the present application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
The technical solutions in the embodiments of the present application are clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application, but the present application may be practiced in other ways than those described herein, and it will be apparent to those of ordinary skill in the art that the present application is not limited by the specific embodiments disclosed below.
Example one
The application provides a chip parameter detection method based on a capacitor array, wherein the capacitor array comprises the following steps: m by N capacitors, wherein M and N are not less than 2;
as shown in fig. 1, the chip parameter detection method includes:
step 101, placing a chip to be detected between an upper plate array and a lower plate array of the capacitor array, wherein the upper plate array is composed of upper plates of the M × N capacitors, and the lower plate array is composed of lower plates of the M × N capacitors;
in the embodiment of the application, the chip to be detected is placed between the upper plate array and the lower plate array of the capacitor array, so as to change the capacitance value of the capacitor array at the chip to be detected.
Specifically, as shown in fig. 2-a, fig. 2-b, and fig. 2-c, are schematic structural diagrams of the chip placement device to be detected provided by the present application at different angles, and as shown in fig. 2-a, fig. 2-b, and fig. 2-c, the chip placement device to be detected includes: the chip to be detected 201, the capacitor array comprising the upper electrode plate array 2021 and the lower electrode plate array 2022, the mobile platform 203, the driving motor 204 and the transmission lead screw 205;
in practical application, a tester can place the chip 201 to be tested on the movable platform 203, and inputs a moving instruction through a controller connected to the driving motor 204, and the driving motor 204 operates according to the moving instruction to drive the transmission screw 205 to move the movable platform 203 and the chip 201 to be tested placed thereon to a position between the upper electrode plate array 2021 and the lower electrode plate array 2022, thereby completing the step of placing the chip 201 to be tested.
It should be noted that, in the present application, since the capacitor array is used for detecting the chip parameters, the chip 201 to be detected needs to be prevented from being placed on the mobile platform 203 while being attached to the mobile platform, otherwise, the result of detecting the chip parameters may be affected.
Step 102, respectively collecting capacitance values of each capacitor in the M × N capacitors to obtain a capacitance value matrix with the size of M × N, wherein elements in an ith row and a jth column in the capacitance value matrix are capacitance values of capacitors in an ith row and a jth column in the M × N capacitors, i belongs to [1, M ], and j belongs to [1, N ];
in the embodiment of the present application, the capacitance values of the capacitors in the capacitor array are respectively collected, and the capacitance values of the capacitors are arranged according to the positions of the capacitors, so as to obtain the capacitor array.
Taking the chip placement device to be detected shown in fig. 2-a, fig. 2-b, and fig. 2-c as an example for explanation, as can be seen from the upper plate array 2021, the capacitor array is formed by 8 × 8 capacitors, so after the capacitance values of the capacitors in the capacitor array are collected and arranged according to the positions of the capacitors, a digital matrix with the size of 8 × 8 can be obtained, and the digital matrix is a capacitance value matrix.
103, determining the central axis of the chip to be detected based on the position of a target element in the capacitance matrix, wherein the target element is an element with a capacitance value larger than a capacitance threshold value;
in the embodiment of the present application, the element in the capacitance matrix, which is larger than the capacitance threshold, may be determined as a target element, and since the area where the target element is located is the area where the chip to be detected is located, the central axis of the chip to be detected may be determined by performing algorithm processing on the area where the target element is located.
Optionally, binarization processing is performed on elements in the capacitance value matrix. Specifically, the elements greater than 2 in the capacitance matrix may be binarized into 3, and the elements less than or equal to 2 in the capacitance matrix may be binarized into 0.
Optionally, the determining the central axis of the chip to be detected based on the position of the target element in the capacitance matrix includes:
determining the positions of four corner points of the chip to be detected based on the positions of the target elements in the capacitance matrix;
and determining the central axis of the chip to be detected based on the positions of the four corner points.
Further, the determining the positions of the four corner points of the chip to be detected based on the position of the target element in the capacitance matrix specifically includes:
extracting all sub-matrixes of the capacitance matrix by using a preset matrix window, and multiplying each sub-matrix by a preset angular point operator matrix to obtain a Hadamard product matrix, wherein the angular point operator matrix and the matrix window have the same row number and column number;
determining an upper left sub-matrix, an upper right sub-matrix, a lower left sub-matrix and a lower right sub-matrix based on the Hadamard product matrixes and preset angular point matrix characteristic information; wherein, the angular point matrix characteristic information includes: the information comprises upper left corner matrix characteristic information, upper right corner matrix characteristic information, lower left corner matrix characteristic information and lower right corner matrix characteristic information, wherein the upper left corner sub-matrix is a sub-matrix corresponding to a Hadamard product matrix matched with the upper left corner matrix characteristic information, the upper right corner sub-matrix is a sub-matrix corresponding to a Hadamard product matrix matched with the upper right corner matrix characteristic information, and the lower left corner sub-matrix is a sub-matrix corresponding to a Hadamard product matrix matched with the lower left corner matrix characteristic information; the lower left sub-matrix is a sub-matrix corresponding to a Hadamard product matrix matched with the characteristic information of the lower left sub-matrix;
and respectively determining the position of the upper left corner point of the upper left corner sub-matrix, the position of the upper right corner point of the upper right corner sub-matrix, the position of the lower left corner point of the lower left corner sub-matrix and the position of the lower right corner point of the lower right corner sub-matrix as the positions of the four corner points of the chip to be detected.
To better illustrate the above scheme for determining the positions of the four corner points of the chip to be detected based on the positions of the target elements in the capacitance matrix, for example, the following steps are performed:
the capacitance matrix is initially:
Figure BDA0002358011970000121
and (3) carrying out binarization processing on elements in the capacitance matrix: the elements of the capacitance matrix larger than 2 are binarized into 3, and the elements of the capacitance matrix smaller than or equal to 2 are binarized into 0.
The capacitance matrix is binarized as follows:
Figure BDA0002358011970000122
the preset corner operator matrix is as follows:
Figure BDA0002358011970000123
all sub-matrices of the capacitance matrix are extracted in a matrix window of 3 x 3.
Examples are as follows:
Figure BDA0002358011970000131
the Hadamard product matrix after calculating the product of the sub-matrix and the angular point operator matrix is as follows:
Figure BDA0002358011970000132
the above-mentioned all sub-matrices include: an upper left corner sub-matrix, an upper right corner sub-matrix, a lower left corner sub-matrix and a lower right corner sub-matrix;
when the following four sub-matrices are extracted:
submatrix 1:
Figure BDA0002358011970000133
sub-matrix 2:
Figure BDA0002358011970000134
sub-matrix 3:
Figure BDA0002358011970000135
the sub-matrix 4:
Figure BDA0002358011970000136
and multiplying the four seed matrixes with the angular point operator matrix respectively to obtain four Hadamard product matrixes as follows:
hadamard product matrix 1:
Figure BDA0002358011970000141
hadamard product matrix 2:
Figure BDA0002358011970000142
hadamard product matrix 3:
Figure BDA0002358011970000143
hadamard product matrix 4:
Figure BDA0002358011970000144
based on the comparison result of the feature information of the four Hadamard product matrixes and the preset corner matrix feature information, determining that the four Hadamard product matrixes are respectively as follows: an upper left corner sub-matrix, an upper right corner sub-matrix, a lower left corner sub-matrix and a lower right corner sub-matrix;
based on the correspondence between the four hadamard product matrices and the four seed matrices, it is determined that the sub-matrix 1 is an upper left sub-matrix, the sub-matrix 2 is an upper right sub-matrix, the sub-matrix 3 is a lower left sub-matrix, and the sub-matrix 4 is a lower right sub-matrix.
And respectively determining the position of the upper left corner point of the upper left corner sub-matrix, the position of the upper right corner point of the upper right corner sub-matrix, the position of the lower left corner point of the lower left corner sub-matrix and the position of the lower right corner point of the lower right corner sub-matrix as the positions of the four corner points of the chip to be detected.
Further, the determining the positions of the four corner points of the chip to be detected based on the position of the target element in the capacitance matrix specifically includes:
carrying out overall feature recognition on the region where the target element is located in the capacitance matrix;
and determining the positions of the four corner points of the chip to be detected based on the overall feature recognition result.
To better illustrate the scheme of determining the central axis of the chip to be detected based on the positions of the four corner points, the following example is given:
as shown in fig. 2-c, a coordinate system is established with a preset 0-degree reference line 206 as a vertical coordinate;
determining coordinates of the four corner points based on the positions of the four corner points;
respectively substituting the abscissa and the ordinate of the coordinates of the four corner points into x in the following circle center fitting formulaRound (T-shaped)And yRound (T-shaped)The method comprises the following steps:
(xround (T-shaped)-xCenter of circle)2+(yRound (T-shaped)-yCenter of circle)2＝r2
Wherein (x)Center of circle，yCenter of circle) As the center of a circle, (x)Round (T-shaped)，yRound (T-shaped)) Is the coordinate of the point on the circle, r is the radius of the circle;
the center coordinates (x) obtained by calculationCenter of circle，yCenter of circle) The central coordinate of the chip to be detected is obtained;
calculating a midpoint coordinate between the largest vertical coordinate and the second largest vertical coordinate of the four corner coordinates, or calculating a midpoint coordinate between the smallest vertical coordinate and the second smallest vertical coordinate of the four corner coordinates;
and determining a straight line by two points based on the central coordinate and the midpoint coordinate, and determining the central axis of the chip to be detected.
And 104, determining and outputting an offset angle of the chip to be detected based on the central axis and a preset 0-degree reference line, wherein the offset angle is the offset angle of the central axis relative to the 0-degree reference line.
In the embodiment of the present application, as shown in fig. 2-c, since the chip to be detected only generates a small angular offset when being placed, the offset angle of the chip to be detected can be determined and outputted by measuring the acute angle between the central axis and the predetermined 0-degree reference line 206.
Optionally, the chip parameter detection method further includes:
and measuring and calculating the thickness of the chip to be detected based on the relation parameters of the plate area, the capacitance value and the thickness of a target capacitor, wherein the target capacitor is a capacitor corresponding to a target element, and the plate area is the opposite area of an upper plate and a lower plate of the target capacitor.
Specifically, the plate area and the capacitance of the capacitor corresponding to a target element can be substituted into the following formula:
Figure BDA0002358011970000161
dis thick and thick＝ε0d
Where C is capacitance, ε is dielectric constant, S is plate area, k is electrostatic force constant, d is inter-plate distance, ε0As a thickness-related parameter, dIs thick and thickThe thickness of the chip to be detected;
and calculating to obtain the thickness of the chip to be detected.
Specifically, the target element may be an element corresponding to the central coordinate.
It should be noted that the thickness relation parameter is an empirical parameter and is used for corresponding to the distance d between the plates and the thickness d of the chip to be testedIs thick and thickThe relationship between them.
As can be seen from the above, in the chip parameter detection method based on the capacitor array, the chip to be detected is placed between the upper plate array and the lower plate array of the capacitor array, capacitance values of the capacitors are respectively collected to obtain a capacitance value matrix, the central axis of the chip to be detected is determined based on the position of the target element in the capacitance value matrix, and the offset angle of the chip to be detected is determined and output based on the central axis and the preset 0-degree reference line. When chips to be detected with different thicknesses are arranged between the upper electrode plate array and the lower electrode plate array of the capacitor array, capacitance values of capacitors in the capacitor array are changed differently, so that on one hand, the deflection angle reliability of the chips to be detected is determined to be high through a scheme of detecting the capacitance values and performing algorithm processing; on the other hand, after the deflection angle of the chip to be detected is obtained, the chip to be detected is favorably subjected to targeted operation by the chip mounter according to the obtained deflection angle, the use of a limiting device is avoided, and the chip mounting operation efficiency is improved.
Example two
The present application further provides a chip parameter detection device based on a capacitor array, which corresponds to the chip parameter detection method described in the first embodiment above. Fig. 3 shows a chip parameter detection apparatus provided in the second embodiment of the present application. For convenience of explanation, only the portions related to the present embodiment are shown. Unless the present embodiment clearly indicates otherwise, the parts not explicitly described in the present embodiment correspond to the chip parameter detection method of the embodiment.
In an embodiment of the present application, the capacitor array includes: m by N capacitors, wherein M and N are not less than 2;
as shown in fig. 3, the chip parameter detection apparatus 30 includes: a placing unit 301, a collecting unit 302, a first determining unit 303 and a second determining unit 304;
the placing unit 301 is configured to: placing a chip to be detected between an upper plate array and a lower plate array of the capacitor array, wherein the upper plate array is composed of upper plates of the M × N capacitors, and the lower plate array is composed of lower plates of the M × N capacitors;
the acquisition unit 302 is configured to: respectively collecting capacitance values of each capacitor in the M x N capacitors to obtain a capacitance value matrix with the size of M x N, wherein the elements in the ith row and the jth column in the capacitance value matrix are the capacitance values of the capacitors in the ith row and the jth column in the M x N capacitors, i belongs to [1, M ], and j belongs to [1, N ];
the first determining unit 303 is configured to: determining the central axis of the chip to be detected based on the position of a target element in the capacitance matrix, wherein the target element is an element with a capacitance value larger than a capacitance threshold value;
the second determination unit 304 is configured to: and determining and outputting the offset angle of the chip to be detected based on the central axis and a preset 0-degree reference line, wherein the offset angle is the offset angle of the central axis relative to the 0-degree reference line.
Optionally, the first determining unit 303 is specifically configured to:
determining the positions of four corner points of the chip to be detected based on the positions of the target elements in the capacitance matrix;
and determining the central axis of the chip to be detected based on the positions of the four corner points.
Further, the first determining unit 303 is further specifically configured to:
extracting all sub-matrixes of the capacitance matrix by using a preset matrix window, and multiplying each sub-matrix by a preset angular point operator matrix to obtain a Hadamard product matrix, wherein the angular point operator matrix and the matrix window have the same row number and column number;
determining an upper left sub-matrix, an upper right sub-matrix, a lower left sub-matrix and a lower right sub-matrix based on the Hadamard product matrixes and preset angular point matrix characteristic information; wherein, the angular point matrix characteristic information includes: the information comprises upper left corner matrix characteristic information, upper right corner matrix characteristic information, lower left corner matrix characteristic information and lower right corner matrix characteristic information, wherein the upper left corner sub-matrix is a sub-matrix corresponding to a Hadamard product matrix matched with the upper left corner matrix characteristic information, the upper right corner sub-matrix is a sub-matrix corresponding to a Hadamard product matrix matched with the upper right corner matrix characteristic information, and the lower left corner sub-matrix is a sub-matrix corresponding to a Hadamard product matrix matched with the lower left corner matrix characteristic information; the lower left sub-matrix is a sub-matrix corresponding to a Hadamard product matrix matched with the characteristic information of the lower left sub-matrix;
and respectively determining the position of the upper left corner point of the upper left corner sub-matrix, the position of the upper right corner point of the upper right corner sub-matrix, the position of the lower left corner point of the lower left corner sub-matrix and the position of the lower right corner point of the lower right corner sub-matrix as the positions of the four corner points of the chip to be detected.
Further, the first determining unit 303 is further specifically configured to:
carrying out overall feature recognition on the region where the target element is located in the capacitance matrix;
and determining the positions of the four corner points of the chip to be detected based on the overall feature recognition result.
Optionally, the chip parameter detecting device 30 further includes: a thickness measurement unit 305;
the thickness measurement unit 305 is configured to:
and measuring and calculating the thickness of the chip to be detected based on the relation parameters of the plate area, the capacitance value and the thickness of a target capacitor, wherein the target capacitor is a capacitor corresponding to a target element, and the plate area is the opposite area of an upper plate and a lower plate of the target capacitor.
It should be noted that the chip parameter detecting device may be integrated into the chip placing device to be detected shown in fig. 2-a, fig. 2-b and fig. 2-c, or may be a separate device, which is not limited herein.
As can be seen from the above, the chip parameter detection device based on the capacitor array of the present application collects the capacitance values of the capacitors respectively by placing the chip to be detected between the upper plate array and the lower plate array of the capacitor array, obtains a capacitance value matrix, determines the central axis of the chip to be detected based on the position of the target element in the capacitance value matrix, and determines and outputs the offset angle of the chip to be detected based on the central axis and the preset 0-degree reference line. When chips to be detected with different thicknesses are arranged between the upper electrode plate array and the lower electrode plate array of the capacitor array, capacitance values of capacitors in the capacitor array are changed differently, so that on one hand, the deflection angle reliability of the chips to be detected is determined to be high through a scheme of detecting the capacitance values and performing algorithm processing; on the other hand, after the deflection angle of the chip to be detected is obtained, the chip to be detected is favorably subjected to targeted operation by the chip mounter according to the obtained deflection angle, the use of a limiting device is avoided, and the chip mounting operation efficiency is improved.
EXAMPLE III
The present application further provides a chip parameter detection apparatus, as shown in fig. 4, the chip parameter detection apparatus in the embodiment of the present application includes: a memory 401, a processor 402, and a computer program and a capacitive array 403 stored in the memory 401 and executable on the processor 402, wherein: the memory 401 is used for storing software programs and modules, the processor 402 executes various functional applications and data processing by operating the software programs and modules stored in the memory 401, and the capacitor array 403 includes: m is N electric capacity, above-mentioned M and N are not less than 2. The memory 401, processor 402 and capacitor array 403 are connected by a bus 404.
Specifically, the processor 402 implements the following steps by running the above-mentioned computer program stored in the memory 401:
placing a chip to be detected between an upper plate array and a lower plate array of the capacitor array, wherein the upper plate array is composed of upper plates of the M × N capacitors, and the lower plate array is composed of lower plates of the M × N capacitors;
respectively collecting capacitance values of each capacitor in the M x N capacitors to obtain a capacitance value matrix with the size of M x N, wherein the elements in the ith row and the jth column in the capacitance value matrix are the capacitance values of the capacitors in the ith row and the jth column in the M x N capacitors, i belongs to [1, M ], and j belongs to [1, N ];
determining the central axis of the chip to be detected based on the position of a target element in the capacitance matrix, wherein the target element is an element with a capacitance value larger than a capacitance threshold value;
and determining and outputting the offset angle of the chip to be detected based on the central axis and a preset 0-degree reference line, wherein the offset angle is the offset angle of the central axis relative to the 0-degree reference line.
Assuming that the above is the first possible implementation manner, in a second possible implementation manner based on the first possible implementation manner, the determining the central axis of the chip to be detected based on the position of the target element in the capacitance matrix includes:
determining the positions of four corner points of the chip to be detected based on the positions of the target elements in the capacitance matrix;
and determining the central axis of the chip to be detected based on the positions of the four corner points.
In a third possible implementation manner based on the second possible implementation manner, the determining, based on the position of the target element in the capacitance matrix, the positions of the four corner points of the chip to be detected specifically includes:
extracting all sub-matrixes of the capacitance matrix by using a preset matrix window, and multiplying each sub-matrix by a preset angular point operator matrix to obtain a Hadamard product matrix, wherein the angular point operator matrix and the matrix window have the same row number and column number;
determining an upper left sub-matrix, an upper right sub-matrix, a lower left sub-matrix and a lower right sub-matrix based on the Hadamard product matrixes and preset angular point matrix characteristic information; wherein, the angular point matrix characteristic information includes: the information comprises upper left corner matrix characteristic information, upper right corner matrix characteristic information, lower left corner matrix characteristic information and lower right corner matrix characteristic information, wherein the upper left corner sub-matrix is a sub-matrix corresponding to a Hadamard product matrix matched with the upper left corner matrix characteristic information, the upper right corner sub-matrix is a sub-matrix corresponding to a Hadamard product matrix matched with the upper right corner matrix characteristic information, and the lower left corner sub-matrix is a sub-matrix corresponding to a Hadamard product matrix matched with the lower left corner matrix characteristic information; the lower left sub-matrix is a sub-matrix corresponding to a Hadamard product matrix matched with the characteristic information of the lower left sub-matrix;
and respectively determining the position of the upper left corner point of the upper left corner sub-matrix, the position of the upper right corner point of the upper right corner sub-matrix, the position of the lower left corner point of the lower left corner sub-matrix and the position of the lower right corner point of the lower right corner sub-matrix as the positions of the four corner points of the chip to be detected.
In a fourth possible implementation manner based on the second possible implementation manner, the determining, based on the position of the target element in the capacitance matrix, the positions of the four corner points of the chip to be detected specifically includes:
carrying out overall feature recognition on the region where the target element is located in the capacitance matrix;
and determining the positions of the four corner points of the chip to be detected based on the overall feature recognition result.
In a fifth possible implementation manner based on the first, second, third, or fourth possible implementation manner, the thickness of the chip to be detected is measured and calculated based on a plate area, a capacitance value, and a thickness relation parameter of a target capacitor, where the target capacitor is a capacitor corresponding to a target element, and the plate area is a facing area of an upper plate and a lower plate of the target capacitor.
In particular, memory 401 may include both read-only memory and random-access memory, and provides instructions and data to processor 402. Some or all of memory 401 may also include non-volatile random access memory; the processor 402 may be a Central Processing Unit (CPU), and may be other general purpose processors, Digital Signal Processors (DSP), Application Specific Integrated Circuits (ASIC), Field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
It should be noted that the chip parameter detecting device may be integrated into the chip placing device to be detected shown in fig. 2-a, fig. 2-b and fig. 2-c, or may be a separate device, which is not limited herein.
Example four
The present application also provides a computer readable storage medium having stored thereon a computer program which, when executed, may implement the steps provided by the above-described embodiments. Specifically, the computer program includes computer program code, which may be in one of a source code form, an object code form, an executable file or some intermediate form, and is not limited herein; the computer readable storage medium can be any entity or device capable of carrying the computer program code, recording medium, U disk, removable hard disk, magnetic disk, optical disk, computer memory, Read-only memory (ROM), Random Access Memory (RAM), electrical carrier signal, telecommunication signal, and software distribution medium, and is not limited herein. It should be noted that the contents contained in the computer-readable storage medium can be increased or decreased as required by legislation and patent practice in the jurisdiction.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-mentioned division of the functional units and modules is illustrated, and in practical applications, the above-mentioned functions may be distributed as different functional units and modules according to needs, that is, the internal structure of the apparatus may be divided into different functional units or modules to implement all or part of the above-mentioned functions. Each functional unit and module in the embodiments may be integrated in one processing unit, or each unit may exist alone physically, or two or more units are integrated in one unit, and the integrated unit may be implemented in a form of hardware, or in a form of software functional unit. In addition, specific names of the functional units and modules are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working processes of the units and modules in the system may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
It should be noted that, the methods and the details thereof provided by the foregoing embodiments may be combined with the apparatuses and devices provided by the embodiments, which are referred to each other and are not described again.
Those of ordinary skill in the art would appreciate that the elements and algorithm steps of the examples described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus/terminal device and method may be implemented in other ways. For example, the above-described apparatus/device embodiments are merely illustrative, and for example, the division of the above-described modules or units is only one logical functional division, and the actual implementation may be implemented by another division, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed.
The above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.

Claims (10)

1. A chip parameter detection method based on a capacitor array is characterized in that the capacitor array comprises the following steps: m by N capacitors, wherein M and N are not less than 2;
the chip parameter detection method comprises the following steps:
placing a chip to be detected between an upper plate array and a lower plate array of the capacitor array, wherein the upper plate array is formed by upper plates of the M × N capacitors, and the lower plate array is formed by lower plates of the M × N capacitors;
respectively collecting capacitance values of each capacitor in the M x N capacitors to obtain a capacitance value matrix with the size of M x N, wherein elements in the ith row and the jth column in the capacitance value matrix are capacitance values of capacitors in the ith row and the jth column in the M x N capacitors, i belongs to [1, M ], and j belongs to [1, N ];
determining the central axis of the chip to be detected based on the position of a target element in the capacitance value matrix, wherein the target element is an element of which the capacitance value is greater than a capacitance threshold value;
and determining and outputting the offset angle of the chip to be detected based on the central axis and a preset 0-degree reference line, wherein the offset angle is the offset angle of the central axis relative to the 0-degree reference line.
2. The chip parameter detection method according to claim 1, wherein the determining the central axis of the chip to be detected based on the position of the target element in the capacitance matrix comprises:
determining the positions of four corner points of the chip to be detected based on the positions of the target elements in the capacitance matrix;
and determining the central axis of the chip to be detected based on the positions of the four corner points.
3. The chip parameter detection method according to claim 2, wherein the determining the positions of the four corner points of the chip to be detected based on the position of the target element in the capacitance matrix specifically comprises:
extracting all sub-matrixes of the capacitance matrix by using a preset matrix window, and multiplying each sub-matrix by a preset angular point operator matrix to obtain a Hadamard product matrix, wherein the angular point operator matrix and the matrix window have the same row number and column number;
determining an upper left sub-matrix, an upper right sub-matrix, a lower left sub-matrix and a lower right sub-matrix based on the Hadamard product matrixes and preset angular point matrix characteristic information; wherein the corner matrix characteristic information includes: the information processing method comprises the following steps of obtaining upper left corner matrix characteristic information, upper right corner matrix characteristic information, lower left corner matrix characteristic information and lower right corner matrix characteristic information, wherein the upper left corner sub-matrix is a sub-matrix corresponding to a Hadamard product matrix matched with the upper left corner matrix characteristic information, the upper right corner sub-matrix is a sub-matrix corresponding to a Hadamard product matrix matched with the upper right corner matrix characteristic information, and the lower left corner sub-matrix is a sub-matrix corresponding to a Hadamard product matrix matched with the lower left corner matrix characteristic information; the lower left sub-matrix is a sub-matrix corresponding to a Hadamard product matrix matched with the characteristic information of the lower left sub-matrix;
and respectively determining the position of the upper left corner point of the upper left corner sub-matrix, the position of the upper right corner point of the upper right corner sub-matrix, the position of the lower left corner point of the lower left corner sub-matrix and the position of the lower right corner point of the lower right corner sub-matrix as the positions of the four corner points of the chip to be detected.
4. The chip parameter detection method according to claim 2, wherein the determining the positions of the four corner points of the chip to be detected based on the position of the target element in the capacitance matrix specifically comprises:
carrying out overall feature identification on the region where the target element is located in the capacitance value matrix;
and determining the positions of four corner points of the chip to be detected based on the overall feature recognition result.
5. The chip parameter detection method according to any one of claims 1 to 4, further comprising:
and measuring and calculating the thickness of the chip to be detected based on the relation parameters of the plate area, the capacitance value and the thickness of a target capacitor, wherein the target capacitor is a capacitor corresponding to a target element, and the plate area is the opposite area of an upper plate and a lower plate of the target capacitor.
6. A chip parameter detection device based on a capacitor array is characterized in that the capacitor array comprises: m by N capacitors, wherein M and N are not less than 2;
the chip parameter detection device includes:
the chip to be detected is placed between an upper plate array and a lower plate array of the capacitor array, wherein the upper plate array is composed of the upper plates of the M × N capacitors, and the lower plate array is composed of the lower plates of the M × N capacitors;
the acquisition unit is used for respectively acquiring capacitance values of all capacitors in the M x N capacitors to obtain a capacitance value matrix with the size of M x N, wherein elements in the ith row and the jth column in the capacitance value matrix are capacitance values of capacitors in the ith row and the jth column in the M x N capacitors, i belongs to [1, M ], and j belongs to [1, N ];
the first determining unit is used for determining the central axis of the chip to be detected based on the position of a target element in the capacitance value matrix, wherein the target element is an element of which the capacitance value is greater than a capacitance threshold value;
and the second determining unit is used for determining and outputting the offset angle of the chip to be detected based on the central axis and a preset 0-degree reference line, wherein the offset angle is the offset angle of the central axis relative to the 0-degree reference line.
7. The chip parameter detection device according to claim 6, wherein the first determination unit is specifically configured to:
determining the positions of four corner points of the chip to be detected based on the positions of the target elements in the capacitance matrix;
and determining the central axis of the chip to be detected based on the positions of the four corner points.
8. The chip parameter detection device according to claim 7, wherein the first determination unit is further specifically configured to:
extracting all sub-matrixes of the capacitance matrix by using a preset matrix window, and multiplying each sub-matrix by a preset angular point operator matrix to obtain a Hadamard product matrix, wherein the angular point operator matrix and the matrix window have the same row number and column number;
determining an upper left sub-matrix, an upper right sub-matrix, a lower left sub-matrix and a lower right sub-matrix based on the Hadamard product matrixes and preset angular point matrix characteristic information; wherein the corner matrix characteristic information includes: the information processing method comprises the following steps of obtaining upper left corner matrix characteristic information, upper right corner matrix characteristic information, lower left corner matrix characteristic information and lower right corner matrix characteristic information, wherein the upper left corner sub-matrix is a sub-matrix corresponding to a Hadamard product matrix matched with the upper left corner matrix characteristic information, the upper right corner sub-matrix is a sub-matrix corresponding to a Hadamard product matrix matched with the upper right corner matrix characteristic information, and the lower left corner sub-matrix is a sub-matrix corresponding to a Hadamard product matrix matched with the lower left corner matrix characteristic information; the lower left sub-matrix is a sub-matrix corresponding to a Hadamard product matrix matched with the characteristic information of the lower left sub-matrix;
and respectively determining the position of the upper left corner point of the upper left corner sub-matrix, the position of the upper right corner point of the upper right corner sub-matrix, the position of the lower left corner point of the lower left corner sub-matrix and the position of the lower right corner point of the lower right corner sub-matrix as the positions of the four corner points of the chip to be detected.
9. A chip parameter detection apparatus comprising a memory, a processor, and a capacitor array, the memory storing a computer program, the capacitor array comprising: m by N capacitors, wherein M and N are not less than 2;
the processor, when executing the computer program, realizes the steps of the method of any one of claims 1 to 5.
10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 5.
CN202010013541.3A 2020-01-07 2020-01-07 Chip parameter detection method and device based on capacitor array Pending CN111207659A (en)

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