CN111199872B - Forming method of wafer edge protection layer, three-dimensional memory and manufacturing method thereof - Google Patents
Forming method of wafer edge protection layer, three-dimensional memory and manufacturing method thereof Download PDFInfo
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
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- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
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- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
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- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
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- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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Abstract
The embodiment of the invention discloses a method for forming a wafer edge protection layer, a method for preparing a three-dimensional memory and the three-dimensional memory; the method for forming the wafer edge protection layer comprises the following steps: providing a wafer; forming an intermediate protection layer at the wafer edge, the intermediate protection layer being generated by a chemical reaction of a first process gas with the exposed wafer material; and forming a main protection layer on the intermediate protection layer.
Description
Technical Field
The present invention relates to the field of semiconductor technologies, and in particular, to a method for forming a wafer edge protection layer, a method for manufacturing a three-dimensional memory, and a three-dimensional memory.
Background
In the field of semiconductor technology, a Wafer edge (Wafer edge) has a special position and a special bevel shape, and when a deposition process or an etching process is performed on a Wafer, the situation of the edge region is often complex. In order to avoid damage to the wafer due to exposure of the edge, it is generally necessary to form a protective layer on the edge.
However, since the edge needs to be in contact with the wafer support, and the exposed edge may have undergone some other etching process; therefore, the crystal edge is often damaged to some extent before the protective layer is formed, thereby having a non-smooth surface. At this time, the formation of the protective layer on the crystal edge is likely to cause problems such as poor adhesion, fracture and peeling, and the like, and an effective crystal edge protection effect is difficult to be achieved, which seriously affects the subsequent process.
Disclosure of Invention
In view of the above, an embodiment of the present invention provides a method for forming a wafer edge protection layer, a method for manufacturing a three-dimensional memory, and a three-dimensional memory for solving at least one of the problems in the background art.
In order to achieve the above purpose, the technical scheme of the invention is realized as follows:
the embodiment of the invention provides a method for forming a wafer edge protection layer, which comprises the following steps:
providing a wafer;
forming an intermediate protection layer at the wafer edge, the intermediate protection layer being generated by a chemical reaction of a first process gas with the exposed wafer material;
and forming a main protection layer on the intermediate protection layer.
In the above aspect, the first process gas includes an oxygen-containing gas and/or a nitrogen-containing gas.
In the above aspect, the first process gas includes at least one of: n (N) 2 O、NH 3 、O 2 。
In the above aspect, the forming an intermediate protection layer includes:
the first process gas is ionized to form a plasma state, and the intermediate protection layer is generated through chemical reaction of the first process gas in the plasma state and the exposed wafer material.
In the above aspect, the forming a main protection layer includes:
generating the main protection layer by chemical reaction of the second process gas and the third process gas; the second process gas comprises an oxygen-containing gas and/or a nitrogen-containing gas; the third process gas comprises a silicon-containing gas.
In the above scheme, the material of the intermediate protection layer is the same as that of the main protection layer.
The embodiment of the invention also provides a preparation method of the three-dimensional memory, which comprises the following steps:
providing a stacked structure, wherein the stacked structure at least comprises a first stacked structure formed on a wafer and a second stacked structure formed on the first stacked structure; the first laminated structure is provided with a first channel through hole, and a sacrificial layer is filled in the first channel through hole; a second channel through hole is formed in the second laminated structure, and the sacrificial layer in the first channel through hole is exposed by the second channel through hole;
the method for forming the wafer edge protection layer according to any one of the above schemes is adopted to form an intermediate protection layer and a main protection layer at the wafer edge;
and removing the sacrificial layer in the first channel through hole.
The embodiment of the invention also provides a three-dimensional memory, which comprises: a semiconductor substrate and a memory device layer on the upper surface of the semiconductor substrate; wherein,,
the edge of the semiconductor substrate further comprises an intermediate protection layer, wherein the intermediate protection layer is generated by the chemical reaction of the first process gas and the semiconductor substrate;
a main protective layer is also included on the intermediate protective layer.
In the above aspect, the first process gas includes an oxygen-containing gas and/or a nitrogen-containing gas.
In the above aspect, the first process gas includes at least one of: n (N) 2 O、NH 3 、O 2 。
In the above scheme, the material of the intermediate protection layer is the same as that of the main protection layer.
The embodiment of the invention provides a method for forming a wafer edge protection layer, a method for preparing a three-dimensional memory and the three-dimensional memory; the method for forming the wafer edge protection layer comprises the following steps: providing a wafer; forming an intermediate protection layer at the wafer edge, the intermediate protection layer being generated by a chemical reaction of a first process gas with the exposed wafer material; and forming a main protection layer on the intermediate protection layer. In this way, the first process gas and the exposed wafer material are subjected to chemical reaction to generate the intermediate protection layer, so that the surface morphology of the wafer edge is improved, the wafer adhesion is increased, better conditions are provided for the formation of the subsequent main protection layer, and the problem of fracture and stripping of the main protection layer is effectively prevented; the intermediate protection layer also has the function of protecting the wafer, and further prevents the edge of the wafer from being damaged in the etching process.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
FIG. 1 is a schematic cross-sectional view of a structure in which a passivation layer is directly formed on the edge of a wafer;
FIGS. 2 a-2 b are electron microscope views of the structure surface of FIG. 1 after forming a protective layer;
FIG. 3 is a flowchart illustrating a method for forming a passivation layer on a wafer edge according to an embodiment of the present invention;
FIG. 4 is a schematic cross-sectional view of a structure in a method for forming a passivation layer on a wafer edge according to an embodiment of the present invention;
FIG. 5 is a schematic flow chart of a method for manufacturing a three-dimensional memory according to an embodiment of the present invention;
fig. 6 is a schematic structural cross-section of a three-dimensional memory in the manufacturing process according to an embodiment of the present invention.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the invention may be practiced without one or more of these details. In other instances, well-known features have not been described in detail so as not to obscure the invention; that is, not all features of an actual implementation are described in detail herein, and well-known functions and constructions are not described in detail.
In the drawings, the size of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like numbers refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on" … …, "" adjacent to "… …," "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected to or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on" … …, "" directly adjacent to "… …," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention. When a second element, component, region, layer or section is discussed, it does not necessarily mean that the first element, component, region, layer or section is present.
Spatially relative terms, such as "under … …," "under … …," "below," "under … …," "above … …," "above," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "under … …" and "under … …" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
In order to provide a thorough understanding of the present invention, detailed steps and detailed structures will be presented in the following description in order to explain the technical solution of the present invention. Preferred embodiments of the present invention are described in detail below, however, the present invention may have other embodiments in addition to these detailed descriptions.
FIG. 1 is a schematic cross-sectional view of a structure in which a passivation layer is directly formed on the edge of a wafer. As shown, the edges of the crystal are already damaged to some extent before the protective layer is formed, the surface is not smooth, and there are several damage points. In this case, the protective layer is directly formed on the wafer edge, and the protective layer cannot be well attached to the wafer surface, so that the problems of fracture, peeling and the like are likely to occur.
Fig. 2a to 2b are electron microscope views of the structure surface after the protective layer is formed in fig. 1. FIG. 2a shows a defect of peeling of a protective layer on a wafer surface; figure 2b shows a defect in which the protective layer on the wafer surface breaks.
It can be understood that after the protective layer is broken and stripped, the edge of the wafer is exposed again, so that effective protection cannot be obtained, and the damage is serious in the subsequent process, so that the yield of the device is directly affected.
Based on the above, the embodiment of the invention provides a method for forming a wafer edge protection layer; please refer to fig. 3 in detail. As shown, the method includes:
and 303, forming a main protective layer on the intermediate protective layer.
It can be appreciated that in the embodiment of the invention, the first process gas is firstly adopted to react with the exposed wafer material to generate the intermediate protection layer, so that the surface morphology of the wafer edge is improved, the wafer adhesiveness is increased, better conditions are provided for the subsequent formation of the main protection layer, and the problem of fracture and stripping of the protection layer is effectively prevented; the intermediate protection layer also has the function of protecting the wafer, and further prevents the edge of the wafer from being damaged in the etching process.
Next, a method for forming a wafer edge protection layer according to an embodiment of the present invention is described in further detail with reference to a schematic structural cross-section in the method for forming a wafer edge protection layer in fig. 4.
Here, the wafer refers to a wafer in a broad range used for manufacturing a semiconductor integrated circuit, and includes, for example: silicon (Si) wafers, germanium (Ge) wafers, and the like.
The forming of the intermediate protection layer includes: the first process gas is ionized to form a plasma state, and the intermediate protection layer is generated through chemical reaction of the first process gas in the plasma state and the exposed wafer material. The forming of the intermediate protection layer may be performed in particular by a plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD) process. Introducing a first process gas into the PECVD reaction chamber, wherein the first process gas comprises oxygen-containing gas and/or nitrogen-containing gas; the first process gas is locally formed into a plasma state by means of microwaves or radio frequency and the like, so that chemical reaction is carried out between the first process gas and a wafer material by utilizing the chemical activity of the plasma state, plasma soaking (Surface Plasma Soak, SPS) is realized on the surface of the wafer, a surface film layer is formed, the surface morphology of the edge of the wafer is improved, and the wafer has better adhesiveness. The surface film layer formed by plasma immersion is an intermediate protective layer in the embodiments of the present application, and may also be referred to as a surface plasma immersion layer, or an interface layer, or a buffer layer.
In other embodiments, the forming the intermediate protection layer may also include: the intermediate protection layer is generated by heating the first process gas to chemically react the first process gas with the exposed wafer material.
The main protective layer is used as a film layer structure formed on the surface of the substrate in a complete deposition mode, and reactants are provided in the forming process; in other words, the reactants that produce the primary protective layer are entirely fed into the reaction chamber by external supply; in the process of generating the intermediate protection layer, only part of the reaction source (namely, the first process gas) is introduced into the reaction chamber, and the part of the reaction source can chemically react with the exposed wafer material to form a film structure on the surface of the edge of the wafer.
When the wafer is a silicon wafer, the first process gas is a gas that does not contain silicon.
Here, the first process gas is not limited to a single process gas, but is limited to a type of gas that chemically reacts with the wafer material; for example, the first process gas may be a mixed gas, but the mixed gas cannot react with the wafer material to generate the intermediate protection layer, and it should be understood that this case is also within the scope of protection of the present application. When the intermediate protection layer is formed, the first process gas is not limited to be introduced only; in practical application, a stabilizing gas, for example, nitrogen, may be introduced, so as to serve as a filling gas to stabilize the pressure.
In a specific embodiment, the first process gas comprises at least one of: n (N) 2 O、NH 3 、O 2 . Thus, the intermediate protective layer formed may include a semiconductor oxide, a semiconductor nitride, or the like; specifically, for example, siO 2 Or SiN.
Next, a main protective layer is formed on the intermediate protective layer. It will be appreciated that the thickness of the main protective layer is generally greater than the thickness of the intermediate protective layer.
The main protective layer may be generated by a chemical reaction of two or more process gases; in one embodiment, the forming the main protection layer includes: generating the main protection layer by chemical reaction of the second process gas and the third process gas; the second process gas comprises an oxygen-containing gas and/or a nitrogen-containing gas; the third process gas comprises a silicon-containing gas. Thus, the material of the protective layer may also comprise SiO 2 Or SiN.
The material of the main protective layer may be the same as the material of the intermediate protective layer. In other embodiments, the material of the main protective layer may also be different from the material of the intermediate protective layer.
Thus, in the embodiments of the present application, the formation of the wafer edge protection layer is actually accomplished through a two-step deposition process; by adding the forming process (such as surface plasma soaking process) of the intermediate protection layer, the surface state of the wafer is improved before the deposition of the main protection layer, the subsequent formation of the main protection layer is facilitated, and the problem of fracture and stripping of the protection layer caused by the uneven surface of the wafer is avoided.
On the basis, the embodiment of the invention also provides a preparation method of the three-dimensional memory; please refer to fig. 5 in detail. As shown, the method includes:
step 501, providing a stacked structure, wherein the stacked structure at least comprises a first stacked structure formed on a wafer and a second stacked structure formed on the first stacked structure;
the first laminated structure is provided with a first channel through hole, and a sacrificial layer is filled in the first channel through hole; a second channel through hole is formed in the second laminated structure, and the sacrificial layer in the first channel through hole is exposed by the second channel through hole;
the method for forming the wafer edge protection layer is any one of the methods in the above embodiments;
The method for manufacturing the three-dimensional memory according to the embodiment of the present invention is described in further detail below with reference to a schematic structural cross-section of the three-dimensional memory in fig. 6 during the manufacturing process.
As shown in fig. 6, the three-dimensional memory has a stacked structure, for example, a dual stacked structure. The stacked structure is used for better forming a Channel Hole (CH) with a large number of layers penetrating through the stacked layer and high aspect ratio. Specifically, the first channel via CH1 (lower CH) is completed, then the second stacked structure (upper stacked layer) is deposited and etched to form the second channel via CH2 (upper CH), so that the upper and lower CH together form CH.
Here, the three-dimensional memory is, for example, a 3D NAND memory.
The first stacked structure 61 includes a plurality of first material layers 611 and second material layers 612 alternately stacked. The first material layer 611 may be a dielectric layer, and its material includes, but is not limited to, dielectric materials such as silicon oxide, silicon nitride layer, silicon oxynitride, etc.; in one embodiment, the first material layer 611 is a silicon dioxide layer. The second material layer 612 may be a sacrificial layer, or dummy gate layer, of a material including, but not limited to, silicon nitride; in a subsequent process, the sacrificial layer is removed, and gate metal is filled in the position of the second material layer 612 to form a gate layer. In an embodiment, the material of the first material layer 611 is silicon oxide (SiO 2 ) The material of the second material layer 612 is silicon nitride (SiN), so that the first stacked layer 61 is formed as an NO stacked layer.
The first stacked structure 61 is etched to form a first channel via CH1.
Specifically, the first trench via CH1 may be formed in the first stacked structure 61 using a dry etching process.
In order to prevent collapse of the subsequently formed second stacked structure 62 at the position of CH1, it is necessary to fill the sacrificial layer 63 in CH1.
The sacrificial layer 63 is, for example, a sacrificial layer of semiconductor material; in one embodiment, the material of the sacrificial layer 63 includes polysilicon.
In a specific application, a step of forming a selective epitaxial layer SEG on the wafer 60 at the bottom of CH1 may also be included before filling the sacrificial layer 63.
Next, a second stacked structure 62 is formed on the first stacked structure 61.
The structure and material of the second laminated structure 62 may be the same as those of the first laminated structure 61. That is, the second stacked structure 62 may also include a plurality of third material layers 621 and fourth material layers 622 alternately stacked. The third material layer 621 may be a dielectric layer, and the material thereof includes, but is not limited to, dielectric materials such as silicon oxide, silicon nitride layer, silicon oxynitride, etc.; in one embodiment, the third material layer 621 is a silicon dioxide layer. The fourth material layer 622 may be a sacrificial layer, or a dummy gate layer, and its material includes, but is not limited to, silicon nitride; in the subsequent process, the sacrificial layer is removed, and the gate metal is filled in the position of the fourth material layer 622, so as to form a gate layer. In an embodiment, the material of the third material layer 621 is silicon oxide (SiO 2 ) The fourth material layer 622 is made of silicon nitride (SiN), so that the second stacked structure 62 is formed as an NO stacked layer.
Next, the second stacked structure 62 is etched to form a second channel via CH2 communicating with the first channel via CH1. The second channel via CH2 exposes the sacrificial layer 63 within the first channel via CH1.
The etching of the second stacked structure 62 may also be performed using a dry etching process.
Next, in order to form a trench through-hole penetrating the second stacked structure 62 and the first stacked structure 61, the sacrificial layer 63 needs to be removed.
To remove the sacrificial layer 63, a tetramethylammonium hydroxide (TMAH) process is generally required. TMAH has a low selectivity to polysilicon and also causes damage to the wafer material, so in order to protect the exposed wafer material at the wafer edge, a protective layer needs to be coated on the wafer edge to prevent serious damage to the wafer edge during the removal process of the sacrificial layer 63.
In the embodiment of the present invention, the intermediate protection layer 64 and the main protection layer 65 are formed at the wafer edge by using the method described in any one of the embodiments of the method for forming a wafer edge protection layer. Thus, the formed main protective layer has lower risk of fracture peeling; the intermediate protection layer also has the function of protecting the wafer, and further prevents the edge of the wafer from being damaged in the etching process.
Then, a step of removing the sacrificial layer 63 in the first trench via CH1 is performed again.
In addition, the embodiment of the invention also provides a three-dimensional memory.
The three-dimensional memory includes: a semiconductor substrate and a memory device layer on the upper surface of the semiconductor substrate; wherein,,
the edge of the semiconductor substrate further comprises an intermediate protection layer, wherein the intermediate protection layer is generated by the chemical reaction of the first process gas and the semiconductor substrate;
a main protective layer is also included on the intermediate protective layer.
It can be appreciated that the three-dimensional memory provided in this embodiment may be prepared by an embodiment of the method for preparing a three-dimensional memory described above.
The semiconductor substrate corresponds to a wafer after the preparation of the three-dimensional memory is completed; it will be appreciated that after the fabrication of the three-dimensional memory is completed, the devices formed on the wafer are typically singulated by a dicing process into individual chips (chips), and the semiconductor substrate in each individual Chip is the wafer employed in the fabrication process.
The first process gas may include an oxygen-containing gas and/or a nitrogen-containing gas.
In a specific embodiment, the first process gas comprises at least one of: n (N) 2 O、NH 3 、O 2 。
In a preferred embodiment, the material of the main protection layer is the same as the material of the intermediate protection layer.
The storage device layer refers to a part having an information storage function in a three-dimensional memory and a part assisting in performing information storage.
The storage device layer includes, for example: a stacked structure (the sacrificial layer in the first stacked structure and the second stacked structure has been replaced with a gate layer) formed over the semiconductor substrate, a channel structure (a structure of a barrier layer, a memory layer, a tunneling layer, a channel layer, and the like formed in a channel via hole) penetrating the stacked structure, and an array common source and the like; and not described here.
It should be noted that, the embodiment of the method for forming the wafer edge protection layer, the embodiment of the three-dimensional memory and the embodiment of the method for preparing the three-dimensional memory provided by the invention belong to the same conception; the features of the embodiments described in the present invention may be combined arbitrarily without any conflict. However, it should be further explained that the three-dimensional memory provided by the embodiment of the present invention has various technical feature combinations that can solve the technical problems to be solved by the present invention; therefore, the three-dimensional memory provided by the embodiment of the invention is not limited by the preparation method of the three-dimensional memory provided by the embodiment of the invention, and any three-dimensional memory prepared by the preparation method capable of forming the three-dimensional memory structure provided by the embodiment of the invention is within the protection scope of the invention.
The above description is not intended to limit the scope of the invention, but is intended to cover any modifications, equivalents, and improvements within the spirit and principles of the invention.
Claims (10)
1. A method for forming a wafer edge protection layer, the method comprising:
providing a wafer;
forming an intermediate protection layer at the wafer edge, the intermediate protection layer being generated by a chemical reaction of a first process gas with the exposed wafer material;
forming a main protection layer on the intermediate protection layer;
the forming an intermediate protection layer includes:
the first process gas is ionized to form a plasma state, and the intermediate protection layer is generated through chemical reaction of the first process gas in the plasma state and the exposed wafer material.
2. The method of claim 1, wherein the first process gas comprises an oxygen-containing gas and/or a nitrogen-containing gas.
3. The method of claim 2, wherein the first process gas comprises at least one of: n (N) 2 O、NH 3 、O 2 。
4. The method of claim 1, wherein forming the main protective layer comprises:
generating the main protection layer by chemical reaction of the second process gas and the third process gas; the second process gas comprises an oxygen-containing gas and/or a nitrogen-containing gas; the third process gas comprises a silicon-containing gas.
5. The method of claim 1, wherein the material of the intermediate protective layer is the same as the material of the main protective layer.
6. A method for preparing a three-dimensional memory, the method comprising:
providing a stacked structure, wherein the stacked structure at least comprises a first stacked structure formed on a wafer and a second stacked structure formed on the first stacked structure; the first laminated structure is provided with a first channel through hole, and a sacrificial layer is filled in the first channel through hole; a second channel through hole is formed in the second laminated structure, and the sacrificial layer in the first channel through hole is exposed by the second channel through hole;
forming an intermediate protective layer and a main protective layer at the wafer edge using the method for forming a wafer edge protective layer as claimed in any one of claims 1 to 5;
and removing the sacrificial layer in the first channel through hole.
7. A three-dimensional memory, comprising: a semiconductor substrate and a memory device layer on the upper surface of the semiconductor substrate; wherein,,
the edge of the semiconductor substrate further comprises an intermediate protection layer, wherein the intermediate protection layer is generated by the chemical reaction of the first process gas and the semiconductor substrate;
the intermediate protective layer also comprises a main protective layer;
wherein the intermediate protective layer and the main protective layer are formed by the method for forming a wafer edge protective layer according to any one of claims 1 to 6.
8. The three-dimensional memory according to claim 7, characterized in that the first process gas comprises an oxygen-containing gas and/or a nitrogen-containing gas.
9. The three-dimensional memory of claim 8, wherein the first process gas comprises at least one of: n (N) 2 O、NH 3 、O 2 。
10. The three-dimensional memory of claim 8, wherein the material of the intermediate protective layer is the same as the material of the main protective layer.
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