CN111199697B - Display device and display method for reducing dynamic blurring - Google Patents
Display device and display method for reducing dynamic blurring Download PDFInfo
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- CN111199697B CN111199697B CN201811367631.1A CN201811367631A CN111199697B CN 111199697 B CN111199697 B CN 111199697B CN 201811367631 A CN201811367631 A CN 201811367631A CN 111199697 B CN111199697 B CN 111199697B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/3406—Control of illumination source
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/001—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes using specific devices not provided for in groups G09G3/02 - G09G3/36, e.g. using an intermediate record carrier such as a film slide; Projection systems; Display of non-alphanumerical information, solely or in combination with alphanumerical information, e.g. digital display on projected diapositive as background
- G09G3/003—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes using specific devices not provided for in groups G09G3/02 - G09G3/36, e.g. using an intermediate record carrier such as a film slide; Projection systems; Display of non-alphanumerical information, solely or in combination with alphanumerical information, e.g. digital display on projected diapositive as background to produce spatial visual effects
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/08—Details of timing specific for flat panels, other than clock recovery
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/06—Adjustment of display parameters
- G09G2320/0626—Adjustment of display parameters for control of overall brightness
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/02—Details of power systems and of start or stop of display operation
- G09G2330/026—Arrangements or methods related to booting a display
Abstract
A display device and display method for reducing dynamic blur, the display device includes: the device comprises a liquid crystal display panel, a driving module, a backlight module and a processing module. The processing module receives the input display data to generate output display data, so that the output display data has an output picture data section and a redundant output picture data section for data transmission with an output pixel clock higher than the input pixel clock within a picture time of the same length as the input display data, and drives the liquid crystal display panel to generate a display picture according to the output display data. The processing module controls the backlight module to be started only in the redundant output picture data interval, and the liquid crystal display panel is started after the liquid crystal display panel responds to the output picture data corresponding to the output picture data interval.
Description
Technical Field
The present invention relates to display technology, and more particularly, to a display device and a display method for reducing motion blur.
Background
A common lcd is implemented as a hold-type display (hold-type display) with a screen updated every 16.67 milliseconds (millisecond) for 60 updates per second (60 hz). The currently displayed picture is still until the new picture is updated. However, when the eyes of the user track the object in the picture, the eyes have expected positions according to the moving speed of the object. However, because of the discontinuity in the update time of the lcd, the actual position of the object on the screen will be in error with the expected position of the brain of the user. The persistence of vision and the dynamic compensation mechanism of human eyes can lead the brain to continue the process of tracking objects with the effect similar to integration, thereby causing motion blur.
Therefore, how to design a new display device and display method for reducing motion blur to solve the above-mentioned drawbacks is a problem to be solved in the industry.
Disclosure of Invention
An object of the present invention is to provide a display device for reducing motion blur, comprising: the device comprises a liquid crystal display panel, a driving module, a backlight module and a processing module. The driving module is electrically coupled to the liquid crystal display panel. The backlight module is configured to generate backlight to the liquid crystal display panel. The processing module is electrically coupled to the backlight module and the driving module and configured to receive input display data, wherein the input display data has an input frame data section for data transmission with an input pixel clock (pixel clock) and an input blank section after the input frame data section in a frame time between two adjacent input vertical synchronization (vertical sync signals; vsync) signals. The processing module is configured to generate output display data according to the input display data, so that the output display data has an output picture data section for data transmission with an output pixel clock greater than the input pixel clock and a redundant output picture data section after the output picture data section within a picture time of the same length, and drive the liquid crystal display panel to generate a display picture according to the output display data through the driving module. The processing module is further configured to control the backlight module to start only in the redundant output frame data section after the liquid crystal display panel has reacted with the output frame data corresponding to the output frame data section.
Another objective of the present invention is to provide a display method for reducing motion blur, which is applied to a display device, wherein the display device includes a liquid crystal display panel, a driving module electrically coupled to the liquid crystal display panel, a backlight module configured to generate backlight to the liquid crystal display panel, and a processing module electrically coupled to the backlight module and the driving module, and the display method includes: the processing module receives input display data, wherein the input display data has an input picture data section for data transmission by using input pixel clock and an input blank section after the input picture data section in the picture time between two adjacent input vertical synchronous signals; the processing module generates output display data according to the input display data, so that the output display data has an output picture data section for data transmission with an output pixel clock greater than the input pixel clock and a redundant output picture data section after the output picture data section in the picture time with the same length; the processing module drives the liquid crystal display panel to generate a display picture through the driving module according to the output display data; and enabling the processing module to control the backlight module to be started only in the redundant output picture data interval after the liquid crystal display panel responds to the output picture data corresponding to the output picture data interval.
The display device has the advantages that the display device can transmit picture data to the liquid crystal display panel in a shorter time by lifting the output pixel clock, so that the display unit has enough reaction time to start the backlight module, the problem of insufficient reaction time of the liquid crystal display panel is solved, and the effect of relatively consistent vertical direction is achieved in the reduction of the improvement range of the dynamic blurring.
Drawings
FIG. 1 is a block diagram of a display device for reducing motion blur according to an embodiment of the invention;
FIG. 2 is a timing diagram of inputting display data and outputting display data according to an embodiment of the present invention;
FIG. 3 is a timing diagram of inputting display data and outputting display data according to another embodiment of the present invention;
FIG. 4 is a flowchart of a display method for reducing motion blur according to an embodiment of the invention;
FIG. 5A is a schematic diagram of a backlight module according to an embodiment of the invention;
FIG. 5B is a schematic diagram of a liquid crystal display panel according to an embodiment of the invention;
FIG. 5C is a timing diagram of the input display data, the output display data and the backlight module switch according to an embodiment of the invention; and
FIG. 6 is a flowchart of a display method for reducing motion blur according to an embodiment of the invention.
[ symbolic description ]
1: display device
100: liquid crystal display panel having a light shielding layer
101: backlight unit
102: driving module
103: inputting display data
104: backlight module
105: output display data
106: processing module
108: storage unit
200. 300, 500: input picture data section
201: first part
202. 302, 502: inputting blank space
203: second part
204. 304, 504A to 504D: output frame data interval
206. 506: output blank interval
306: redundant output frame data interval
208. 308: interval of
400: display method
401 to 404: step (a)
600: display method
601 to 602: step (a)
BZ1 to BZ4: backlight assembly section
PZ1 to PZ4: panel area
TD: preset time
TFI, TFO: time of picture
Vsync_in: inputting vertical synchronous signals
Vsync_out: outputting vertical synchronous signals
Detailed Description
Please refer to fig. 1 at the same time. Fig. 1 is a block diagram of a display device 1 for reducing motion blur according to an embodiment of the invention. The display device 1 includes: the display device comprises a liquid crystal display panel 100, a driving module 102, a backlight module 104 and a processing module 106.
In one embodiment, the lcd panel 100 includes a plurality of display units (not shown) arranged in an array.
The driving module 102 is electrically coupled to the liquid crystal display panel 100. In one embodiment, the driving module 102 includes a gate driver and a source driver (not shown). The gate driver is connected to the gates of the transistors in one row of display units of the LCD panel, and is responsible for switching on and off the transistors in each row, and turning on the transistors in one row at a time during scanning. When the transistor is turned on, the source driver can enter the control voltage for controlling brightness, gray scale and color into the pixels of the display unit line by line through the channel formed by the source and drain of the transistor.
The backlight module 104 is configured to generate backlight 101 to the liquid crystal display panel 100 to illuminate the panel, so that a user can watch a display screen displayed on the liquid crystal display panel 100.
In one embodiment, the processing module 106 is a scaler (scaler) or a timing controller (timing controller), which is not a limitation of the present invention. The processing module 106 is electrically coupled to the backlight module 104 and the driving module 102, and is configured to receive the input display data 103 and generate output display data 105 according to the input display data 103. The processing module 106 can drive the liquid crystal display panel 100 to generate a display screen through the driving module 102 according to the output display data 105. Further, the processing module 106 can match with the output display data 105 to control the backlight module 104 to generate the backlight 101 to illuminate the liquid crystal display panel 100, so as to achieve the purpose of providing the display screen for the user to watch.
The generation mechanism of the output display data 105 by the processing module 106 and the control mechanism of the backlight module 104 will be described in more detail below.
Please refer to fig. 2. FIG. 2 is a timing diagram of input display data 103 and output display data 105 according to one embodiment of the present invention.
As shown in fig. 2, the input display data 103 has a plurality of input vertical synchronization signals vsync_in, and each two adjacent input vertical synchronization signals vsync_in will correspond to data containing one display frame.
The input display data 103 has an input frame data section 200 for data transfer with an input pixel clock (pixel clock) and an input blank section 202 following the input frame data section 200 within a frame time TFI between two adjacent input vertical synchronization signals vsync_in.
In one embodiment, the input frame data section 200 is used to transmit actual frame data, while the input blank section 202 is used to transmit no frame data. In one embodiment, the input frame data interval 200 is used to transmit frame data at the input pixel clock. Taking a frame update rate of 2000×1127 (frame size 1920×1080) and 90 hz for example, the amount of frame data in the horizontal and vertical directions, the input pixel clock will be 2000×1127×90=202.86 megahertz (MHz). While the length of the input blank interval 202 is approximately 0.46 milliseconds.
Similarly, the output display data 105 has a plurality of output vertical synchronization signals vsync_out, and each two adjacent output vertical synchronization signals vsync_out correspond to data containing one display frame. In the present embodiment, the time length of the frame time TFO between two adjacent output vertical synchronization signals vsync_out is the same as the time length of the frame time TFI.
The output display data 105 has an output frame data section 204 for data transfer at an output pixel clock greater than the input pixel clock and an output blank section 206 following the output frame data section 204 within the frame time TFO.
Similarly, the output frame data segments 204 are used to transmit actual frame data, while the output blank segments 206 are used to transmit no frame data. Since the output pixel clock is greater than the input pixel clock, the output frame data section 204 will be able to transmit the corresponding frame data amount of the input frame data section 200 in a shorter time. In contrast, the output blank interval 206 will thus be longer than the input blank interval 202.
Taking the example of output pixel clock up to 596.88 mhz, a frame data amount of 2000 x 3316 (2000 x 3316 x 90= 596.88 mhz) in the horizontal and vertical directions can be transferred while the frame refresh rate remains the same at 90 hz. However, since the frame size is still 1920×1080, the output frame interval 204 can be significantly reduced by about 1/3 times the input frame interval 200. In contrast, the length of the output blank interval 206 may be elongated to about 7.49 milliseconds.
In one embodiment, the frame time TFO in the output display data 105 is delayed by a predetermined time TD from the corresponding frame time TFI in the input display data 103 so that the frame data is not lost. In other words, the output vertical synchronization signal vsync_out corresponding to each frame time TFO is delayed by the preset time TD from the input vertical synchronization signal vsync_in corresponding to the frame time TFI.
At this time, the input frame data corresponding to the input frame data section 200 includes a first portion 201 and a second portion 203. The processing module 106 temporarily stores the first portion 201 by the included storage unit 108, so as to access the storage unit 108 to output the first portion 201 and directly output the second portion 203 in the output frame data interval 204 as output frame data.
Therefore, the processing module 106 is further configured to control the backlight module 104 to turn on only in the output blank interval 206 after the liquid crystal display panel 100 has reacted to the output frame data corresponding to the output frame data interval 204. In fig. 2, the time for turning on the backlight module 104 is shown by a section 208.
In more detail, by turning off the backlight module 104, the display device 1 can achieve the effect of inserting black pictures between display pictures, i.e. backlight black insertion, so that the picture persistence time for the human eyes is reduced, and the effect of dynamic blur is further reduced. However, since the liquid crystal reaction speed of the liquid crystal display panel 100 is not fast enough, it takes 4 to 6 ms or more than 10 ms to react completely. If the backlight module 104 is turned on too early, the response time of the display unit of the liquid crystal display panel 100 updated later according to the frame data is insufficient, which results in different effects of improving the dynamic blur in the vertical direction.
Therefore, the display device 1 of the present invention can transmit the frame data to the liquid crystal display panel 100 in a shorter time by increasing the output pixel clock through the driving module 102, so that the display unit has enough response time. The backlight module 104 can be turned on in the interval 208 after waiting for the liquid crystal display panel 100 to react to the output frame data corresponding to the output frame data interval 204, so as to solve the problem of insufficient reaction time of the liquid crystal display panel 100.
It should be noted that the predetermined time TD for the delay and the size of the first portion 201 to be stored in the storage unit 108 can be determined according to the magnitude relationship between the output pixel clock and the input pixel clock and the response time of the lcd panel 100. In addition, the backlight 101 generated by the backlight module 104 may be a strobe backlight (strobe backlight), and the backlight module 104 determines the illumination brightness according to the on time. For example, when the backlight module 104 is turned on for a short time, the brightness of the illumination can be improved, so as to avoid the brightness of the liquid crystal display panel 100 from being too dark.
Please refer to fig. 3. FIG. 3 is a timing diagram of the input display data 103 and the output display data 105 according to another embodiment of the present invention.
As shown in fig. 3, the input display data 103 has a plurality of input vertical synchronization signals vsync_in, and each two adjacent input vertical synchronization signals vsync_in will correspond to data containing one display frame.
The input display data 103 has an input frame data section 300 transmitted at an input pixel clock and an input blank section 302 following the input frame data section 300 within a frame time TFI between two adjacent input vertical synchronization signals vsync_in.
In one embodiment, the input frame data section 300 is used to transmit actual frame data, while the input blank section 302 is used to transmit no frame data.
Similarly, the output display data 105 has a plurality of output vertical synchronization signals vsync_out. In the present embodiment, the output display data 105 is divided into two sub-frame times by three output vertical synchronization signals vsync_out in the frame time TFO having the same time length as the frame time TFI. Wherein the first sub-frame time is the output frame data interval 304 and the second sub-frame time is the redundant output frame data interval 306. In another embodiment, the frame time of the output display data is divided into N-1 sub-frame times by N output vertical synchronous signals Vsync_out, wherein N is an integer greater than 3, but the invention is not limited thereto. In addition, the output frame data interval 304 corresponds to the first sub-frame time, and the redundant output frame data interval 306 corresponds to at least one sub-frame time after the first sub-frame time.
In one embodiment, the frame time TFO in the output display data 105 is delayed by a predetermined time TD from the corresponding frame time TFI in the input display data 103 so that the frame data is not lost. In other words, the output vertical synchronization signal vsync_out corresponding to both ends of each frame time TFO is delayed by the preset time TD from the input vertical synchronization signal vsync_in corresponding to the frame time TFI.
At this time, the input picture data section 300 corresponds to the input picture data. The processing module 106 can temporarily store all the input frame data by the included storage unit 108, so as to transmit the input frame data as output frame data in the output frame data interval 304 in a manner of partially accessing the storage unit 108 and partially directly outputting the input frame data by using the output pixel clock greater than the input pixel clock. Further, the processing module 106 accesses the storage unit 108 in the redundant output frame data interval 306, and transmits the redundant output frame data again at an output pixel clock greater than the input pixel clock, and outputs the redundant output frame data.
Therefore, the processing module 106 is further configured to control the backlight module 104 to turn on only in the redundant output frame data interval 306 after the liquid crystal display panel 100 has reacted to the output frame data corresponding to the output frame data interval 304. In fig. 3, the time for turning on the backlight module 104 is shown by a section 308.
In more detail, by turning off the backlight module 104, the display device 1 can achieve the effect of inserting black pictures between display pictures, so that the time for suspending pictures seen by human eyes is reduced, and the effect of dynamic blur is reduced. However, since the liquid crystal reaction speed of the liquid crystal display panel 100 is not fast enough, it takes 4 to 6 ms or more than 10 ms to react completely. If the backlight module 104 is turned on too early, the response time of the display unit of the liquid crystal display panel 100 updated later according to the frame data is insufficient, which results in a poor effect of improving the dynamic blur.
Therefore, the display device 1 of the present invention can transmit the frame data to the liquid crystal display panel 100 in a shorter time by increasing the output pixel clock through the driving module 102, and make the frame update rate of the output display data 105 be actually 2 times or more than 2 times the frame update rate of the input display data 103 in a repeated frame playing manner, but have the same equivalent frame update rate. The display unit will have sufficient reaction time due to the repetition of the picture content. The backlight module 104 can be turned on in the interval 308 after waiting for the liquid crystal display panel 100 to react with the output frame data corresponding to the output frame data interval 304, that is, the backlight is turned on only after the last piece of the repeated image, so as to solve the problem of insufficient reaction time of the liquid crystal display panel 100.
It should be noted that the predetermined time TD for the delay may be determined according to the magnitude relationship between the output pixel clock and the input pixel clock and the response time of the lcd panel 100. In addition, in the above embodiment, taking 2 times of playing the output frame data as an example, in other embodiments, when the output pixel clock is more times higher than the input pixel clock, the effect of playing the output frame data with higher magnification can be achieved.
Please refer to fig. 4. Fig. 4 is a flowchart of a display method 400 for reducing motion blur according to an embodiment of the invention. The display method 400 can be applied to the display device 1 of fig. 1. The method 400 includes the following steps (it should be understood that the steps mentioned in this embodiment may be performed simultaneously or partially simultaneously, and the order of the steps may be adjusted according to the actual needs, unless the order is specifically described.
In step 401, the processing module 106 is enabled to receive the input display data 103, wherein the input display data 103 has an input frame data interval 200 transmitted by an input pixel clock and an input blank interval 202 following the input frame data interval 200 within a frame time TFI corresponding to a frame time between two adjacent input vertical synchronization signals vsync_in.
In step 402, the processing module 106 generates the output display data 105 according to the input display data 103, such that the output display data 105 has an output frame data section transmitted at an output pixel clock greater than the input pixel clock and an output blank section 206 or a redundant output frame data section 306 following the output frame data section within the same length of the frame time TFO.
In one embodiment, the processing module 106 may generate the output frame data interval 204 by the method shown in fig. 2 and the output blank interval 206 without transmitting frame data after the output frame data interval 204. In another embodiment, the processing module 106 can generate the output frame data interval 304 and transmit the redundant output frame data interval 306 of the redundant frame data after the output frame data interval 304 by the method shown in fig. 3.
In step 403, the processing module 106 drives the liquid crystal display panel 100 to generate a display screen according to the output display data 105 via the driving module 102.
In step 404, the processing module 106 controls the backlight module 104 to turn on only in the blank interval 206 or the redundant output frame data interval 306, after the lcd panel 100 has reacted to the output frame data corresponding to the output frame data interval (the output frame data interval 204 of fig. 2 or the output frame data interval 304 of fig. 3).
Please refer to fig. 5A, fig. 5B and fig. 5C. Fig. 5A is a schematic diagram of a backlight module 104 according to an embodiment of the invention. Fig. 5B is a schematic diagram of a liquid crystal display panel 100 according to an embodiment of the invention. Fig. 5C is a timing diagram of switching on and off the input display data 103, the output display data 105, and the backlight module 104 according to an embodiment of the invention.
As shown in fig. 5A and 5B, the backlight module 104 is divided into a plurality of backlight assembly sections BZ1, BZ2, BZ3 and BZ4, and the liquid crystal display panel 100 is divided into panel sections PZ1, PZ2, PZ3 and PZ4. The backlight assembly may be a Light Emitting Diode (LED) or a Cold Cathode Fluorescent Lamp (CCFL) to be divided into a plurality of backlight assembly sections BZ1, BZ2, BZ3 and BZ4, to which the present invention is not limited. In one embodiment, the size of the liquid crystal display panel 100 is substantially the same as that of the backlight module 104, and the backlight assembly sections BZ1, BZ2, BZ3 and BZ4 generate backlight to the corresponding panel areas PZ1, PZ2, PZ3 and PZ4, respectively.
As shown in fig. 5C, the input display data 103 has a plurality of input vertical synchronization signals vsync_in, and each two adjacent input vertical synchronization signals vsync_in corresponds to data including one display frame.
The input display data 103 has an input frame data section 500 transmitted at an input pixel clock and an input blank section 502 following the input frame data section 500 within a frame time TFI between two adjacent input vertical synchronization signals vsync_in.
In one embodiment, the input frame data section 500 is used to transmit actual frame data. While the blank interval 502 is input without transmitting the picture data.
Similarly, the output display data 105 has a plurality of output frame data sections 504A, 504B, 504C and 504D transmitted at the output pixel clock within the frame time TFO between two adjacent output vertical synchronization signals vsync_out, and an input blank section 506 following the output frame data sections 504A to 504D.
In this embodiment, the output pixel clock and the input pixel clock are equal, and there is no delay between the frame time TFO of the output display data 105 and the frame time TFI corresponding to the input display data 103. Thus, the total time length of the output frame data sections 504A-504D is substantially the same as the input frame data section 500. Wherein, the output frame data sections 504A-504D sequentially transmit the input frame data corresponding to one of the panel regions PZ1, PZ2, PZ3 and PZ4, respectively. While the blank interval 502 is input without transmitting the picture data.
The processing module 106 is configured to control the backlight assembly sections BZ1, BZ2, BZ3 and BZ4 to be turned on after the corresponding panel areas PZ1, PZ2, PZ3 and PZ4 have reacted with the output frame data, respectively, so as to generate backlight to the panel areas PZ1, PZ2, PZ3 and PZ4.
In fig. 5C, the timing of turning on the backlight assembly zones BZ1, BZ2, BZ3 and BZ4 of the backlight module 104 is shown. In the present embodiment, the backlight assembly section BZ1 is turned on at a time corresponding to the output frame data section 504D to illuminate the panel area PZ1.
Therefore, the display unit of the panel region PZ1 has a response time corresponding to the length of the frame data sections 504B and 504C. The subsequent backlight assembly sections BZ2 to BZ3 will have the same length of response time for the display units of the illumination panel sections PZ2 to PZ3 when they are turned on.
In one embodiment, the backlight assembly segments BZ1, BZ2, BZ3 and BZ4 are turned on for a period corresponding to the period of the output frame data segments 504A to 504D, so that each panel region PZ2 to PZ3 has an average response time and brightness.
Therefore, the display device 1 of the present invention can achieve the effect that the display unit will have enough response time and solve the problem of insufficient response time of the liquid crystal display panel 100 by controlling the on-time of the backlight module 104 in a partitioning manner without changing the pixel clock and the frame update rate of the output display data 105 relative to the input display data 103.
Please refer to fig. 6. Fig. 6 is a flowchart of a display method 600 for reducing motion blur according to an embodiment of the invention. The display method 600 can be applied to the display device 1 of fig. 1 and fig. 5A, 5B, and 5C. The method 600 includes the following steps (it should be understood that the steps mentioned in this embodiment may be performed simultaneously or partially simultaneously, and the order of the steps may be adjusted according to the actual needs, unless the order is specifically described.
In step 601, the processing module 106 is enabled to receive the input display data 103 to generate the output display data 105, and drive the liquid crystal display panel 100 to generate a display screen according to the output display data 105 through the driving module 102, wherein the output display data 105 has a plurality of output screen data sections 504A to 504D corresponding to one of the panel regions within a screen time TFO between two adjacent output vertical synchronization signals vsync_out, respectively.
In step 602, the processing module 106 is enabled to control the backlight module segments BZ1, BZ2, BZ3 and BZ4 to be turned on after the corresponding panel regions PZ1, PZ2, PZ3 and PZ4 have reacted with the output frame data, so as to generate backlight to the panel regions PZ1, PZ2, PZ3 and PZ4.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the invention, but any modifications, equivalents, improvements, etc. within the principles of the present invention should be included in the scope of the present invention.
Claims (8)
1. A display device for reducing motion blur, comprising:
a liquid crystal display panel;
a driving module electrically coupled to the LCD panel;
a backlight module configured to generate a backlight to the liquid crystal display panel; and
a processing module, electrically coupled to the backlight module and the driving module, configured to receive an input display data, wherein the input display data has an input frame data interval transmitted by an input pixel clock (pixelclock) and an input blank interval following the input frame data interval within a frame time between two adjacent input vertical synchronization (vertical sync signals; vsync) signals;
the processing module is configured to generate an output display data according to the input display data, so that the output display data has an output picture data section transmitted by an output pixel clock pulse greater than the input pixel clock pulse and a redundant output picture data section behind the output picture data section in the picture time with the same length, and the liquid crystal display panel is driven by the driving module to generate a display picture according to the output display data;
the processing module is further configured to control the backlight module to be turned on only in the redundant output frame data section after the LCD panel has reacted with an output frame data corresponding to the output frame data section,
the frame time of the output display data is divided into N-1 sub-frame times by N output vertical synchronous signals, the output frame data interval corresponds to the first sub-frame time, and the redundant output frame data interval corresponds to at least one sub-frame time after the first sub-frame time;
the processing module further comprises a storage unit configured to temporarily store the input picture data, to output the input picture data in the output picture data section as the output picture data, and to access the storage unit at each sub-picture time after the first sub-picture time to output the input picture data again as a redundant output picture data.
2. The display device of claim 1, wherein the frame time of the output display data is delayed by a predetermined time relative to the frame time corresponding to the input display data.
3. The display device of claim 2, wherein a picture update rate of the output display data is 2 times or more than an integer multiple of the picture update rate of the input display data.
4. The display device of claim 1, wherein the processing module is a scaler (scaler) or a timing controller.
5. A display method for reducing dynamic blur is applied to a display device, the display device comprises a liquid crystal display panel, a driving module electrically coupled to the liquid crystal display panel, a backlight module configured to generate a backlight to the liquid crystal display panel, and a processing module electrically coupled to the backlight module and the driving module, the display method comprises the following steps:
the processing module receives an input display data, wherein the input display data has an input picture data interval transmitted by an input pixel clock and an input blank interval behind the input picture data interval in a picture time corresponding to two adjacent input vertical synchronous signals;
the processing module generates an output display data according to the input display data, so that the output display data has an output picture data section transmitted by an output pixel clock pulse greater than the input pixel clock pulse and a redundant output picture data section behind the output picture data section in the picture time with the same length;
the processing module drives the liquid crystal display panel to generate a display picture through the driving module according to the output display data; and
the processing module controls the backlight module to be turned on only in the blank output interval, the LCD panel is turned on after finishing responding to an output picture data corresponding to the output picture data interval,
the frame time of the output display data is divided into N-1 sub-frame times by N output vertical synchronous signals, the output frame data interval corresponds to the first sub-frame time, the redundant output frame data interval corresponds to at least one sub-frame time after the first sub-frame time, the input frame data interval corresponds to an input frame data, the display method further comprises:
temporarily storing the input frame data in a storage unit included in the processing module;
outputting the input picture data as the output picture data in the output picture data section; and
the storage unit is accessed at each sub-frame time after the first sub-frame time to output the input frame data again as a redundant output frame data.
6. The display method according to claim 5, wherein the frame time of the output display data is delayed by a predetermined time relative to the frame time corresponding to the input display data.
7. The display method of claim 5, wherein a picture update rate of the output display data is 2 times or more than an integer multiple of the picture update rate of the input display data.
8. The display method according to claim 5, wherein the processing module is a scaler or a timing controller.
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