CN111198843A - File system writing acceleration method based on bus control on application processor chip - Google Patents
File system writing acceleration method based on bus control on application processor chip Download PDFInfo
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Abstract
The invention discloses a file system writing acceleration method based on bus control on an application processor chip, which comprises the following steps: calling an open () function of the file system to create a file and obtain a file handle; calling a write () function of a file system to write sensor data into a file, writing the data into a memory by the file system according to the size of a fixed file, wherein the single writing is carried out according to the size of a Page, only generating tag information of the Page by the file system in the writing process, and copying the tag information of the Page to a buffer area of a controller by a driving layer; when the processor obtains a data writing starting signal, the processor starts to monitor the data of the on-chip bus; the coprocessor acquires and temporarily stores an on-chip bus Page, then replaces a Page data area with data in an external data buffer area according to a fixed size, and sends the replaced Page to the memory; when the size of the residual written file is less than or equal to 0, the file writing is finished; the file system calls the close () function to close the file, which can speed up the storage performance of the file system.
Description
Technical Field
The invention belongs to the field of embedded system software, and relates to a file system write acceleration method based on-chip bus control of an application processor.
Background
An embedded system is a special computer system designed for specific applications, and with the wide application of the embedded system in the current society, the embedded system faces the challenges of complex application scene, heavy data processing task and the like. A typical application of the embedded system is data collection and storage, and a file system is generally applied in a system software layer in order to facilitate access and search of data.
The file system is widely applied to embedded system software as a method for storing and organizing computer data, the file system in the embedded system software is limited by the performance of a processor and the limitation of on-chip resources, generally brings adverse effects on the speed of the multitask or process operation of the software system, and particularly in some application scenes with high requirements on real-time performance, such as aerospace, automotive electronics and other equipment, the storage performance of the file system becomes a key element directly influencing the whole system.
Therefore, in the face of a complex and large-volume data processing environment and a scene with high performance requirements, acceleration of storage performance of a file system is a great concern in the field of embedded systems.
Disclosure of Invention
The present invention is directed to overcoming the above-mentioned drawbacks of the prior art and providing a file system write acceleration method based on bus control on an application processor chip, which can accelerate the storage performance of the file system.
In order to achieve the aim, the accelerating method is completed by the cooperation of a file system and an FPGA coprocessor, wherein the file system runs in a main processor and comprises an open () function interface, a read () function interface, a write () function interface and a close () function interface; the memory is connected with an on-chip bus of the application processor through the FPGA coprocessor, and the file system is used for generating tag information of the Page in the process of writing the file; the peripheral data stream is stored in a buffer area of the coprocessor in real time, the coprocessor monitors through an on-chip bus, temporarily stores a Page captured by the on-chip bus, and replaces the Page data area with data in the buffer area;
the method specifically comprises the following steps:
1) starting an application processor operating system, finishing initialization of a file system, entering a synchronous communication state after a coprocessor receives an application processor and file system starting finishing signal, and waiting for an operating signal of the file system;
2) calling an open () function of the file system to create a file and obtain a file handle;
3) calling a write () function of a file system to write peripheral data into a file, writing the data into a memory by the file system according to the size of a fixed file, wherein the single writing is carried out according to the size of a Page, only generating tag information of the Page by the file system in the writing process, and copying the tag information of the Page to a buffer area of a controller by a driving layer; when the coprocessor obtains a data writing start signal, starting to monitor the data of the on-chip bus;
4) the coprocessor acquires and temporarily stores an on-chip bus Page, then replaces a Page data area with data in an external data buffer area according to a fixed size, and sends the replaced Page to the memory;
5) when the size of the residual written file is less than or equal to 0, ending the file writing, otherwise, turning to the step 3);
6) the file system calls the close () function to close the file.
Establishing a bottom layer communication mechanism with a memory driving layer in a file system, and marking the content type written into a memory by an upper layer application; and establishing a calling start signal and a calling end signal before and after a write () function body of the file system, driving a bottom-layer Page writing function to judge whether the upper-layer calling function writes file data or not through the mark, and writing a Tags signal of the Page into a controller buffer area of the memory to start a writing command when the operation is confirmed to be the operation of writing the file data.
Establishing a synchronous communication mechanism between the application processor and the FPGA coprocessor, wherein the synchronous communication mechanism is used for synchronizing the cooperative writing operation of the file system and the coprocessor to the Page; when a file system calls a write () function to start writing data into a file, a start signal and an end signal are respectively triggered before and after the write () function interface is called, and when a coprocessor receives the start signal, an on-chip bus monitoring mode is started to operate a Page data area; and when the coprocessor receives the ending signal, the monitoring mode is exited, and the memory is directly connected with the local recovery bus of the processor.
Performing a first-stage operation on a Page by a write () function interface of a file system, specifically, generating tag information and filling a section corresponding to a buffer area of a controller, wherein the position of a data area of the buffer area of the controller is reserved but is not operated; and then the coprocessor carries out second-stage operation on the Page, and specifically, the Page data area is replaced by the external data stream buffer area according to a fixed size.
The running state of the coprocessor comprises an initial state, a synchronous communication state, a time sequence monitoring state and a data insertion state, and in the initial state, the memory is directly connected with the bus on the application processor chip; in a synchronous communication state; the initialization of the file system of the application processor is completed; in a time sequence monitoring state, calling a write () function interface of a file system to prepare for writing data into a file; in a data insertion state, replacing a Page data area with an external data buffer area according to a fixed size, and sending a Page to a memory; the translation between the states of the coprocessor is controlled by the application processor and coprocessor event states.
The invention has the following beneficial effects:
when the file system write acceleration method based on the bus control on the application processor chip is specifically operated, a communication identifier of an application interface layer and a memory controller driving layer is established in the file system, and the bottom layer judges the operation of the bottom layer calling on the Page through the identifier; meanwhile, a quick communication mechanism is established between the application processor and the coprocessor, a file system only needs to generate and copy tag data to a controller buffer area, and the coprocessor monitors the on-chip bus time sequence and replaces actual data to a Page data area; the invention reduces the data flow path when the original file system stores the external data, realizes the shortest path for directly storing the external data into the memory, and greatly reduces the repeated copying of the data by the processor of the Load-Store mechanism, wherein, the file system only needs to be responsible for the creation of the file and the tag information of each page to be written, thereby reducing the code execution amount of the main processor calling the writing interface of the file system, and accelerating the writing performance of the file system.
Drawings
FIG. 1 is a comparison of a data flow path of a file system before and after applying the present invention in accordance with one embodiment;
FIG. 2 is a system hardware connection diagram according to the first embodiment;
FIG. 3 is a diagram of a specific function call process for the Yaffs2 file system process;
FIG. 4 is a diagram of the conversion relationship between different states of the FPGA.
Detailed Description
The invention is described in further detail below with reference to the accompanying drawings:
the invention is completed by the cooperation of a file system and an FPGA coprocessor, wherein the FPGA coprocessor is positioned between an application processor storage controller and a memory and is used for monitoring the time sequence of an on-chip bus, and simultaneously, externally arranged acquisition data is collected to a buffer area of the processor; the coprocessor monitors a Page write time sequence of an on-chip bus, performs multi-level caching on the data, and replaces the data in an external data buffer area to a Page data area, wherein the size of the data area is determined according to the adaptive value of a memory and a memory controller buffer area;
the application processor runs a software system and comprises a file system, and the FPGA coprocessor is used as hardware in the invention to jointly complete the cooperative acceleration of the software and the hardware of the file system;
the file system runs in a main processor and comprises an open () function interface, a read () function interface, a write () function interface and a close () function interface; the memory is connected with an on-chip bus of the application processor through the FPGA coprocessor, and the file system is used for generating tag information of the Page in the process of writing the file; the peripheral data stream is stored in a buffer area of the coprocessor in real time, the coprocessor monitors through an on-chip bus, temporarily stores a Page captured by the on-chip bus, and replaces the Page data area with data in the buffer area; specifically, the file system write acceleration method based on the bus control on the application processor chip specifically comprises the following steps:
1) starting an application processor operating system, finishing initialization of a file system, entering a synchronous communication state after a coprocessor receives an application processor and file system starting finishing signal, and waiting for an operating signal of the file system;
2) calling an open () function of the file system to create a file and obtain a file handle;
3) calling a write () function of a file system to write peripheral data into a file, writing the data into a memory by the file system according to the size of a fixed file, wherein the single writing is carried out according to the size of a Page, only generating tag information of the Page by the file system in the writing process, and copying the tag information of the Page to a buffer area of a controller by a driving layer; when the coprocessor obtains a data writing start signal, starting to monitor the data of the on-chip bus;
4) the coprocessor acquires and temporarily stores an on-chip bus Page, then replaces a Page data area with data in an external data buffer area according to a fixed size, and sends the replaced Page to the memory;
5) when the size of the residual written file is less than or equal to 0, ending the file writing, otherwise, turning to the step 3);
6) the file system calls the close () function to close the file.
Establishing a bottom layer communication mechanism with a memory driving layer in a file system, and marking the content type written into a memory by an upper layer application; and establishing a calling start signal and a calling end signal before and after a write () function body of the file system, driving a bottom-layer Page writing function to judge whether the upper-layer calling function writes file data or not through the mark, and writing a Tags signal of the Page into a controller buffer area of the memory to start a writing command when the operation is confirmed to be the file data writing operation.
When the flag bit is 1, the function interface based on the invention is called, and when the flag bit is 0, the function is not called; the memory controller drives a file system interface called by the application layer judged by the global zone bit; when the drive layer writes the memory buffer area function and judges that the global flag bit is 1, the upper application software is identified to call the function interface designed by the invention, and only the Tags information of the memory controller buffer area is operated and copied; when the drive layer writes the memory buffer area function and judges that the global flag bit is 0, the drive layer indicates that the upper application software calls the original file system function interface, the drive layer keeps the original Page processing process unchanged, namely, data with fixed length transmitted by the file system is copied to the data segment of the memory controller buffer area, and the Tags information generated by the file system is copied to the Tags area of the controller buffer area.
Establishing a synchronous communication mechanism between the application processor and the FPGA coprocessor, wherein the synchronous communication mechanism is used for synchronizing the cooperative writing operation of the file system and the coprocessor to the Page; when a file system calls a write () function to start writing data into a file, a start signal and an end signal are respectively triggered before and after the write () function interface is called, and when a coprocessor receives the start signal, an on-chip bus monitoring mode is started to operate a Page data area; and when the coprocessor receives the ending signal, the monitoring mode is exited, and the direct connection between the memory and the on-chip bus of the processor is restored.
Performing a first-stage operation on a Page by a write () function interface of a file system, specifically, generating tag information and filling a section corresponding to a buffer area of a controller, wherein the position of a data area of the buffer area of the controller is reserved but is not operated; and then the coprocessor carries out second-stage operation on the Page, and specifically, the Page data area is replaced by the external data stream buffer area according to a fixed size.
The running state of the coprocessor comprises an initial state, a synchronous communication state, a time sequence monitoring state and a data insertion state, and in the initial state, the memory is directly connected with the bus on the application processor chip; in a synchronous communication state; the initialization of the file system of the application processor is completed; in a time sequence monitoring state, calling a write () function interface of a file system to prepare for writing data into a file; in a data insertion state, replacing a Page data area with an external data buffer area according to a fixed size, and sending a Page to a memory; the translation between the states of the coprocessor is controlled by the application processor and coprocessor event states.
The invention ensures that the original application software calling interface of the file system is unchanged, adds the file data writing function interface based on the invention, keeps the parameter of the function interface consistent, is convenient for the upper application interface to migrate, and only needs to replace the original file system to write the data API function name when the invention is applied.
In the invention, the application processor adopts a PowerPC processor, the coprocessor adopts an FPGA, the data storage medium adopts NAND Flash, the NAND Flash and the on-chip bus of the PowerPC processor are both connected with the FPGA, and the file system adopts Yaffs 2; data collected by the peripheral equipment are collected into an FIFO (first in first out) in the FPGA, and application software stores the data flow data.
Example one
An embedded system for data acquisition is built, and hardware resources on the system are as follows: a 32-bit PowerPC processor, 128MBDDR, 8M NorFlash, 2GB NAND Flash and FPGA; the FPGA is used as a coprocessor, and an external acquisition data stream is temporarily stored in the FPGA at first; the system software adopts a Yaffs2 file system, the application layer constructs a data acquisition function, and calls a file system standard API to store data in the NAND Flash.
In the embodiment, the NAND Flash is 2GB in size, the single Page is 2KB +64B in size, the Flash controller buffer in the PowerPC is set to be 2KB +64B in size, the parameter of Page operation in the file system is also set to be the value, and the software and hardware parameters are unified.
FIG. 1 is a comparison of a file system data flow path before and after the application of the present invention.
The original data flow path is: external data is stored in an asynchronous FIFO (first in first out) in an FPGA (field programmable gate array) in real time, and a PowerPC (personal computer) processor firstly copies the data in the FIFO to a continuous space Buffer area opened in a memory; after the initialization of the file system is completed, storing the data in the Buffer into a file, writing the data into the file in the process of storing the data by taking pages as units, and generating extra OOB information for each Page and attaching the extra OOB information to a Tags area; and respectively filling the data area and the OOB area of the Page into a cache area of a Flash controller, and sending a write instruction to the controller by a drive layer to finish the writing of a single Page.
The data path after the invention is applied is as follows: external data are stored in the FPGA asynchronous FIFO, and the PowerPC processor does not need to open up an external data cache region in the memory; the Yaffs2 file system is responsible for creating a file, acquiring a file handle, when Page data is written into the file, operating a Flash controller data area is not performed, only OOB area data of the virtual Page is generated and filled into a controller buffer area, and a drive layer sends a writing instruction to the controller; and the FPGA carries out secondary temporary storage on the Page time sequence sent to the NAND Flash by the controller by monitoring the on-chip bus time sequence, and replaces external data stored in the FIFO into a Page data area according to a fixed size of 2 KB.
FIG. 2 is a system hardware connection diagram. The NAND Flash is connected to PowerPC LocalBus through the FPGA, and the length of a data bus of the NAND Flash is 8 bits; the PowerPC and the FPGA communicate through 2 paths of GPIOs, wherein one path of GPIOs are responsible for starting the processor to complete a synchronization signal, and the other path of GPIOs are used as a file system Page writing process starting synchronization signal.
FIG. 3 is a diagram of a specific function call process for processing the Yaffs2 file system, wherein three file system APIs, respectively Yaffs _ open (), Yaffs _ write _ fpga (), and Yaffs _ close (), are respectively called for data storage; yaffs _ open () creates a file containing the file name and authority attributes, etc., and returns the file handle; yaffs _ write _ fpga () is a file writing API realized by applying the present invention, and the number and the type of the parameters of the interface are kept consistent with those of the yaffs2 standard API, so that the application of the present invention becomes convenient; yaffs _ close () closes the file handle, marking the process of saving a piece of data to the file complete.
Flash controller buffer write operation is called by yaffs _ open () and yaffs _ write _ FPGA () on the bottom layer, and a global variable FPGA _ FLAG is used for a driving layer to judge an upper layer calling interface of the buffer write operation in a yaffs2 file system; when the Flash controller driver layer is called by yaffs _ open (), keeping the operation of the original driver layer on Page unchanged; when the Flash controller driver layer is called by yaffs _ write _ fpga (), the driver layer writes the buffer function to only write the OOB information into the buffer, and sends a write instruction to the Flash controller.
Referring to fig. 3, the processing of the yaffs _ write _ fpga () function is described in detail.
After a file is opened or created, a yaffs _ open () function returns a handle, wherein in the function parameter list, TestT is a memory Buffer pointer and points to memory data Buffer, and nBytes is the number of bytes to be stored; yaffs _ write _ fpga () acquires the file handle pointer and handle object, and the lower layer calls the yaffs _ write datatofile () function; the yaffs _ WriteDataToFile () function contains a while loop, a Page is written in a single loop, and when the data length of the residual writing buffer is less than 0, the loop is ended, and the writing of the file content is finished.
yaffs2 file system bottom layer processing functions yaffs _ WriteCornkDataToObject () to yaffs _ WriteCornkWithTagToNAND () are processing operations to the write page in sequence; the MTD layer nandmtd2_ WritEChunkWithTagsToNAND () to fsl _ elbc _ write _ buf () is a NAND Flash controller driver layer function, and the final data writing of the software layer is completed.
The Flash controller buffer is completed by fsl _ elbc _ write _ buf (), and when the write length is judged to be equal to 64, the write length represents that the OOB data are written in the call; otherwise, continuously judging the value of the FPGA _ FLAG, and writing data if the value is true, operating as null and false; when the data operation of the controller buffer area is completed, a writing instruction is sent to the FCM, and the FCM starts a writing time sequence on hardware.
When the while loop of yaffs _ WriteDataToFile () function judges that the byte nByte which needs to be continuously written is less than or equal to 0, the completion of data writing of the file system is represented, a writing end signal is immediately sent to the FPGA, meanwhile, the global FLAG variable FPGA _ FLAG is assigned to false, and the FPAG receives the signal and exits the time sequence monitoring state.
FIG. 4 is a conversion relationship diagram of different states of the FPGA, after power-on is started, the PowerPC raises the GPIO1, and the FPGA enters a synchronous communication state after receiving the signal; in a synchronous communication state, when the FPGA captures a GPIO2 pull-up signal, entering a NAND Flash time sequence monitoring mode; when capturing a Page of an on-chip bus, entering a data insertion state, performing secondary registration on the Page, replacing data in the asynchronous FIFO with a Page data area, and returning to a time sequence monitoring mode after finishing; when the GPIO2 is pulled low, indicating that the file writing process is complete, a synchronous communication state is returned.
The above description is only one embodiment of the present invention, and not all or only one embodiment, and any equivalent alterations to the technical solutions of the present invention, which are made by those skilled in the art through reading the present specification, are covered by the claims of the present invention.
Claims (5)
1. A file system write acceleration method based on bus control on an application processor chip is characterized in that the acceleration method is completed by the cooperation of a file system and an FPGA coprocessor, the file system runs in a main processor, and the file system comprises an open () function interface, a read () function interface, a write () function interface and a close () function interface; the memory is connected with an on-chip bus of the application processor through the FPGA coprocessor, and the file system is used for generating tag information of the Page in the process of writing the file; the peripheral data stream is stored in a buffer area of the coprocessor in real time, the coprocessor monitors through an on-chip bus, temporarily stores a Page captured by the on-chip bus, and replaces the Page data area with data in the buffer area;
the method specifically comprises the following steps:
1) starting an application processor operating system, finishing initialization of a file system, entering a synchronous communication state after a coprocessor receives an application processor and file system starting finishing signal, and waiting for an operating signal of the file system;
2) calling an open () function of the file system to create a file and obtain a file handle;
3) calling a write () function of a file system to write peripheral acquired data into a file, writing the data into a memory by the file system according to the size of a fixed file, wherein the single writing is carried out according to the size of a Page, only generating tag information of the Page by the file system in the writing process, and copying the tag information of the Page to a buffer area of a controller by a driving layer; when the coprocessor obtains a data writing start signal, starting to monitor the data of the on-chip bus;
4) the coprocessor acquires and temporarily stores an on-chip bus Page, then replaces a Page data area with data in an external data buffer area according to a fixed size, and sends the replaced Page to the memory;
5) when the size of the residual written file is less than or equal to 0, ending the file writing, otherwise, turning to the step 3);
6) the file system calls the close () function to close the file.
2. The method of claim 1, wherein a bottom-level communication mechanism is established in the file system with the memory driver layer to mark the type of content written to memory by upper-level applications; and establishing a calling start signal and a calling end signal before and after a write () function body of the file system, driving a bottom-layer Page writing function to judge whether the upper-layer calling function writes file data or not through the mark, and writing a Tags signal of the Page into a controller buffer area of the memory to start a writing command when the operation is confirmed to be the file data writing operation.
3. The file system write acceleration method based on bus control on the application processor chip as claimed in claim 1, characterized in that a synchronous communication mechanism is established between the application processor and the FPGA coprocessor, said synchronous communication mechanism is used for synchronizing the cooperative write operation to Page between the file system and the coprocessor; when a file system calls a write () function to start writing data into a file, a start signal and an end signal are respectively triggered before and after the write () function interface is called, and when a coprocessor receives the start signal, the coprocessor starts an on-chip bus monitoring mode to operate a Page data area; and when the coprocessor receives the ending signal, the monitoring mode is exited, and the memory is directly connected with the on-chip bus of the application processor.
4. The method of claim 2, wherein the write () function interface of the file system performs a first phase operation on the Page, specifically, generating Tags information and filling the corresponding sectors of the controller buffer, and the controller buffer data area is reserved but not operated; and then the coprocessor carries out second-stage operation on the Page, and specifically, the Page data area is replaced by the external data stream buffer area according to a fixed size.
5. The method according to claim 3, wherein the operating states of the coprocessor include an initial state in which the memory is directly connected to the on-chip bus of the application processor, a synchronous communication state, a timing monitoring state, and a data insertion state; in a synchronous communication state; the initialization of the file system of the application processor is completed; in a time sequence monitoring state, an application processor calls a write () function interface of a file system to write data into a file, and a coprocessor monitors bus data on a chip; in a data insertion state, replacing a Page data area with a peripheral acquired data buffer area according to a fixed size, and sending a Page to a memory; the translation between the states of the coprocessor is controlled by the application processor and coprocessor event states.
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| CN113253942A (en) * | 2021-06-25 | 2021-08-13 | 深圳小米通讯技术有限公司 | File writing method and device, file reading method and device, equipment and medium |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112001494A (en) * | 2020-08-20 | 2020-11-27 | 浪潮电子信息产业股份有限公司 | Method for realizing support of FPGA (field programmable Gate array) back-end equipment by nGraph framework |
| US11762721B2 (en) | 2020-08-20 | 2023-09-19 | Inspur Electronic Information Industry Co., Ltd. | Method for realizing nGraph framework supporting FPGA rear-end device |
| CN113253942A (en) * | 2021-06-25 | 2021-08-13 | 深圳小米通讯技术有限公司 | File writing method and device, file reading method and device, equipment and medium |
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| CN111198843B (en) | 2023-03-28 |
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