CN111198757B

CN111198757B - CPU kernel scheduling method, CPU kernel scheduling device and storage medium

Info

Publication number: CN111198757B
Application number: CN202010011545.8A
Authority: CN
Inventors: 谷超; 董万强; 张楠
Original assignee: Beijing Xiaomi Mobile Software Co Ltd
Current assignee: Beijing Xiaomi Mobile Software Co Ltd
Priority date: 2020-01-06
Filing date: 2020-01-06
Publication date: 2023-11-28
Anticipated expiration: 2040-01-06
Also published as: CN111198757A

Abstract

The disclosure relates to a CPU kernel scheduling method, a CPU kernel scheduling device and a storage medium. The CPU kernel scheduling method is applied to a terminal, wherein a frame drawing application is installed on the terminal, the CPU of the terminal supports a multi-core cluster platform architecture, and the CPU kernel scheduling method comprises the following steps: respectively determining the scheduling delay time of each core in each core cluster in the multi-core clusters in a frame drawing period; if the scheduling delay time of each kernel in the first cluster exceeds a specified delay time threshold, scheduling the tasks with the specified number in the first cluster into a second cluster; the second cluster is different from the first cluster, and the performance index meets the requirement of running the specified number of tasks. By the method and the device, scheduling delay in a heavy load scene can be reduced, and blocking is reduced.

Description

CPU kernel scheduling method, CPU kernel scheduling device and storage medium

Technical Field

The disclosure relates to the technical field of terminals, and in particular relates to a CPU core scheduling method, a CPU core scheduling device and a storage medium.

Background

Along with the popularization of touch screen smartphones and the high-speed development of mobile phone hardware, the application supported by smartphones is more and more, and further, the processing capacity requirements on hardware devices such as a central processing unit (central processing unit, CPU) of a terminal are continuously improved. For example, mobile games are popular with more and more young people as a daily entertainment mode for relaxing mood, reducing blood pressure and reducing emission. From early stand-alone games to multi-player online competitive (Multiplayer Online Battle Arena, MOBA) games with fire explosion in the market today, the load of the games is higher and higher, and the processing capacity requirements on hardware devices such as a CPU are also continuously improved.

The hardware devices such as the CPU cannot continuously maintain to work at the high-performance working frequency due to the restriction of heat dissipation and power consumption. For better balancing the relationship between performance and power consumption, the CPU evolved a big.littale architecture, i.e., a size core architecture. By tracking the load change of the thread, the thread is divided into large and small tasks, the large tasks with heavy load are run on a Big core (Big core) to obtain better performance experience, and the small tasks with light load are run on a small core (LITTLE core) to save power consumption.

Furthermore, in order to fully utilize the performance of hardware and take account of power consumption and heating, some platforms are newly added with one to two oversized cores to provide additional performance support on the basis of a large-sized core architecture, so that a novel multi-core cluster platform architecture, such as a three-core cluster (3-cluster) platform architecture, namely a small-medium-large (Little-Mid-Big) architecture, is hatched by a traditional big.LITTLE double cluster architecture. The Little core cluster (Little cluster) composed of Little cores, the middle core cluster (Mid cluster) composed of middle cores and the Big core cluster (Big cluster) composed of Big cores are included in the Little-Mid-Big architecture. The Big cluster is used for meeting the interactive input which is strict or sensitive to the response time requirement, and providing additional performance support when the system load is very heavy.

However, in consideration of power consumption and limitation of hardware heat dissipation capability, in a game scene, big cluster is not fully utilized, and actual tests show that in a process of backtracking reasons of frame loss caused by sudden heavy loads in the game scene, as hardware resources are not fully utilized in time, game computing capability is not met in time, and the problem of frame loss is more common.

Disclosure of Invention

In order to overcome the problems in the related art, the present disclosure provides a CPU core scheduling method, a CPU core scheduling apparatus, and a storage medium.

According to a first aspect of an embodiment of the present disclosure, there is provided a CPU core scheduling method applied to a terminal, where a frame drawing application is installed on the terminal, and a CPU of the terminal supports a multi-core cluster platform architecture, the CPU core scheduling method includes:

respectively determining the scheduling delay time of each core in each core cluster in the multi-core clusters in a frame drawing period; if the scheduling delay time of each kernel in the first cluster exceeds a specified delay time threshold, scheduling the tasks with the specified number in the first cluster into a second cluster; the second cluster is different from the first cluster, and the performance index meets the requirement of running the specified number of tasks.

In one embodiment, the method for scheduling a CPU core further includes:

determining a weight value of an operation task in each core cluster in the multi-core clusters according to the load size and the importance degree of the task; the task weight value with high load is higher than the task weight value with low load, and the task weight value with high importance degree is higher than the task weight value with low importance degree.

In another embodiment, scheduling the specified number of tasks in the first cluster to a second cluster includes:

and dispatching the tasks with the appointed number in the first cluster to a second cluster according to the sequence of the weight values of the tasks from high to low.

In yet another embodiment, the second cluster is a larger core cluster in the multi-core cluster having a higher index than the first cluster, and/or the second cluster is a core cluster in which the sum of the scheduling delay times of the cores in the multi-core cluster is less than the sum of the scheduling delay times of the cores in the first cluster.

In yet another embodiment, when there is a new task enqueue or a task scheduling switch, a scheduling delay time of each core in each core cluster in the multi-core cluster is respectively determined in a frame drawing period.

In another embodiment, the method for scheduling a CPU core further includes:

monitoring the number of ready tasks in each core cluster in the multi-core cluster in real time; and if the number of the ready tasks in the core cluster exceeds the set task number threshold, and the unactivated cores exist in the core cluster with the number of the ready tasks exceeding the set task number threshold, activating the unactivated cores.

In yet another embodiment, the multi-core cluster platform architecture is a three-core cluster platform architecture.

According to a second aspect of the embodiments of the present disclosure, there is provided a CPU core scheduling apparatus applied to a terminal, on which a frame drawing class application is installed, and a CPU of the terminal supports a multi-core cluster platform architecture, the CPU core scheduling apparatus including:

a determining unit, configured to determine a scheduling delay time of each core in each core cluster in the multi-core clusters in a frame drawing period; the scheduling unit is used for scheduling the tasks with the appointed number in the first cluster to the second cluster when the scheduling delay time of each kernel in the first cluster exceeds the appointed delay time threshold; the second cluster is different from the first cluster, and the performance index meets the requirement of running the specified number of tasks.

In one embodiment, the scheduling unit is further configured to:

In another embodiment, the scheduling unit schedules the specified number of tasks in the first cluster to the second cluster in the following manner:

In still another embodiment, the determining unit determines, when there is a new task enqueue or task scheduling switch, a scheduling delay time of each core in each core cluster in the multi-core cluster in a frame drawing period, respectively.

In yet another embodiment, the scheduling unit is further configured to:

monitoring the number of ready tasks in each core cluster in the multi-core cluster in real time; and when the number of ready tasks in the core cluster exceeds a set task number threshold, and inactive cores exist in the core cluster with the number of ready tasks exceeding the set task number threshold, activating the inactive cores.

According to a third aspect of the embodiments of the present disclosure, there is provided a CPU core scheduling apparatus, including:

a processor; a memory for storing processor-executable instructions; wherein the processor is configured to: the CPU core scheduling method described in the first aspect or any implementation manner of the first aspect is executed.

According to a fourth aspect of the disclosed embodiments, there is provided a non-transitory computer readable storage medium, which when executed by a processor of a mobile terminal, enables the mobile terminal to perform the CPU core scheduling method of the first aspect or any implementation of the first aspect.

The technical scheme provided by the embodiment of the disclosure can comprise the following beneficial effects: and determining the scheduling delay time of each core in each core cluster in the frame drawing period, and scheduling the tasks with the scheduling delay time exceeding the designated delay time threshold value in the core clusters of each core to other core clusters based on the scheduling delay time of each core so as to reduce the scheduling delay in a heavy load scene, reduce the blocking and improve the use experience.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure.

FIG. 1 is a flowchart illustrating a method of CPU core scheduling, according to an exemplary embodiment.

FIG. 2 is a task distribution diagram of a Mid cluster and a Big cluster, as shown in an exemplary embodiment.

FIG. 3 is a task profile illustrating enqueuing of additional tasks in accordance with an exemplary embodiment.

FIG. 4 is a task scheduling diagram according to the Mid cluster and Big cluster shown in an exemplary embodiment.

Fig. 5 is a schematic diagram illustrating a process of performing core activation based on a fixed time window in accordance with the related art as shown in an exemplary embodiment.

FIG. 6 is a schematic diagram of a process for monitoring the number of tasks and activating the kernel in real time based on a frame drawing period, as shown in an exemplary embodiment.

FIG. 7 is a block diagram illustrating a CPU core scheduler in accordance with an exemplary embodiment.

FIG. 8 is a block diagram illustrating an apparatus for CPU core scheduling, according to an example embodiment.

Detailed Description

Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples are not representative of all implementations consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present disclosure as detailed in the accompanying claims.

The CPU kernel scheduling method provided by the embodiment of the disclosure is applied to the terminal provided with the frame drawing application. The frame drawing class has a frame drawing period during operation. The frame drawing period can be understood as the display interval of two adjacent frames of images.

In the embodiment of the disclosure, the frame drawing class application may be an APP class application installed on the terminal, for example, the frame drawing class application may be a game. The embodiments of the present disclosure will be described below by taking a frame drawing application as an example of a game, and of course, the embodiments of the present disclosure are not limited to the frame drawing application as a game application, but may be other applications.

The terminal with the frame drawing class application installed in the embodiment of the disclosure supports a multi-core cluster platform architecture, such as a 3-cluster platform architecture.

In the embodiment of the disclosure, a multi-core cluster platform architecture is taken as an example to describe a 3-cluster platform architecture.

In a system supporting a 3-cluster platform architecture, a small-core cluster (Little cluster) composed of small cores, a middle-core cluster (Mid cluster) composed of middle cores and a large-core cluster (Big cluster) composed of large cores are included, and kernel performance indexes on different clusters are different. The kernel on the Big cluster has the highest performance index, which can provide the largest cpu performance, but the power consumption overhead is also the largest. The kernel on the Little cluster has the optimal power consumption performance, but cannot meet the performance requirements of the high-load scene. The kernel on the Mid cluster has performance and power consumption between Big-Little. To account for this discrepancy, the scheduler may bind different capability indicators to the kernels on different clusters. For example, the capability index of the large core is set to 1000, the capability index of the medium core is set to 800, and the capability index of the small core is set to 400. Thus, when a certain task wakes up for enqueuing, a cluster meeting the performance requirement can be selected according to the historical load value of the enqueuing task. And selects the appropriate core to perform the task. The task load in the operating system is approximately equal to the task run time within a fixed window period and is updated at the end of each window period.

For convenience of description, the load of the task is set to be equal to the running time of the task in the embodiment of the disclosure, and the time is agreed to be a standardized value, regardless of the running frequency of the CPU on which the task runs and the value of Inter-process communication (Inter-Process Communication, IPC).

In the related art, aiming at a CPU kernel scheduling scheme supporting a 3-cluster platform architecture, the following logic is adopted to select a target CPU kernel: when a certain task wakes up for enqueuing, sequentially checking whether the load value of the task for waking up for enqueuing is smaller than or equal to the set percentage threshold value of the capability index of the cluster to be checked according to the arrangement sequence of the Little-Mid cluster. The load value of the wake-up enqueuing task is smaller than or equal to the set percentage threshold value of the cluster ability index to be inspected, and the cluster to be inspected can be determined to meet the performance requirement of the current task, so that a proper CPU core can be selected from the cluster meeting the performance requirement of the current task to execute the task. And if the load value of the wake-up enqueuing task is larger than the set percentage threshold value of the capability index of the cluster to be examined, the cluster with better performance index is continuously searched until the condition is met or the CPU core in the Big cluster is inspected.

For simplifying the description, the embodiment of the disclosure simplifies the following model, and supposing that the window period length of load update is 100ms, the maximum performance index in the system is 1, the big cluster can reach the index of 100% performance, the Mid cluster can reach 80% at most, and the Little cluster can reach 40% at most.

According to the mode of carrying out CPU kernel scheduling in the related art, the following scheme can be adopted:

1: when the task load (running time) is not more than 100ms (window period length) (1×40% of maximum performance that the small core can provide) ×85% (threshold percentage) =34 ms, the task will run on the core of the Little cluster.

2: the task load (running time) is not more than 100ms (window period length) (1×80% of maximum performance that the small core can provide) ×85% (threshold percentage) =68 ms, and above 34ms, the task will run onto the core of the Mid cluster.

3: when the task load (run time) exceeds 68ms, the task will run on the kernel of the Big cluster.

However, in the scene of actually running a frame drawing application such as a game, when a frame loss is found, a composite scene with very low kernel utilization rate of a Big cluster and very high Mid cluster scheduling delay exists. The analysis of the reasons is mainly caused by the fact that the use conditions of the large cores are severely limited, and tasks are unevenly distributed among different clusters due to inflexibility. For example, when a large number of ready tasks with loads between 34 and 68 occur for a certain period of time in the system, because the number of tasks far exceeds the number of cores available in the Mid cluster and does not have the conditions to schedule to the Big cluster, the backlog of most tasks on the Mid cluster is caused. Similarly, when a large number of ready tasks with loads higher than 68 occur in the system for a certain period of time, the tasks of the large cores are backlogged, and high scheduling delay is caused.

In summary, during the process of performing CPU core scheduling in the multi-core cluster platform architecture, there are phenomena such as blocking caused by task scheduling delay.

In view of this, an embodiment of the present disclosure provides a method for scheduling CPU cores, in which a scheduling delay time of each core in each cluster is determined in a frame drawing period, and based on the scheduling delay time of each core, a specified number of tasks in clusters, in which the scheduling delay time of each core exceeds a specified delay time threshold, are scheduled to other clusters, so as to reduce scheduling delay in a heavy load scenario, reduce blocking, and improve use experience.

Fig. 1 is a flowchart illustrating a method for scheduling a CPU core for use in a terminal on which a frame drawing class application is installed, and a CPU of the terminal supporting a multi-core cluster platform architecture, for example, supporting a 3-cluster platform architecture, according to an exemplary embodiment.

As shown in fig. 1, the CPU core scheduling method includes the following steps.

In step S11, the scheduling delay time of each core in each of the multi-core clusters is determined in the frame drawing period, respectively.

In step S12, if there are clusters whose scheduling delay times of the cores exceed the specified delay time threshold, the specified number of tasks in the cluster are scheduled to other clusters.

For convenience of description in the embodiment of the present disclosure, a cluster in which the scheduling delay time of each core exceeds a specified delay time threshold is referred to as a first cluster. The other cluster to which the task in the first cluster is scheduled is called a second cluster. Wherein the second cluster is different from the first cluster, and the performance index is capable of satisfying the task scheduled from the first cluster.

In the embodiment of the disclosure, if the first cluster that the scheduling delay time of each core exceeds the specified delay time threshold is monitored, it may be determined that task backlog on the first cluster results in an increase in scheduling delay. The task scheduling method has the advantages that the task scheduling method can realize active balancing of the ready task number of each cluster by scheduling the task on the first cluster on the second cluster, so that the problem of frame loss caused by uneven task allocation is avoided.

The CPU core scheduling method according to the above embodiment will be described in connection with practical applications.

In an example of the present disclosure, when a new task is enqueued or task scheduling is switched, scheduling delay time of each core in each cluster in the multi-cluster can be respectively determined in a frame drawing period, so as to implement balanced scheduling of CPU cores in time when the new task is enqueued or task scheduling is performed.

In another example of the present disclosure, a weight value for running tasks in each cluster in the multi-cluster is determined according to the task load size and the importance level. The task weight value with high load is higher than the task weight value with low load, the task weight value with high importance degree is higher than the task weight value with low importance degree, and finally the task weight value with high importance degree is higher as the load is higher.

In the embodiment of the present disclosure, when the weight value of the task is determined, the task of the designated number in the first cluster may be scheduled to the second cluster according to the weight value of each task in the first cluster. For example, the embodiments of the present disclosure may schedule the specified number of tasks in the first cluster to the second cluster in the order in which the weight values of the tasks are from high to low.

It is understood that the number of tasks scheduled from the first cluster in the embodiments of the present disclosure may be determined according to the performance indexes of the first cluster and the second cluster, the scheduling delay time, and so on. For example, if the scheduling delay time of the first cluster is very large and the performance index of the second cluster is high, a larger number of tasks may be scheduled into the second cluster. The scheduling delay time of the first cluster is smaller, and the performance index of the second cluster is lower, so that the tasks with smaller quantity can be scheduled into the second cluster.

In an example, in the embodiment of the present disclosure, to implement better kernel scheduling balance, the second may be a cluster higher than the first cluster in the multi-cluster, for example, the first cluster is a littlecluster, and the second cluster may be a Mid cluster or a Big cluster. In an embodiment of the present disclosure, the embodiment may be a Big cluster with the highest performance index in multiple clusters, so as to realize the direct migration of related tasks to oversized core processing once the rapid increase of the load in a short period is monitored by monitoring the heavy load task in the frame drawing period in real time.

In another example, in order to implement better core scheduling balance, the second embodiment of the disclosure may be a cluster in which the sum of the scheduling delay times of the cores in the 3-cluster is smaller than the sum of the scheduling delay times of the cores in the first cluster. For example, in the embodiment of the present disclosure, if the first cluster is a Big cluster, the second cluster may be a Little cluster or a Mid cluster, so as to avoid higher scheduling delay caused by backlog of large-core tasks.

In the embodiment of the disclosure, the threads in the frame drawing class application are ordered according to the load size and importance by counting and tracking the load change of the threads to which the frame drawing class application belongs in each frame drawing period in real time. The greater the load, the greater the thread weight value of higher importance. When the scheduling delay increase caused by the task backlog on a certain cluster is monitored, the ready task number of each cluster is actively balanced, so that the problem of frame loss caused by uneven task allocation is avoided.

In an exemplary application scenario, the method is applied to a 3-cluster platform architecture. If a game scene is in progress, the task distribution of the current Mid cluster and Big cluster is shown in fig. 2. FIG. 2 is a task distribution diagram of a Mid cluster and a Big cluster shown in an exemplary embodiment. In FIG. 2, there are 3 kernels running on the Mid cluster: kernel 0, kernel 1, and kernel 2. And the task queues running on the kernel 0, the kernel 1 and the kernel 2 are respectively task 1, task 2, task 3, task 1, task 2, task 3 and task 1, task 2. The Big cluster has 1 kernel running on it: kernel 0. There is no running task queue on core 0. When task a, task B and task C are awakened for new enqueue, these three types of task loads (run time) are between 34 and 68 according to the task allocation principles in the related art, and therefore are queued into the run queues on the Mid cluster, as shown in fig. 3. However, according to the method for scheduling CPU cores provided in the embodiments of the present disclosure, at this time, the total scheduling delay time of three cores on the Mid cluster is relatively high, so that a specified number of tasks are pumped out and scheduled to the Big cluster, for example, as shown in fig. 4, task 1 on core 0 and task B on core 1 are scheduled to the Big cluster, so as to realize active balancing of the ready task numbers of each cluster, thereby avoiding the problem of frame loss caused by uneven task allocation.

Further, in the embodiment of the present disclosure, to better balance the number of ready tasks of each cluster, the number of ready tasks in each cluster may be monitored in real time during a frame drawing period, and if there is a number of ready tasks exceeding a threshold of the set number of tasks and there is an inactive core in a cluster whose number of ready tasks exceeds the threshold of the set number of tasks, the inactive core is activated.

In the embodiment of the disclosure, the number of ready tasks in each cluster is monitored in real time in a frame drawing period, and when the number of ready tasks exceeds a set task number threshold, more clusters are activated in real time to process tasks, so that the method is suitable for situations in which the number of ready tasks suddenly increases, for example, situations in which the number of ready tasks suddenly increases at a certain moment due to scene change and the like in a game, more kernels are activated in real time to process the suddenly increased tasks, and scheduling delay and frame loss can be reduced.

The following describes the above-mentioned scheduling manner based on real-time monitoring of the number of ready tasks and activation of inactive kernels in a frame drawing period with reference to practical applications.

Fig. 5 is a schematic diagram of a process of performing core activation based on a fixed time window in the related art. Assuming a fixed time window length of 100ms in fig. 5, the average number of ready tasks per current time period is monitored and the dynamic up-down of the kernel is performed. In fig. 5, at the time point when the number of tasks increases suddenly, the time point of adjusting the on-line and off-line of the kernel is not reached, so that the task of the kernel activation process increases suddenly in time cannot be performed, and scheduling delay and frame loss occur.

FIG. 6 is a schematic diagram of a process for monitoring the number of tasks and activating the kernel in real time based on a frame drawing period in an exemplary embodiment of the present disclosure. In fig. 6, when a new task enters an operation queue in a cluster in a certain frame drawing period, the monitoring time is increased, if the scheduling congestion condition of the operation queue exceeds a certain threshold, the unactivated kernel in the cluster is immediately activated, and more kernels are activated in real time to process the suddenly increased task, so that scheduling delay and frame loss can be reduced.

The CPU kernel scheduling method provided by the embodiment of the disclosure is a general and independent load real-time monitoring and multi-core calling method. By applying real-time monitoring of heavy load tasks to frame drawing types such as games, once the rapid increase of the load in a short period is monitored, related tasks are directly migrated to other suitable clusters for processing, such as ultra-large core processing, and the number of available cores in a system is timely adjusted according to the real-time number of heavy load threads monitored in real time, so that scheduling delay in a heavy load scene is reduced, game experience is improved, and blocking is reduced.

Based on the same conception, the embodiment of the disclosure also provides a CPU core scheduling device.

It can be appreciated that, in order to implement the above functions, the CPU core scheduling apparatus provided in the embodiments of the present disclosure includes a hardware structure and/or a software module that perform each function. The disclosed embodiments may be implemented in hardware or a combination of hardware and computer software, in combination with the various example elements and algorithm steps disclosed in the embodiments of the disclosure. Whether a function is implemented as hardware or computer software driven hardware depends upon the particular application and design constraints imposed on the solution. Those skilled in the art may implement the described functionality using different approaches for each particular application, but such implementation is not to be considered as beyond the scope of the embodiments of the present disclosure.

FIG. 7 is a block diagram illustrating a CPU core scheduler in accordance with an exemplary embodiment. Referring to fig. 7, a CPU core scheduling apparatus 700 is applied to a terminal on which a frame drawing class application is installed, and the CPU of the terminal supports a multi-core cluster platform architecture. The CPU core scheduling apparatus 700 includes a determination unit 701 and a scheduling unit 702.

A determining unit 701, configured to determine a scheduling delay time of each core in each core cluster in the multi-core clusters in a frame drawing period. A scheduling unit 702, configured to schedule a specified number of tasks in the first cluster to the second cluster when the scheduling delay time of each core in the first cluster exceeds a specified delay time threshold. The second cluster is different from the first cluster, and the performance index meets the requirement of running the specified number of tasks.

In one embodiment, the scheduling unit 702 is further configured to: and determining the weight value of the running task in each core cluster in the multi-core clusters according to the load size and the importance degree of the task. The task weight value with high load is higher than the task weight value with low load, and the task weight value with high importance degree is higher than the task weight value with low importance degree.

In another embodiment, the scheduling unit 702 schedules the specified number of tasks in the first cluster to the second cluster in the order of the weight values of the tasks from high to low.

In yet another embodiment, the second cluster is a larger core cluster having a higher index than the first cluster in the multi-core cluster, and/or the second cluster is a core cluster having a sum of scheduling delay times for each core in the multi-core cluster that is less than a sum of scheduling delay times for each core in the first cluster.

In yet another embodiment, when there is a new task enqueue or task scheduling switch, the determining unit 701 determines the scheduling delay time of each core in each core cluster in the multi-core clusters in the frame drawing period, respectively.

In yet another embodiment, the scheduling unit 102 is further configured to: and monitoring the number of ready tasks in each core cluster in the multi-core cluster in real time. And when the number of ready tasks in the core cluster exceeds a set task number threshold, and the inactive cores exist in the core cluster with the number of ready tasks exceeding the set task number threshold, activating the inactive cores.

According to the CPU core scheduling device provided by the embodiment of the disclosure, the scheduling delay time of each core in each core cluster is determined in the frame drawing period, and based on the scheduling delay time of each core, the tasks with the scheduling delay time exceeding the designated delay time threshold in the core cluster of each core are scheduled to other core clusters, so that the scheduling delay in a heavy load scene is reduced, the blocking is reduced, and the use experience is improved.

The specific manner in which the various modules perform the operations in the apparatus of the above embodiments have been described in detail in connection with the embodiments of the method, and will not be described in detail herein.

FIG. 8 is a block diagram illustrating an apparatus 800 for CPU core scheduling, according to an example embodiment. For example, apparatus 800 may be a mobile phone, computer, digital broadcast terminal, messaging device, game console, tablet device, medical device, exercise device, personal digital assistant, or the like.

Referring to fig. 8, apparatus 800 may include one or more of the following components: a processing component 802, a memory 804, a power component 806, a multimedia component 808, an audio component 810, an input/output (I/O) interface 812, a sensor component 814, and a communication component 816.

The processing component 802 generally controls overall operation of the apparatus 800, such as operations associated with display, telephone calls, data communications, camera operations, and recording operations. The processing component 802 may include one or more processors 820 to execute instructions to perform all or part of the steps of the methods described above. Further, the processing component 802 can include one or more modules that facilitate interactions between the processing component 802 and other components. For example, the processing component 802 can include a multimedia module to facilitate interaction between the multimedia component 808 and the processing component 802.

The memory 804 is configured to store various types of data to support operations at the device 800. Examples of such data include instructions for any application or method operating on the device 800, contact data, phonebook data, messages, pictures, videos, and the like. The memory 804 may be implemented by any type or combination of volatile or nonvolatile memory devices such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic or optical disk.

The power component 806 provides power to the various components of the device 800. The power components 806 may include a power management system, one or more power sources, and other components associated with generating, managing, and distributing power for the device 800.

The multimedia component 808 includes a screen between the device 800 and the user that provides an output interface. In some embodiments, the screen may include a Liquid Crystal Display (LCD) and a Touch Panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from a user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensor may sense not only the boundary of a touch or slide action, but also the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 808 includes a front camera and/or a rear camera. The front camera and/or the rear camera may receive external multimedia data when the device 800 is in an operational mode, such as a shooting mode or a video mode. Each front camera and rear camera may be a fixed optical lens system or have focal length and optical zoom capabilities.

The audio component 810 is configured to output and/or input audio signals. For example, the audio component 810 includes a Microphone (MIC) configured to receive external audio signals when the device 800 is in an operational mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signals may be further stored in the memory 804 or transmitted via the communication component 816. In some embodiments, audio component 810 further includes a speaker for outputting audio signals.

The I/O interface 812 provides an interface between the processing component 802 and peripheral interface modules, which may be a keyboard, click wheel, buttons, etc. These buttons may include, but are not limited to: homepage button, volume button, start button, and lock button.

The sensor assembly 814 includes one or more sensors for providing status assessment of various aspects of the apparatus 800. For example, the sensor assembly 814 may detect an on/off state of the device 800, a relative positioning of the components, such as a display and keypad of the apparatus 800, the sensor assembly 814 may also detect a change in position of the apparatus 800 or one component of the apparatus 800, the presence or absence of user contact with the apparatus 800, an orientation or acceleration/deceleration of the apparatus 800, and a change in temperature of the apparatus 800. The sensor assembly 814 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. The sensor assembly 814 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 814 may also include an acceleration sensor, a gyroscopic sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

The communication component 816 is configured to facilitate communication between the apparatus 800 and other devices, either in a wired or wireless manner. The device 800 may access a wireless network based on a communication standard, such as WiFi,2G or 3G, or a combination thereof. In one exemplary embodiment, the communication component 816 receives broadcast signals or broadcast related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, the communication component 816 further includes a Near Field Communication (NFC) module to facilitate short range communications. For example, the NFC module may be implemented based on Radio Frequency Identification (RFID) technology, infrared data association (IrDA) technology, ultra Wideband (UWB) technology, bluetooth (BT) technology, and other technologies.

In an exemplary embodiment, the apparatus 800 may be implemented by one or more Application Specific Integrated Circuits (ASICs), digital Signal Processors (DSPs), digital Signal Processing Devices (DSPDs), programmable Logic Devices (PLDs), field Programmable Gate Arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic elements for executing the methods described above.

In an exemplary embodiment, a non-transitory computer readable storage medium is also provided, such as memory 804 including instructions executable by processor 820 of apparatus 800 to perform the above-described method. For example, the non-transitory computer readable storage medium may be ROM, random Access Memory (RAM), CD-ROM, magnetic tape, floppy disk, optical data storage device, etc.

It is further understood that the term "plurality" in this disclosure means two or more, and other adjectives are similar thereto. "and/or", describes an association relationship of an association object, and indicates that there may be three relationships, for example, a and/or B, and may indicate: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship. The singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It is further understood that the terms "first," "second," and the like are used to describe various information, but such information should not be limited to these terms. These terms are only used to distinguish one type of information from another and do not denote a particular order or importance. Indeed, the expressions "first", "second", etc. may be used entirely interchangeably. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the present disclosure.

It will be further understood that although operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing may be advantageous.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any adaptations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

It is to be understood that the present disclosure is not limited to the precise arrangements and instrumentalities shown in the drawings, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. The CPU kernel scheduling method is characterized by being applied to a terminal, wherein a frame drawing application is installed on the terminal, the CPU of the terminal supports a multi-core cluster platform architecture, and the CPU kernel scheduling method comprises the following steps:

respectively determining the scheduling delay time of each core in each core cluster in the multi-core clusters in a frame drawing period;

if the scheduling delay time of each kernel in the first cluster exceeds a specified delay time threshold, scheduling the tasks with the specified number in the first cluster into a second cluster;

the second cluster is other clusters different from the first cluster in the multi-core cluster, and the performance index meets the requirement of running the specified number of tasks;

the specified number of tasks is determined according to the performance indexes of the first cluster and the second cluster and the scheduling delay time.

2. The CPU core scheduling method of claim 1, wherein the CPU core scheduling method further comprises:

determining a weight value of an operation task in each core cluster in the multi-core clusters according to the load size and the importance degree of the task;

the task weight value with high load is higher than the task weight value with low load, and the task weight value with high importance degree is higher than the task weight value with low importance degree.

3. The CPU core scheduling method of claim 2, wherein scheduling the specified number of tasks in the first cluster into a second cluster comprises:

4. A method of scheduling CPU cores according to any one of claims 1 to 3, wherein the second cluster is a larger core cluster of the multi-core cluster having a higher index than the first cluster, and/or wherein the second cluster is a core cluster of the multi-core cluster having a sum of scheduling delay times for respective cores of the multi-core cluster that is less than a sum of scheduling delay times for respective cores of the first cluster.

5. The CPU core scheduling method of claim 1, wherein when there is a new task enqueue or task scheduling switch, a scheduling delay time of each core in each core cluster in the multi-core cluster is determined in a frame drawing period, respectively.

6. The CPU core scheduling method of claim 1, wherein the CPU core scheduling method further comprises:

monitoring the number of ready tasks in each core cluster in the multi-core cluster in real time;

and if the number of the ready tasks in the core cluster exceeds the set task number threshold, and the unactivated cores exist in the core cluster with the number of the ready tasks exceeding the set task number threshold, activating the unactivated cores.

7. The CPU core scheduling method of claim 1, wherein the multi-core cluster platform architecture is a tri-core cluster platform architecture.

8. The utility model provides a CPU kernel scheduling device which characterized in that is applied to the terminal, install the frame on the terminal and draw class application, and the CPU of terminal supports many core cluster platform framework, CPU kernel scheduling device includes:

a determining unit, configured to determine a scheduling delay time of each core in each core cluster in the multi-core clusters in a frame drawing period;

the scheduling unit is used for scheduling the tasks with the appointed number in the first cluster to the second cluster when the scheduling delay time of each kernel in the first cluster exceeds the appointed delay time threshold;

wherein the second cluster is a different cluster than the first cluster, and the performance index satisfies the task running the specified number of tasks;

9. The CPU core scheduling apparatus of claim 8, wherein the scheduling unit is further configured to:

10. The CPU core scheduling apparatus according to claim 9, wherein the scheduling unit schedules the specified number of tasks in the first cluster into the second cluster by:

11. The CPU core scheduling apparatus according to any one of claims 8 to 10, wherein the second cluster is a larger core cluster of the multi-core cluster having a higher index than the first cluster, and/or wherein the second cluster is a core cluster of the multi-core cluster having a sum of scheduling delay times of cores of the multi-core cluster smaller than a sum of scheduling delay times of cores of the first cluster.

12. The CPU core scheduling apparatus according to claim 8, wherein the determining unit determines the scheduling delay time of each core in each core cluster in the multi-core cluster, respectively, in a frame drawing period when there is a new task enqueue or task scheduling switch.

13. The CPU core scheduling apparatus of claim 8, wherein the scheduling unit is further configured to:

and when the number of ready tasks in the core cluster exceeds a set task number threshold, and inactive cores exist in the core cluster with the number of ready tasks exceeding the set task number threshold, activating the inactive cores.

14. The CPU core scheduling apparatus of claim 8, wherein the multi-core cluster platform architecture is a three-core cluster platform architecture.

15. A CPU core scheduler, comprising:

a processor;

a memory for storing processor-executable instructions;

wherein the processor is configured to: a CPU core scheduling method according to any one of claims 1 to 7.

16. A non-transitory computer readable storage medium, which when executed by a processor of a mobile terminal, causes the mobile terminal to perform the CPU core scheduling method of any one of claims 1 to 7.