CN111193934A - Intra-frame prediction method, system, computer equipment and readable storage medium - Google Patents
Intra-frame prediction method, system, computer equipment and readable storage medium Download PDFInfo
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Abstract
The invention discloses an intra-frame prediction method, a system, computer equipment and a readable storage medium, which relate to the field of video coding and decoding and the technical field of digital chips and comprise the following steps: writing in an initial pixel, dividing LCUs, predicting and reconstructing a first CU, updating a register, predicting and reconstructing other CUs, traversing all CUs, and repeating the step of updating the register and the step of predicting and reconstructing other CUs until all CUs finish predicting and reconstructing. The method provided by the invention adopts the new reference pixel to cover a large number of reference pixels which are only read once, occupies the original storage space, does not need to newly develop a storage space to store the new reference pixel, and realizes the purpose of reducing the on-chip storage space.
Description
Technical Field
The invention relates to the field of video coding and decoding and the technical field of digital chips, in particular to an intra-frame prediction method, an intra-frame prediction system, computer equipment and a readable storage medium.
Background
Hevc (high Efficiency Video coding) is a new Video coding standard published in 2013 by the organization jctvc (joint Video Team) formed by the union of ITU (international telecommunication union, international telecommunication organization) and MPEG (Moving Picture Experts Group). Compared with the previous generation video coding standard, i.e., H.264/AVC, the goal is to reduce the compression rate by a factor of two at the same visual quality.
Video coding mainly utilizes various coding tools to remove spatial redundancy, temporal redundancy, information redundancy and the like of video information, realizes a compression effect, and is beneficial to storage, transmission and the like. The HEVC video coding standard extends the basic methods of previous generation coding standards such as block-based coding, intra prediction, inter prediction, transform quantization, loop filtering, entropy coding, etc. The intra-frame prediction is mainly a method for predicting the content of the residual video frame by using the content of the current video frame which is coded, so that a large amount of video spatial redundancy is removed. In HEVC, intra prediction is performed on a block basis, and a square block is formed by a plurality of pixels as a prediction unit. The prediction value calculation of the current prediction block requires the prediction mode of the current block and surrounding reference pixels. Where the prediction mode is input by the front end and the reference pixels need to be managed by the current module. In the HEVC standard, a total of five reconstructed pixels located in close proximity to the current block are used as reference pixels of the current block, namely, top right, top left, and bottom left, as shown in fig. 1. After the current block completes the prediction and reconstruction process, the obtained reconstructed pixels are still partially stored, and are used as reference pixels of other next prediction blocks, and the reconstructed pixels to be stored are located in the rightmost column and the lowermost row of the current block, as shown in fig. 1.
In order to further improve coding efficiency, a coding block partitioning manner of a quadtree is introduced in HEVC, where the largest coding block may be 64 × 64. At the encoding end, the 4 coding blocks 32 × 32 may be selected according to the coding efficiency, or the division may not be continued. For a 32 × 32 coding block, it is also possible to choose to continue dividing into 4 16 × 16 coding blocks. Doing so in sequence, the minimum coding block size may be 4 × 4. At the decoding end, the division mode of the current 64 × 64 block is determined, and only the corresponding intra-frame prediction needs to be performed according to the size of the current block. In the intra-frame prediction calculation process of a maximum block 64 × 64, both an encoding end and a decoding end need to repeat reference pixel writing and reading for many times and the storage requirement of a large number of reference pixels, so that the hardware cost is high, the speed is low, and the method becomes one of the key bottlenecks of hardware design of real-time high-speed video encoding and decoding.
Disclosure of Invention
In order to solve the problems, the invention provides an intra-frame prediction method, which is used for overcoming the defects of a reference pixel storage method in the prior art, efficiently utilizing chip resources, improving the storage efficiency of reference pixels and meeting the requirements of high-definition and high-speed video coding and decoding.
In order to achieve the purpose, the invention adopts the following technical scheme:
an intra prediction method, comprising the steps of:
writing an initial pixel: storing N/2 pixels on the left side of the LCU at N x N in a horizontal register, wherein the N/2 pixels are counted from the topmost end of the LCU; storing N pixels on the upper side of the LCU at N x N in a vertical register; storing pixels located at the upper left corner of the LCU at N x N in an upper left register;
dividing: dividing the LCU of N by N into a plurality of CUs;
first CU prediction and reconstruction: reading pixels of the reference pixels of the CU at the upper left corner in the corresponding positions of the horizontal register, the vertical register and the upper left register, and predicting and reconstructing the CU at the upper left corner based on the read pixels;
updating a register: updating the pixels in the lowest row of the reconstructed CU to a horizontal register, updating the pixels in the rightmost column of the reconstructed CU to a vertical register, covering the pixels stored in the corresponding position of the horizontal register or the vertical register during updating, and updating the pixels of the corresponding position of the upper left reference pixel of the divided CU in the rightmost column of the reconstructed CU to an upper left register according to the division of the LCU;
other CU prediction and reconstruction: predicting the next CU, reading pixels of the reference pixel of the current CU at corresponding positions in the updated horizontal register, the updated vertical register and the updated upper left register, and predicting and reconstructing the current CU based on the read pixels;
and traversing all CUs, and repeating the step of updating the register and the step of predicting and reconstructing other CUs until all CUs finish predicting and reconstructing.
Optionally, in the step of traversing all CUs, prediction and reconstruction are sequentially performed according to the zig-zag order.
Optionally, the abscissa of the CU is the corresponding positions of the upper right reference pixel and the upper reference pixel of the CU in the horizontal register; the lower three bits of the ordinate of the CU are corresponding positions of a left reference pixel and a lower left reference pixel of the CU in the vertical register; the lower three bits of the ordinate of the CU are the corresponding positions of the upper left reference pixel of the CU in the upper left register, and only one pixel is read.
Optionally, the read and write address calculation formula of the horizontal register is:
wherein x is the abscissa of the current CU; CUSize is the current CU size, horiAddr is the horizontal register read and write address, and horiSize is the horizontal register read and write pixel number;
the read and write address calculation formula for the vertical register is:
wherein y is the ordinate of the current CU; CUSize is the current CU size, VertADDr is the vertical register read and write address, and VertSize is the vertical register read and write pixel number;
the read and write address calculation formula for the top left register is:
wherein TplfAddr is the upper left register read and write address, TplfSize is the number of pixels read and write to the upper left register.
Optionally, when the CU at the top left corner is 32 × 32, the bottom left reference pixel of the CU at the top left corner is 32 pixels located at the left side of the LCU of 64 × 64, and the 32 pixels are counted from the top of the LCU.
Optionally, the LCU of N × N is one of an LCU of 64 × 64, an LCU of 32 × 32, and an LCU of 16 × 16.
Optionally, in the other CU predicting and reconstructing step, if the read pixel is invalid for the current CU, the read pixel of the current CU is filled in.
The invention has the following beneficial effects:
according to the technical scheme provided by the invention, the method for greatly reducing the storage space required by the reference pixel is determined according to the use characteristics of the reference pixel in the intra-frame prediction process. In the prior art, after a 64 × 64 LCU is divided, the rightmost column and the bottommost row of all CUs need to be stored for prediction of other blocks, if all the reference pixels of the CU are stored, when the 64 × 64 LCU is divided into 4 × 4 CUs, the required storage space is the largest, and a space of at least 1792 pixels is required, wherein 265 upper left reference pixels, 768 upper right reference pixels and upper reference pixels, and 768 left reference pixels and lower left reference pixels are required. Because only the worst storage requirement, i.e. all the CUs divided into 4 × 4, is satisfied, the storage requirements of other divisions can be satisfied. This causes the need of writing and reading reference pixels and storing a large number of reference pixels, which need to be repeated many times at both the encoding end and the decoding end, resulting in the disadvantages of high hardware overhead and low speed. And the calculation of the prediction value of the current CU is based on the reference pixels generated by the previously reconstructed CU. However, since the reference pixels only adopt one row and one column of pixels around the current block, and the pixels at other positions are not referred to, a large number of reference pixels can be used only once and can not be used any more later, so that the reference pixels which are read once are covered by new reference pixels, the original storage space is occupied, and the storage space is not required to be newly opened up to store the new reference pixels, so as to achieve the purpose of reducing the on-chip storage space.
In the present invention, only a space of 32 pixels in one column is needed for the storage of the reference pixels at the left and lower left (vertical register), and a space of 64 pixels in one row is needed for the storage of the reference pixels at the upper and upper right (horizontal register), plus the storage space of 8 reference pixels at the upper left (upper left register), so that the reference pixel management of the entire 64 × 64 LCU can be realized. A total of only 32 + 64 + 8 = 104 pixels is needed for reference pixel storage, and 1792 are not needed, which greatly reduces the on-chip storage space requirement and thus reduces the chip area.
Meanwhile, only the storage space of 104 pixels is needed, the storage of the reference pixels is realized in a register file mode finally, and an SRAM (static random access memory) is not needed, so that the read-write complexity of the reference pixels is further reduced, and the processing speed is increased. In the implementation of the SRAM, only N pixels in one memory block can be read in one clock cycle, generally N =4, so that the clock cycles required for reading and writing the reference pixels of different CUs are different, that is, in the implementation of the SRAM, at least 4 clock cycles are required to complete the reading or writing. The management of horizontal, vertical and upper left reference pixels is realized by adopting a register pair mode, the reference pixels at corresponding positions can be directly written into corresponding registers for CUs of various sizes, and all the required reference pixels can be completely read or written in one period, so that the reading and writing time of the reference pixels is remarkably reduced, the intra-frame prediction is accelerated, and the requirements of high-definition and high-speed video coding and decoding are favorably met.
In addition, the present invention also provides an intra prediction system, comprising:
and the register comprises a horizontal register, a vertical register and an upper left register, wherein the horizontal register is used for storing pixels at positions corresponding to the upper reference pixel and the upper right reference pixel of the CU as the upper reference pixel and the upper right reference pixel of the CU, the vertical register is used for storing pixels at positions corresponding to the left reference pixel and the lower left reference pixel of the CU as the left reference pixel and the lower left reference pixel of the CU, and the upper left register is used for storing pixels at positions corresponding to the upper left reference pixel of the CU as the upper left reference pixel of the CU.
The partitioning module is used for partitioning the LCU into a plurality of CUs for prediction and reconstruction;
the reading and writing module is used for reading pixels of the reference pixels of the current CU at corresponding positions in the horizontal register, the vertical register and the upper left register as the reference pixels of the current CU, updating the pixels of the lowest row of the reconstructed CU to the horizontal register, updating the pixels of the rightmost column of the reconstructed CU to the vertical register, covering the stored pixels at the corresponding positions of the horizontal register or the vertical register during updating, and updating the pixels of the divided upper left reference pixels of the CU at the corresponding positions in the vertical register to the upper left register according to the division of the LCU;
and the prediction and reconstruction module is used for predicting and reconstructing the current CU based on the read pixels.
The beneficial effect of the intra-frame prediction system provided by the invention is similar to the beneficial effect reasoning process of the intra-frame prediction method, and is not repeated herein.
Meanwhile, the invention also provides computer equipment which comprises a memory and a processor, wherein the memory stores a computer program, and the processor realizes the method of any one of the above items when executing the computer program.
Meanwhile, the invention also provides a computer readable storage medium, on which a computer program is stored, which when executed by a processor implements the method of any one of the above.
These features and advantages of the present invention will be disclosed in more detail in the following detailed description and the accompanying drawings. The best mode or means of the present invention will be described in detail with reference to the accompanying drawings, but the present invention is not limited thereto. In addition, the features, elements and components appearing in each of the following and in the drawings are plural and different symbols or numerals are labeled for convenience of representation, but all represent components of the same or similar construction or function.
Drawings
The invention will be further described with reference to the accompanying drawings in which:
fig. 1 is a schematic diagram of a HEVC reference pixel in the prior art.
FIG. 2 is a diagram illustrating pixel update and storage states of a horizontal register and a vertical register according to an embodiment of the invention.
Fig. 3 is a schematic diagram of a traversal order according to an embodiment of the present invention.
Detailed Description
The technical solutions of the embodiments of the present invention are explained and illustrated below with reference to the drawings of the embodiments of the present invention, but the following embodiments are only preferred embodiments of the present invention, and not all embodiments. Based on the embodiments in the implementation, other embodiments obtained by those skilled in the art without any creative effort belong to the protection scope of the present invention.
Reference in the specification to "one embodiment" or "an example" means that a particular feature, structure or characteristic described in connection with the embodiment itself may be included in at least one embodiment of the patent disclosure. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment.
Example one
As shown in fig. 2 and fig. 3, the present embodiment provides an intra prediction method, where in the present embodiment, the LCU is 64 × 64, and the method specifically includes the following steps:
writing an initial pixel: storing 32 pixels to the left of the 64 x 64 LCU in a horizontal register, the 32 pixels counted from the top of the LCU; storing 64 pixels on the upper side of the 64 x 64 LCU in a vertical register; the pixel at the upper left corner of the 64 x 64 LCU is stored in the upper left register.
Dividing: the 64 x 64 LCU is divided into CUs. In the present embodiment, the division is performed in a manner as shown in fig. 2, where 64 × 64 LCU is divided into 4 32 × 32 CUs, 32 × 32CU positioned at the upper right is divided into 4 16 × 16 CUs, and 16 × 16 CU positioned at the lower left is divided into 4 8 × 8 CUs, and for convenience of description, in the present embodiment, 32 × 32CU positioned at the upper left is referred to as CU1, 16 × 16 CU positioned at the right side of CU1 is referred to as CU2, 16 × 16 CU positioned at the right side of CU2 is referred to as CU3, and 8 CU 8 positioned at the upper left corner among four 8 CU right sides of CU1 and the lower side of CU2 is referred to as CU 3.
First CU prediction and reconstruction: reading pixels of corresponding positions of the upper reference pixel and the upper right reference pixel of the CU1 in the horizontal register as the upper reference pixel and the upper right reference pixel of the CU 1; reading a pixel of a corresponding position of a top-left reference pixel of the CU1 in a top-left register as a top-left reference pixel of the CU 1; and reading the pixel of the corresponding position of the left reference pixel of the CU1 in the vertical register as the left reference pixel of the CU 1. When the CU at the top left corner is 32 × 32, the bottom left reference pixel of the CU at the top left corner 32 × 32 takes 32 pixels located to the left of the LCU at 64 × 64, and the 32 pixels are counted from the topmost end of the LCU. Since the upper left CU (i.e., CU 1) is 32 × 32 for the partition of the LCU in this embodiment, the lower left reference pixel of CU1 is the same as the left reference pixel of CU1 and is stored in the vertical register in the initial pixel writing step, the upper and upper right reference pixels of CU1 are stored in the horizontal register in the initial pixel writing step, and the upper left reference pixel of CU1 is stored in the upper left register in the initial pixel writing step. As shown in fig. 2, when the first CU prediction and reconstruction are performed, the pixels stored in the horizontal register are indicated by horizontal bars with left-oblique lines, and the pixels stored in the vertical register are indicated by vertical bars with left-oblique lines, and CU1 is predicted and reconstructed based on each read reference pixel.
Updating a register: and updating the pixels of the lowest row of the reconstructed CU to a horizontal register, updating the pixels of the rightmost column of the reconstructed CU to a vertical register, covering the pixels stored at the corresponding position of the horizontal register or the vertical register during updating, and updating the pixels of the corresponding position of the upper left reference pixel of the divided CU in the rightmost column of the reconstructed CU to the upper left register according to the division of the LCU. As shown in fig. 2, specifically in this embodiment, after the CU1 is reconstructed, the rightmost column of pixels and the bottommost row of pixels of the reconstructed CU1 are represented by a grid with a cross grid, the bottommost row of pixels of the reconstructed CU1 is updated to the horizontal register, and the pixels stored in the updated horizontal register include a horizontal bar with a cross grid and a horizontal bar with a left oblique line, because the pixel of the corresponding position of the upper left reference pixel of the CU2 in the rightmost column of pixels of the reconstructed CU1 is also updated, the pixel of the corresponding position of the upper left reference pixel of the CU2 in the rightmost column of pixels of the reconstructed CU1 is updated to the upper left register, and the pixel of the rightmost column of pixels of the reconstructed CU1 is updated to the vertical register, and the updated vertical register only includes a vertical bar with a cross grid.
Other CU prediction and reconstruction: predicting the next CU, reading pixels of the reference pixel of the current CU at corresponding positions in the updated horizontal register, the updated vertical register and the updated upper left register, and predicting and reconstructing the current CU based on the read pixels; specifically, in this embodiment, as shown in fig. 2, CU2 is predicted, pixels at corresponding positions in the updated horizontal register, vertical register and upper left register are read, the pixels stored in the horizontal register include horizontal bars with crossed grids and horizontal bars with left oblique lines, the vertical register includes only vertical bars with crossed grids, pixels at corresponding positions of the reference pixels of CU2 are read to reconstruct CU2, and after reconstruction, the rightmost column of pixels and the bottommost row of pixels are represented by horizontal bars and vertical bars with right oblique lines.
As shown in fig. 2, the horizontal register is updated again, the pixels in the bottom row of the reconstructed CU2 are updated to the horizontal register, and the pixels stored in the updated horizontal register include the horizontal bar with the cross grid, the horizontal bar with the right oblique line, and the horizontal bar with the left oblique line, and since the pixel at the corresponding position of the upper left reference pixel of the CU3 in the rightmost column of the pixels of the reconstructed CU2 is also updated, the pixel at the corresponding position of the upper left reference pixel of the CU3 in the rightmost column of the pixels of the reconstructed CU2 is updated to the upper left register, and the pixels at the right most column of the pixels of the reconstructed CU2 are updated to the vertical register, and the updated vertical register includes the vertical bar with the right oblique line and the vertical bar with the cross grid.
As shown in fig. 3, traversing all CUs in the zig-zag order, repeating the step of updating the registers and the other CU prediction and reconstruction steps, and sequentially predicting and reconstructing each CU, wherein in the reconstruction process, after the reconstruction is completed on CU3, the pixels stored in the horizontal register include horizontal bars with a cross grid, horizontal bars with a right oblique line, and blank horizontal bars, and since the pixels of the upper left reference pixel of CU4 in the corresponding position in the rightmost column of pixels of reconstructed CU3 are also updated, the pixels of the upper left reference pixel of CU4 in the corresponding position in the rightmost column of pixels of reconstructed CU3 are updated to the upper left register, and at the same time, the pixels of the rightmost column of pixels of reconstructed CU3 are updated to the vertical register, and the updated vertical register includes blank vertical bars and vertical bars with a cross grid.
And predicting and reconstructing a CU4 based on the horizontal register, the upper left register and the vertical register which are updated after reconstruction is completed by the CU3, and updating the horizontal register, the upper left register and the vertical register after the prediction and reconstruction of the CU4 are completed, wherein the specific steps are similar to the steps for predicting and reconstructing the CUs 1, the CUs 2 and the CUs 3 and updating the horizontal register, the upper left register and the vertical register, and are not repeated herein until all the CUs complete the prediction and reconstruction.
And in the predicting and reconstructing steps for other CUs, if the read pixel is invalid for the current CU, the read pixel of the current CU is filled in by the other read pixels of the current CU. And selecting the effective pixel closest to the read ineffective pixel to fill the currently read ineffective pixel by adopting a proximity principle during filling. If none of the five positions exist, all are set to a default value (1< < (BitDepth-1)), if BitDepth is 8, the default value is 128; if the upper reference pixel does not exist, filling with the pixel at the top left, and if the left reference pixel does not exist, filling with the pixel at the top left; if the top right reference pixel does not exist, it is filled by the top rightmost pixel, and if the bottom left reference pixel does not exist, it is filled by the left bottommost pixel.
In this embodiment, the abscissa of the CU is the corresponding positions of the upper right reference pixel and the upper reference pixel of the CU in the horizontal register, and the read and write address calculation formula is as follows:
wherein x is the abscissa of the current CU; CUSize is the current CU size, horiAddr is the horizontal register read and write address, and horiSize is the horizontal register read and write pixel number;
the lower three bits of the ordinate of the CU are the corresponding positions of the left reference pixel and the lower left reference pixel of the CU in the vertical register, and the read and write address calculation formula is as follows:
wherein y is the ordinate of the current CU; CUSize is the current CU size, VertADDr is the vertical register read and write address, and VertSize is the vertical register read and write pixel number;
the lower three bits of the ordinate of the CU are the corresponding positions of the upper left reference pixel of the CU in the upper left register, only one pixel is read, and the read and write address calculation formula of the horizontal register is as follows:
wherein TplfAddr is the upper left register read and write address, TplfSize is the number of pixels read and write to the upper left register.
Since the maximum LCU of 64 × 64 in the hevc standard, 32 × 32 LCUs and 16 × 16 LCUs can be compatible with 64 × 64 LCUs.
In the present embodiment, the calculation of the prediction value of the current CU is based on reference pixels generated by a CU whose reconstruction was completed before. However, since the reference pixels only adopt one row and one column of pixels around the current block, and the pixels at other positions are not referred to, a large number of reference pixels can be used only once and can not be used any more later, so that the reference pixels which are read once are covered by new reference pixels, the original storage space is occupied, and the storage space is not required to be newly opened up to store the new reference pixels, so as to achieve the purpose of reducing the on-chip storage space.
In this embodiment, only a space of 32 pixels in a column is needed for the storage of the reference pixels at the left and lower left (vertical register), and a space of 64 pixels in a row is needed for the storage of the reference pixels at the upper and upper right (horizontal register), plus the storage space of 8 reference pixels at the upper left (upper left register), to achieve the reference pixel management of the entire 64 × 64 LCU. A total of only 32 + 64 + 8 = 104 pixels of space is required for reference pixel storage, and 1792 are not required, greatly reducing on-chip storage space requirements and thus reducing chip area.
Meanwhile, only the storage space of 104 pixels is needed, the storage of the reference pixels is realized in a register file mode finally, and an SRAM (static random access memory) is not needed, so that the read-write complexity of the reference pixels is further reduced, and the processing speed is increased. In the implementation of the SRAM, only N pixels in one memory block can be read in one clock cycle, generally N =4, so that the clock cycles required for reading and writing the reference pixels of different CUs are different, that is, in the implementation of the SRAM, at least 4 clock cycles are required to complete the reading or writing. The management of horizontal, vertical and upper left reference pixels is realized by adopting a register pair mode, the reference pixels at corresponding positions can be directly written into corresponding registers for CUs of various sizes, and all the required reference pixels can be completely read or written in one period, so that the reading and writing time of the reference pixels is remarkably reduced, the intra-frame prediction is accelerated, and the requirements of high-definition and high-speed video coding and decoding are favorably met.
Example two
A difference between this embodiment and this embodiment is that, in this embodiment, the LCU is 32 × 32, and the step of writing the initial pixel is: storing 16 pixels to the left of the 32 x 32 LCU in a horizontal register, 16 pixels counted from the top of the LCU; storing 32 pixels on the upper side of the 32 x 32 LCU in a vertical register; storing the pixel positioned at the upper left corner in an upper left register; the method comprises the following steps: divide 32 x 32 LCUs into CUs.
EXAMPLE III
A difference between the present embodiment and the first embodiment is that, in the present embodiment, the LCU is 16 × 16, and the step of writing the initial pixel includes: storing 8 pixels to the left of the 16 x 16 LCU in a horizontal register, 8 pixels counted from the top of the LCU; storing 16 pixels on the upper side of the 16 x 16 LCU in a vertical register; storing the pixel positioned at the upper left corner in an upper left register; the method comprises the following steps: the 16 x 16 LCU is divided into CUs.
Example four
The present embodiment provides an intra prediction system, which is applied to the intra prediction methods according to the first embodiment, the second embodiment and the third embodiment, and includes:
and the register comprises a horizontal register, a vertical register and an upper left register, wherein the horizontal register is used for storing pixels at positions corresponding to the upper reference pixel and the upper right reference pixel of the CU as the upper reference pixel and the upper right reference pixel of the CU, the vertical register is used for storing pixels at positions corresponding to the left reference pixel and the lower left reference pixel of the CU as the left reference pixel and the lower left reference pixel of the CU, and the upper left register is used for storing pixels at positions corresponding to the upper left reference pixel of the CU as the upper left reference pixel of the CU.
The partitioning module is used for partitioning the LCU into a plurality of CUs for prediction and reconstruction;
the reading and writing module is used for reading pixels of the reference pixels of the current CU at corresponding positions in the horizontal register, the vertical register and the upper left register as the reference pixels of the current CU, updating the pixels of the lowest row of the reconstructed CU to the horizontal register, updating the pixels of the rightmost column of the reconstructed CU to the vertical register, covering the stored pixels at the corresponding positions of the horizontal register or the vertical register during updating, and updating the pixels of the divided upper left reference pixels of the CU at the corresponding positions in the vertical register to the upper left register according to the division of the LCU;
and the prediction and reconstruction module is used for predicting and reconstructing the current CU based on the read pixels.
EXAMPLE five
The present embodiment provides a computer device comprising a memory and a processor, the memory having a computer program stored therein, the processor implementing the method of any of the embodiments as described above when executing the computer program. It will be understood by those skilled in the art that all or part of the flow of the method implementing the above embodiments may be implemented by a computer program instructing associated hardware. Accordingly, the computer program can be stored in a non-volatile computer readable storage medium, and when executed, can implement the method according to any one of the above embodiments. Any reference to memory, storage, database, or other medium used in the embodiments provided herein may include non-volatile and/or volatile memory, among others. Non-volatile memory can include read-only memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), Rambus Direct RAM (RDRAM), direct bus dynamic RAM (DRDRAM), and bus dynamic RAM (RDRAM).
While the present invention has been described with reference to the preferred embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. Any modification which does not depart from the functional and structural principles of the present invention is intended to be included within the scope of the claims.
Claims (10)
1. An intra prediction method, comprising:
writing an initial pixel: storing N/2 pixels on the left side of the LCU at N x N in a horizontal register, wherein the N/2 pixels are counted from the topmost end of the LCU; storing N pixels on the upper side of the LCU at N x N in a vertical register; storing pixels located at the upper left corner of the LCU at N x N in an upper left register;
dividing: dividing the LCU of N by N into a plurality of CUs;
first CU prediction and reconstruction: reading pixels of the reference pixels of the CU at the upper left corner in the corresponding positions of the horizontal register, the vertical register and the upper left register, and predicting and reconstructing the CU at the upper left corner based on the read pixels;
updating a register: updating the pixels in the lowest row of the reconstructed CU to a horizontal register, updating the pixels in the rightmost column of the reconstructed CU to a vertical register, covering the pixels stored in the corresponding position of the horizontal register or the vertical register during updating, and updating the pixels of the corresponding position of the upper left reference pixel of the divided CU in the rightmost column of the reconstructed CU to an upper left register according to the division of the LCU;
other CU prediction and reconstruction: predicting the next CU, reading pixels of the reference pixel of the current CU at corresponding positions in the updated horizontal register, the updated vertical register and the updated upper left register, and predicting and reconstructing the current CU based on the read pixels;
and traversing all CUs, and repeating the step of updating the register and the step of predicting and reconstructing other CUs until all CUs finish predicting and reconstructing.
2. The method of claim 1, wherein the prediction and reconstruction are performed sequentially in a zig-zag order in the step of traversing all CUs.
3. The method of claim 1, wherein the abscissa of the CU is the corresponding positions of the upper-right reference pixel and the upper reference pixel of the CU in the horizontal register; the lower three bits of the ordinate of the CU are corresponding positions of a left reference pixel and a lower left reference pixel of the CU in the vertical register; the lower three bits of the ordinate of the CU are the corresponding positions of the upper left reference pixel of the CU in the upper left register, and only one pixel is read.
4. The method of claim 3, wherein the read and write addresses of the horizontal register are calculated by:
wherein x is the abscissa of the current CU; CUSize is the current CU size, horiAddr is the horizontal register read and write address, and horiSize is the horizontal register read and write pixel number;
the read and write address calculation formula for the vertical register is:
wherein y is the ordinate of the current CU; CUSize is the current CU size, VertADDr is the vertical register read and write address, and VertSize is the vertical register read and write pixel number;
the read and write address calculation formula for the top left register is:
wherein TplfAddr is the upper left register read and write address, TplfSize is the number of pixels read and write to the upper left register.
5. The method of claim 1, wherein when the upper-left CU is (N/2) × (N/2), the lower-left reference pixel of the upper-left CU is N/2 pixels located at the left side of the LCU of N × N, and N/2 pixels are counted from the topmost end of the LCU.
6. The method of any of claims 1 to 5, wherein the LCU of N x N is one of a LCU of 64 x 64, a LCU of 32 x 32, and a LCU of 16 x 16.
7. The method according to one of claims 1 to 5, wherein in the other CU prediction and reconstruction step, if the read pixel is invalid for the current CU, the other read pixel of the current CU is filled in.
8. An intra prediction system, comprising:
the register comprises a horizontal register, a vertical register and an upper left register, wherein the horizontal register is used for storing pixels at positions corresponding to an upper reference pixel and an upper right reference pixel of the CU as the upper reference pixel and the upper right reference pixel of the CU, the vertical register is used for storing pixels at positions corresponding to a left reference pixel and a lower left reference pixel of the CU as the left reference pixel and the lower left reference pixel of the CU, and the upper left register is used for storing pixels at positions corresponding to the upper left reference pixel of the CU as the upper left reference pixel of the CU;
the partitioning module is used for partitioning the LCU into a plurality of CUs for prediction and reconstruction;
the reading and writing module is used for reading pixels of the reference pixels of the current CU at corresponding positions in the horizontal register, the vertical register and the upper left register as the reference pixels of the current CU, updating the pixels of the lowest row of the reconstructed CU to the horizontal register, updating the pixels of the rightmost column of the reconstructed CU to the vertical register, covering the stored pixels at the corresponding positions of the horizontal register or the vertical register during updating, and updating the pixels of the divided upper left reference pixels of the CU at the corresponding positions in the vertical register to the upper left register according to the division of the LCU;
and the prediction and reconstruction module is used for predicting and reconstructing the current CU based on the read pixels.
9. A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor implements the method of any one of claims 1 to 6 when executing the computer program.
10. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the method of any one of claims 1 to 6.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104363455A (en) * | 2014-10-29 | 2015-02-18 | 复旦大学 | Hardware on-chip storage method applicable to infra-frame prediction reference pixels in HEVC (high efficiency video coding) standard |
| CN105791829A (en) * | 2016-03-30 | 2016-07-20 | 南京邮电大学 | HEVC parallel intra-frame prediction method based on multi-core platform |
| CN107105234A (en) * | 2010-08-17 | 2017-08-29 | M&K控股株式会社 | device for decoding image |
| US20190373267A1 (en) * | 2015-09-29 | 2019-12-05 | Qualcomm Incorporated | Video intra-prediction using position-dependent prediction combination for video coding |
| CN110662079A (en) * | 2019-10-23 | 2020-01-07 | 中国人民解放军国防科技大学 | Reference pixel on-chip storage method based on H.265HEVC intra-frame prediction |
-
2020
- 2020-04-10 CN CN202010277506.2A patent/CN111193934A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107105234A (en) * | 2010-08-17 | 2017-08-29 | M&K控股株式会社 | device for decoding image |
| CN104363455A (en) * | 2014-10-29 | 2015-02-18 | 复旦大学 | Hardware on-chip storage method applicable to infra-frame prediction reference pixels in HEVC (high efficiency video coding) standard |
| US20190373267A1 (en) * | 2015-09-29 | 2019-12-05 | Qualcomm Incorporated | Video intra-prediction using position-dependent prediction combination for video coding |
| CN105791829A (en) * | 2016-03-30 | 2016-07-20 | 南京邮电大学 | HEVC parallel intra-frame prediction method based on multi-core platform |
| CN110662079A (en) * | 2019-10-23 | 2020-01-07 | 中国人民解放军国防科技大学 | Reference pixel on-chip storage method based on H.265HEVC intra-frame prediction |
Non-Patent Citations (1)
| Title |
|---|
| 张亚运: "基于FPGA的视频编解码关键算法研究与设计", 《中国优秀硕士学位论文全文数据库》 * |
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