CN111190774A

CN111190774A - Configurable dual-mode redundancy structure of multi-core processor

Info

Publication number: CN111190774A
Application number: CN201911371031.7A
Authority: CN
Inventors: 宋立国; 于立新; 彭和平; 庄伟�; 覃辉; 亓洪亮; 王兴友; 苏天红; 飞海东; 张世远; 秦智勇; 杨雪; 任艳慧; 刘亚丽
Original assignee: Beijing Microelectronic Technology Institute; Mxtronics Corp
Current assignee: Beijing Microelectronic Technology Institute; Mxtronics Corp
Priority date: 2019-12-26
Filing date: 2019-12-26
Publication date: 2020-05-22
Anticipated expiration: 2039-12-26
Also published as: CN111190774B

Abstract

A multi-core processor configurable dual modular redundancy architecture, comprising: the system comprises a microprocessor, a first interface unit, a first routing unit, a second interface unit, a second routing unit and an on-chip shared storage unit. The two processors in the dual-mode redundancy mode automatically copy input data and automatically compare output data to find errors, and the errors are eliminated through automatic comparison of data in the register file and an automatic data recovery structure in the register file. The invention realizes that any two processors in the multi-core processor can be configured into a dual-mode redundancy mode.

Description

Configurable dual-mode redundancy structure of multi-core processor

Technical Field

The invention relates to a configurable dual-mode redundancy structure of a multi-core processor, and belongs to the technical field of multi-core processors.

Background

The method for improving soft error capability of a multi-core processor in the architecture mainly comprises the following steps: calculating the shifted operands through a redundant pipeline, and detecting transient and permanent errors in the ALU; detecting an error in the ALU using a function mapping relationship existing between an input operand and an output result of the arithmetic logic operation by the Berger code; watchdog (Watchdog) technology is used to monitor the address and data buses; performing soft error detection and correction on units such as an on-chip memory, a Cache, a register file and the like by using an ECC (error correction code) check code technology; the soft error detection execution model CRT detects soft errors by comparing the outputs of redundant threads.

The existing method needs to increase special hardware resources, and has limited error observation capability, such as: redundant pipelines and Berger code can only detect errors in ALU; the watchdog judges whether the program runs away or not through the query of fixed time, and the error cannot be found in time; the error correction and detection capability of the ECC check code is limited, and the encoding and decoding circuit has a large influence on the read-write performance of the memory. In the soft error tolerant execution model CRT of the multi-core microprocessor, the defects exist in the aspects of flexibility, performance and recoverability:

firstly, in the aspect of flexibility, the current multi-core processor fault-tolerant structure can only realize unidirectional data transmission and comparison between adjacent microprocessors, after one microprocessor core is designated as a main microprocessor, a slave microprocessor with a corresponding dual-mode redundancy function is uniquely determined, and vice versa, the dual-mode redundancy of any two microprocessor cores cannot be realized, the flexibility is lacked, and the expandability of the model is severely limited;

in the aspect of performance, in the current structure, data in a register in each processor needs to be directly compared after each instruction is executed, the data size is large, so that the pipeline blockage caused by the fact that the operation result cannot be timely compared is caused, the performance of an execution model is reduced, and the method is particularly not suitable for a multi-core processor with multiple emission processor cores; and the large amount of data transfer and comparison also increases the dynamic power consumption of the chip.

In the aspect of recoverability, a hardware-implemented field saving and recovering function is lacked, and software is needed to assist in completing two functions: 1) backing up the operating environment; 2) after detecting the soft error, the operation environment is restored to the correct operation environment. The soft error tolerance and overall performance of the multi-core processor are reduced due to the need for excessive participation in the software.

Disclosure of Invention

The technical problem to be solved by the invention is as follows: the defects of the prior art are overcome, a configurable dual-mode redundancy structure of the multi-core processor is provided, and the problem that any two processors in the multi-core processor can be configured into a dual-mode redundancy mode at any time according to needs, and the two processors which are not fixed are in the dual-mode redundancy mode is solved; the data quantity which needs to be compared when the dual-mode redundancy mode detection error occurs is reduced, only the output data of the microprocessor is compared, and the comparison is not carried out on each instruction, so that the requirements on the bandwidth and the time sequence of the read-write data of the main microprocessor and the slave microprocessor are reduced; the method solves the error recovery function of the dual-mode redundancy mode, integrally backs up and recovers the register file in the microprocessor core from hardware, and realizes the hardware field storage and recovery functions.

The technical scheme of the invention is as follows:

a multi-core processor configurable dual modular redundancy architecture, comprising: the system comprises a microprocessor, a first interface unit, a first routing unit, a second interface unit, a second routing unit and an on-chip shared storage unit;

the on-chip shared storage unit is respectively connected with a plurality of first interface units, and each first interface unit is respectively connected with a corresponding first routing unit and a microprocessor; each microprocessor is connected with a second interface unit and a second routing unit in sequence;

the microprocessor is used for executing instructions and processing data, and comprises: the device comprises a controller, an Arithmetic Logic Unit (ALU), a register file, a redundancy control register and a register file redundancy control unit; the controller is used for sending control information; the arithmetic logic unit ALU is used for operating data; the register file is used for storing an intermediate processing result; the redundancy control register is used for setting the microprocessor to be used as a master microprocessor or a slave microprocessor under a dual-mode redundancy mode; the register file redundancy control unit is used for completing backup and recovery of register files in the microprocessor;

when the microprocessor executes the load instruction load, the microprocessor receives data input by the first interface unit; when executing the storage instruction store, the microprocessor outputs data to the first interface unit; after the microprocessor executes a thread, register file information is sent to the second interface unit through the register file redundancy control unit; when the two processors in the dual-mode redundancy mode respectively send register file information to the second interface unit to be the same, the register file redundancy control unit copies the data in the register file to the backup register file; when the two processors in the dual-mode redundancy mode respectively send register file information to the second interface unit, the register file redundancy control unit copies data in the internally backed-up register file into the register file;

the first interface unit is used for comparing the output data of the execution Store instruction of the main microprocessor and the slave microprocessor under the dual-mode redundancy mode and judging whether an error is detected;

the first interface unit reads data from the on-chip shared memory unit and transmits the data to the microprocessor according to an address and a read signal input by the microprocessor executing the load instruction load; the first interface unit receives data corresponding to the execution of the storage instruction store by the microprocessor, and stores the data corresponding to the storage instruction store; judging whether the data corresponding to the storage instruction store executed by the master microprocessor and the slave microprocessor under the dual-mode redundancy mode are the same, if so, transmitting the data to the on-chip shared storage unit, and if not, indicating that an error is detected; when the microprocessor connected with the first interface unit is used as a main microprocessor in a dual-mode redundancy mode, receiving data fed back by the first routing unit for comparison, wherein the data source is data corresponding to a storage instruction store executed by a slave microprocessor in the dual-mode redundancy mode; when the microprocessor connected with the first interface unit is used as a slave microprocessor in a dual-mode redundancy mode, transmitting data corresponding to the execution and storage instruction store of the microprocessor to the first routing unit;

the first routing units are connected pairwise;

corresponding to any one first routing unit, receiving data input by the first interface unit and transmitting the data to the adjacent first routing unit; meanwhile, receiving data input by an adjacent first routing unit, transmitting the received data to a first interface unit when judging that an address signal in the received data is matched with the address information of the first routing unit, and continuously transmitting the received data to the adjacent first routing unit when judging that the address signal of the received data is not matched with the address information of the first routing unit;

the second interface unit is used for comparing data in the register file after the main microprocessor and the slave microprocessor execute each section of thread in the dual-mode redundancy mode, notifying the register file redundancy control unit when the data are different, restoring the register file to the state after the last section of thread is executed, and re-executing the thread with errors; after the microprocessor executes a thread, the second interface unit sequentially receives data in the register file sent by the register file redundancy control unit in the microprocessor; when the microprocessor connected with the second interface unit is used as a main microprocessor in a dual-mode redundancy mode, receiving data fed back by the second routing unit and comparing the data with the received data in the register file sent by the register file redundancy control unit; when the microprocessor connected with the second interface unit is used as a slave microprocessor in a dual-mode redundancy mode, transmitting data in the register file sent by the register file redundancy control unit to the second routing unit; judging whether register file data received by a second interface unit connected with the master-slave microprocessor under the dual-mode redundancy mode are the same or not, and feeding back a judgment result to respective register file redundancy control units;

the second routing unit receives the data input by the second interface unit and transmits the data to the corresponding second routing unit in the dual-mode redundancy mode; and receiving data input by the adjacent second routing unit, transmitting the received data to the second interface unit when judging that the address signal in the received data is matched with the address information of the second routing unit, and continuously transmitting the received data to the adjacent second routing unit when judging that the address signal in the received data is not matched with the address information of the second routing unit.

Compared with the prior art, the invention has the beneficial effects that:

1) the invention is not limited to the realization of dual-mode redundancy between adjacent processor cores, but can realize flexible configuration of dual-mode redundancy of any two microprocessor cores in the multi-core processor, including adjacent core dual-mode redundancy setting, non-adjacent core dual-mode redundancy setting and master-slave microprocessor setting, rather than fixed dual-mode redundancy configuration of adjacent cores.

2) The invention reduces the data quantity of dual-mode redundancy comparison of the microprocessor core, only compares the output data of the microprocessor, but not compares the output data of each instruction, each program jump and each register rewriting, and reduces the requirements on the bandwidth and the time sequence of the read-write data of the master microprocessor and the slave microprocessor.

3) The data read by the main microprocessor loading load instruction is stored in the cache, and the slave microprocessor directly reads from the main microprocessor cache instead of reading the data from the storage system again when executing the load instruction, so that the requirement on the access of an external memory is reduced, and the consistency of the data input by the main microprocessor and the slave microprocessor can be ensured.

4) The invention designs the register backup file, realizes the functions of hardware field saving and restoring, and integrally saves and restores the register file in the microprocessor core.

5) The inter-core queue realizes data transmission by using a ring network-on-chip structure, simplifies the design and verification of the multi-core processor and realizes the expandability of the structure.

Drawings

FIG. 1 is a diagram of the dual modular redundancy architecture of the present invention;

FIG. 2 is a diagram illustrating the definition of redundancy control registers according to the present invention;

FIG. 3 is a diagram of a register file redundancy control unit architecture according to the present invention;

FIG. 4 is a diagram of a first interface unit according to the present invention;

FIG. 5(a) is a diagram of a first routing unit architecture according to the present invention;

FIG. 5(b) is a diagram of a first routing unit architecture according to the present invention;

FIG. 6 is a diagram of a second interface unit according to the present invention;

FIG. 7(a) is a diagram of a second routing unit architecture according to the present invention;

fig. 7(b) is a diagram showing a second routing unit structure according to the present invention.

Detailed Description

The invention discloses a configurable dual-modular redundancy structure of a multi-core processor, which is shown in figure 1 and comprises the following components: the microprocessor 101, the first interface unit 141, the first routing unit 151, the second interface unit 161, the second routing unit 171, and the on-chip shared memory unit 181;

the on-chip shared memory unit 181 is respectively connected with a plurality of first interface units 141, and each first interface unit 141 is respectively connected with a corresponding first routing unit 151 and the microprocessor 101; each microprocessor 101 is connected with a second interface unit 161 and a second routing unit 171 in sequence;

microprocessor 101 is used to execute instructions and process data, including: a controller, an arithmetic logic unit ALU, a register file, a redundancy control register 121, a register file redundancy control unit 131; the controller is used for sending control information to other components; the arithmetic logic unit ALU is used for carrying out various operations on the data; the register file is used for storing an intermediate processing result; the redundancy control register 121 is used to set the microprocessor 101 as a master microprocessor or as a slave microprocessor in the dual redundancy mode; the register file redundancy control unit 131 is used to complete the backup and restore of the register file in the microprocessor 101. The traditional microprocessor internally comprises a controller which sends control information to other components; an arithmetic logic unit ALU, which is responsible for various operations on data; and the register file is used for storing the intermediate processing result. On the basis, the invention adds a redundancy control register 121, and sets whether the processor is used as a master microprocessor or a slave microprocessor under a dual-mode redundancy mode through the redundancy control register 121; the register file redundancy control unit 131 is added to complete the backup and recovery of the register file in the microprocessor.

When the microprocessor 101 executes the load instruction load, it receives the data input by the first interface unit 141; when executing the store instruction store, the microprocessor 101 outputs data to the first interface unit 141; after the microprocessor 101 executes a thread, the register file redundancy control unit 131 sends out register file information to the second interface unit 161; when the two processors in the dual-mode redundancy mode respectively send register file information to the second interface unit 161 to be the same, the register file redundancy control unit 131 copies the data in the register file to the backup register file; when the two processors in the dual-mode redundancy mode send register file information to the second interface unit 161 differently, the register file redundancy control unit 131 copies data in the internally backed-up register file to the register file, and through this hardware register file detection and recovery manner, after detecting a register file error, the program will trace back to the previous correct starting point and resume executing the program.

The first interface unit 141 is used for comparing the output data of the Store instruction executed by the main microprocessor and the slave microprocessor in the dual-mode redundancy mode, and judging whether an error is detected;

the first interface unit 141 reads data from the on-chip shared memory unit 181 and transfers the data to the microprocessor 101 according to an address and a read signal input by the microprocessor 101 executing the load instruction load; the first interface unit 141 receives data corresponding to the execution of the store instruction store by the microprocessor 101, and stores the data corresponding to the store instruction store; judging whether the data corresponding to the storage instruction store executed by the master microprocessor and the slave microprocessor under the dual-mode redundancy mode are the same, if so, transmitting the data to the on-chip shared storage unit 181, and if not, indicating that an error is detected; when the microprocessor 101 connected to the first interface unit 141 is used as a master microprocessor in the dual-mode redundancy mode, the data fed back by the first routing unit 151 is received and compared, and the data source is data corresponding to the storage instruction store executed by the slave microprocessor in the dual-mode redundancy mode; when the microprocessor 101 connected to the first interface unit 141 is a slave microprocessor in the dual redundancy mode, the transfer microprocessor 101 executes the store instruction store corresponding data to the first routing unit 151;

the plurality of first routing units 151 are connected two by two;

corresponding to any one of the first routing units 151, receiving the data input by the first interface unit 141, and transmitting the data to the adjacent first routing unit 151; meanwhile, receiving data input by the adjacent first routing unit 151, when judging that an address signal in the received data matches the address information of the first routing unit 151, transferring the received data to the first interface unit 141, and when judging that the address signal in the received data does not match the address information of the first routing unit 151, continuing to transfer the received data to the adjacent first routing unit 151;

the second interface unit 161 is configured to compare data in the register file after the master microprocessor and the slave microprocessor execute each section of thread in the dual-modular redundancy mode, notify the register file redundancy control unit 131 when the data are different, restore the register file to a state after the previous section of thread is executed, and re-execute the thread with an error. After the microprocessor 101 executes a thread, the second interface unit 161 sequentially receives data in the register file sent by the register file redundancy control unit 131 in the microprocessor 101; when the microprocessor 101 connected to the second interface unit 161 is a master microprocessor in the dual-mode redundancy mode, receiving the data fed back by the second routing unit 171 and comparing the data with the received data in the register file sent by the register file redundancy control unit 131; when the microprocessor 101 connected to the second interface unit 161 functions as a slave microprocessor in the dual redundancy mode, data in the register file transmitted by the register file redundancy control unit 131 is transferred to the second routing unit 171; judging whether the register file data received by the second interface unit 161 connected with the master-slave microprocessor 101 in the dual-mode redundancy mode are the same or not, and feeding back the judgment result to the respective register file redundancy control unit 131;

the second routing unit 171 receives the data input by the second interface unit 161, and transmits the data to the corresponding second routing unit 171 in the dual-mode redundancy mode; and receiving data input by the adjacent second routing unit 171, transmitting the received data to the second interface unit 161 when judging that the address signal in the received data matches the address information of the own second routing unit 171, and continuously transmitting the received data to the adjacent second routing unit 171 when judging that the address signal in the received data does not match the address information of the own second routing unit 171.

In particular, the method comprises the following steps of,

in fig. 1, the microprocessor 101 is a 32-bit microprocessor capable of performing arithmetic and logic operations, and integrating the redundancy control register 121 and the register file redundancy control unit 131 to implement configurable dual-modular redundancy functions; the integrated redundant control register 121 is a redundant control register, which is an internal unit of the microprocessor 101 and has the function of setting a main microprocessor/redundant core function and position information; the register file redundancy control unit 131 is a register file redundancy control unit and is an internal unit of the microprocessor 101, and has the function of completing the backup and recovery functions of the register file of the microprocessor core; the first interface unit 141 is responsible for copying input data when the load instruction load is executed by the microprocessor 101, comparing output data when the store instruction store is executed, and performing external store access when the store instruction store is normal (no redundancy function is set). There are three data input/output connections, respectively, a microprocessor 101 data access connection (consisting of a read operation request signal 418, a read operation reply signal 424, and a write operation signal 434), a first route consisting of a unit 151 data access connection (consisting of an additional redundant core Store request input 428, an own redundant core Store request output 432, an additional redundant core Load request input 426, an additional redundant core Load reply output 427, an own redundant core Load reply input 423, an own redundant core Load request output 422), and an on-chip shared memory unit 181 data access connection (consisting of a shared memory read access request signal 419, a shared memory read access reply signal 425, and a shared memory write access signal 429).

As shown in fig. 1, the plurality of first routing units 151 are connected to each other to form a ring network structure, and there are three data input/output connections, that is, input/output connections of left adjacent first routing units 151, input/output connections of right adjacent first routing units 151, and input/output connections of the first interface unit 141 (composed of other redundant core Store request input 428, self redundant core Store request output 432, other redundant core Load request input 426, other redundant core Load response output 427, self redundant core Load response input 423, and self redundant core Load request output 422).

The second interface unit 161 is responsible for comparing the register file by the microprocessor 101 in the dual-modular redundancy configuration. There are two data connections, respectively, a microprocessor 101 data output connection (register file compare signal 310) and a second routing unit 171 data input/output connection (consisting of its own redundant core register compare output 609 and other redundant core register compare inputs 610).

The second routing unit 171 and the plurality of second routing units 171 are connected to each other to form a ring network structure, and there are three data input/output connections, namely, input/output connection of the second routing unit 171 adjacent to the left, input/output connection of the second routing unit 171 adjacent to the right, and input/output connection of the second interface unit 161 (composed of a comparison output 609 of the self redundant core register and a comparison input 610 of other redundant core registers).

The on-chip shared memory unit 181 may be a shared secondary Cache or a shared RAM. There are input/output connections to each microprocessor core (consisting of shared memory read access request signal 419, shared memory read access acknowledge signal 425, and shared memory write access signal 429).

FIG. 2 shows redundancy

control register structures

121, 201 with a dual-mode redundancy enable bit of '1' active, and the remaining bits in the register are only active if this bit is set to '1'. 202 sets bits for redundant core locations, occupying four bits, from '0000' to '1111', which can designate a 16-location processor core as a redundant core (slave microprocessor) in dual mode redundancy mode. 203 is a redundant core local enable bit of '1' active, which is set to '1' after which the core is a redundant core (slave microprocessor) in dual mode redundancy mode. 204 sets bits for the master microprocessor position, occupying four bits, from '0000' to '1111', which can designate the 16-position processor core as the master microprocessor in dual mode redundancy mode. 205 is a master microprocessor local enable bit of '1' active, and after this bit is set to '1', this core is the master microprocessor in dual mode redundancy mode.

Fig. 3 shows a 131 register file redundancy control unit structure, in which 301 is a register file, which includes an IU (integer unit) register file inside the microprocessor core and an IU-related internal register, and the register file has a bit width of 32 bits and is read and written according to an address. 302 is a register backup file, which comprises an IU (integer unit) register file inside the microprocessor core and IU related internal registers, the bit width of the register backup file is 33 bits, wherein the lower 32 bits are data bits, the highest bit is a flag bit, and the file is read and written according to the address. When a write operation is performed to register file 301, the most significant bit of the corresponding address of register file 302 is set to '1', indicating that the data at this address in the register file has been altered. 303 is a first sequential logic function unit, which has the following functions:

1) when a thread executes, it reads normally, issuing a read signal 304 to read data from the register file 301.

2) When the thread executes, normal write operation is carried out, and a write signal 306 and data write register file aiming at the register file 301 are sent; meanwhile, with respect to the write signal 306 of the register backup file 302, the flag of the corresponding address is set in the register backup file 302, but the lower 32-bit data is not changed.

3) After the thread is executed, firstly, reading operation is executed aiming at the register backup file 302 to obtain address information corresponding to the flag setting as '1'; depending on the obtained address information, the data is read back from the register file 301 and output as register file compare signal 310.

4) When the register file is correct, the data in the register file 301 is copied to the register backup file 302 one by one according to the address, and the Flag is cleared.

5) When the register file is incorrect, the data in the register backup file 302 is copied to the register file 301 one by one according to the address, and the Flag is cleared.

304 issues a read signal 303 to register file 301.

305 issues a read signal to register file 302 for 303.

306 issues a 303 write signal to register file 301.

307 issues a write signal to register backup file 302 at 303.

308 are data output signals of the register file 301, which are directly input to the first sequential logic function unit 303.

Reference numeral 309 denotes the data output signal of the register file 302, which is directly inputted into the first sequential logic unit 303.

310 is the register file compare signal, 33 bits wide, 303 bits wide, with the output connected to 161.

Fig. 4 is a structure diagram of the first interface unit 141, where 401 is an input data buffer FIFO, data bit wide 33 bits, buffer depth 128 words, and the input data is an output signal 423 (self redundant core Load acknowledge input) of the first routing unit 151, and the output is connected to the multiplexer 406. 402 is the input data buffer FIFO, data bit wide 33 bits, buffer depth 128 words, input data is the output of the tri-state gate 415, the output is connected to the first combinational logic circuit 407. 403 is the input data buffer FIFO with 33 bits of data width and 128 words of buffer depth, the input data is the output signal 426 (other redundant core Load request input) of the first routing unit 151, and the output is connected to the first combinational logic circuit 407. 404 is an input data buffer FIFO with a data bit width of 65 bits and a buffer depth of 128 words, the input data is the output of the tri-state gate 413, and the output is connected to the second combinational logic circuit 408. 405 is an input data buffer FIFO with a data bit width of 33 bits and a buffer depth of 128 words, the input data is an output signal 428 (other redundant core Store request input) of the first routing unit 151, and the output is connected to the second combinatorial logic circuit 408. 406 is an alternative multiplexer having inputs for the output of the FIFO 401 and the memory access acknowledge signal 425, respectively, and a control signal 421. Reference numeral 407 denotes a first combinational logic circuit, which receives the output data of the

FIFOs

402 and 403 and the output of the and gate 416, respectively, and outputs a signal 427 (other redundant core Load response output) to the first routing unit 151. The function is to read 402 the data output in the FIFO when the output of AND gate 416 is '1'. 408 is a second combinational logic circuit having inputs for the output data of the

FIFOs

404 and 405 and the output of the and gate 417, respectively, and outputs having two 429 and 430. The function is to compare the output data of 404 and 405 to be equal when the output of AND gate 417 is '1' and if equal, output the data to shared memory system 118 via 429; if not, a thread execution error signal 430 is generated, 429 output is set to a high impedance state. 409 is a tristate gate, the input is a read operation request signal 418 output by the microprocessor core, the control signals are signals obtained by logical and operation of 201 and 205, and the output is a read operation request signal 419 of the shared memory system 118. The input of the gate 410 is a read operation request signal 418 output by the microprocessor core, the control signals are signals obtained by logical and operations of 201 and 203, and the output is an input signal 422 (self redundant core Load request output) of the first routing unit 151. Reference numeral 411 is a tri-state gate having an input of a write request signal 435 output by the microprocessor core, a control signal 433 and '0' active, and an output of a write signal 429 output to the shared memory system 418. And 412 is a tri-state gate having an input for a write operation request signal from the microprocessor core, a control signal 433 and '1' active, and outputs coupled to the inputs of

tri-state gates

413 and 414, respectively. 413 is a tri-state gate having an input at the output of tri-state gate 412 and a control signal 431, 0' active, and an output coupled to FIFO 404. The input of 414 is a tri-state gate, the output of which is the tri-state gate 412, the control signal is 431 and '1' is valid, and the output is connected with the input signal 432 (self redundant core Store request output) of the first routing unit 151. 415 is a tri-state gate having an input of a memory access acknowledge signal 425, and

control signals

201 and 205 are logically anded signals, with the input connections of the output FIFO 402. 416 is an and gate having inputs for the non-empty signals of FIFO 402 and FIFO 403 respectively and an output coupled to the first combinatorial logic circuit 407. 417 is an and gate having inputs for non-empty signals of FIFO 404 and FIFO 405, respectively, and an output coupled to second combinatorial logic 408. 418 is a read request signal from the microprocessor core, which includes a read enable signal line, a 32-bit address line, directly connected to the inputs of the

tri-state gates

409, 410. 419 is a read operation request signal for the shared memory system 118, which includes a read enable signal line, a 32-bit address line, and is the output of the tri-state gate 409. The input control signal 420 of the tri-state gate 409 is a 201-bit and 205-bit logically anded signal. The input control signal 421 of the tri-state gate 410 is a 201-bit and 203-bit logically anded signal. The output 422 of tristate gate 410, which contains read enable, 32-bit address, and 204-bit information of the host microprocessor location, is used as the input signal 422 (self redundant core Load request output) of the first routing unit 151. 423 is the first routing unit 151 output signal (native redundant core Load acknowledge input) containing 32 bits of data and a data valid bit as inputs to the FIFO 401. 424 is the output of the one-out-of-two multiplexer 406 as a microprocessor core read operation acknowledge signal containing 32 bits of data and a data valid bit. 425 is a memory access acknowledge signal comprising 32 bits of data and a data valid bit, coupled to the 406 input and 415 input, respectively. 426 is a first routing unit 151 output signal (other redundant core Load request input) comprising 32 bits of data and a data valid bit, coupled to a FIFO 403 input. 427 is an output of the first combinational logic circuit 407, and includes 32-bit data and a data valid bit as an input signal (other redundant core Load response output) of the first routing unit 151. 428 outputs a signal (other redundant core Store request input) for the first routing unit 151 as an input to the FIFO 405, containing 32 bits of data and a data valid bit. 429 is a memory access write signal comprising a write enable signal line, a 32-bit address line, and a 32-bit data line, coupled to shared memory system 118. The error flag signal line 430 is a '1' indicating that the comparison data of the second combinational logic circuit 408 is not equal, and a thread execution error condition occurs. 431 are control signals for tri-state gate 413, respectively, with '0' active at this time; the control signal of tri-state gate 414, now '1', is active. Is a 203-bit signal line. 432 is the output of tristate gate 414 as the first routing unit 151 input signal (self redundant core Store request output) containing the data valid bit, 32 bit data bit and main microprocessor location 204 bit information. 433 are the control signals of the tri-state gate 411, respectively, where '0' is active; the control signal of tri-state gate 412, now '1', is active. Is a 201-bit signal line.

434 are write request signals output by the microprocessor core, including a write enable signal line, a 32-bit address line, and a 32-bit data line, directly connected to the inputs of the

tri-state gates

411, 412.

Fig. 5(a) (b) is a 151 first routing unit structure diagram, as in fig. 5 (a):

501 is an input data buffer FIFO, data bit wide 33 bits, buffer depth 128 words, and input is an output 513 of the left adjacent first routing unit 151; the output is 508 and is connected to a first arbitration logic unit 515 and a first crossbar unit 516, respectively.

502 is the input data buffer FIFO, data bit wide 33 bits, buffer depth 128 words, input is the output 514 of the right adjacent first routing unit 151; the output is 509, which is connected to a first arbitration logic unit 515 and a crossbar unit 516, respectively.

503 is input data buffer FIFO, data bit wide 33 bits, buffer depth 128 words, input 432; the output is 510, which is connected to a first arbitration logic unit 515 and a crossbar unit 516, respectively.

504 is input data buffer FIFO, data bit wide 33 bit, buffer depth 128 word, input 427; the output is 511, which is connected to a first arbitration logic unit 515 and a crossbar unit 516, respectively.

505 is input data buffer FIFO, data bit wide 33 bits, buffer depth 128 words, input 422; the output is 512, which is connected to the first arbitration logic unit 515 and the crossbar unit 566, respectively.

506 is the input to the FIFO 501, a 33-bit signal line, and is the output 513 of the left-adjacent first routing cell 151.

507 is the input to the FIFO 502, a 33-bit signal line, and is the output 514 of the right-adjacent first routing cell 151.

508 is the FIFO 501 output, 33-bit signal line, input to the first arbitration logic 515 and the first crossbar 516.

509 is the FIFO 502 output, 33-bit signal line, input to a first arbitration logic unit 515 and a first crossbar unit 516.

510 is the FIFO 503 output, 33-bit signal line, input to a first arbitration logic unit 515 and a first crossbar unit 516.

511 is the FIFO 504 output, 33-bit signal line, input to a first arbitration logic unit 515 and a first crossbar unit 516.

512 is the FIFO 505 output, 33 bit signal line, input first arbitration logic 515 and first crossbar 516.

513 is the output of the multiplexer 525, the 33-bit signal line, and also the output of the first cross switch unit 516 in the right direction.

514 is the output of the multiplexer 526, 33 bit signal line, which is also the output of the first cross switch unit 516 to the left.

515 is a first arbitration logic unit with

inputs

508, 509, 510, 511, 512 respectively and an output connected to a first crossbar unit 516. The function is to adopt a classic Round-Robin arbitration algorithm to realize the sorting of the output sequence of the five inputs from the perspective of fairness and priority.

516 is a first crossbar unit with

inputs

522, 523, 524, 525, 526 and

outputs

423, 426, 428, 510, 511, respectively. The function is to realize the transmission path selection by using a register and a multiplexer. The structure is shown in FIG. 5 (b).

517 is a 33-bit register, the input is 510, and the outputs are connected to multiplexers 525, 526, respectively.

518 is a 33-bit register with inputs 511 and outputs connected to multiplexers 525 and 526, respectively.

519 is a 33-bit register with 512 inputs and outputs connected to multiplexers 525 and 526, respectively.

520 is a 33-bit register with inputs 509 and outputs connected to multiplexers 522, 523, 524, 526, respectively.

521 is a 33-bit register with inputs 508 and outputs connected to multiplexers 522, 523, 524, 525 respectively.

522 is a multiplexer with inputs at the outputs of 520 and 521 and an output at 428.

523 is a multiplexer with inputs at the outputs of 520 and 521 and an output at 426.

524 is a multiplexer, the inputs are the outputs of 520 and 521, and the output is 423.

525 is a multiplexer with inputs at 517, 518, 519, and 521, and an output at 513.

526 is a multiplexer with inputs at 517, 518, 519, and 520 outputs at 514.

Fig. 6 is a diagram of a 161 second interface unit structure, in which: 601 is a tristate gate with 310 inputs, 611 control signals and 609 outputs. 602 is a tristate gate with an input of 310, a control signal of 612 and an output as an input to the FIFO 603. 603 is an input data buffer FIFO with 33 bits of data bit width and 256 words of buffer depth, buffer register file data output by the main microprocessor, an output data line is connected with a third combinational logic circuit 606, and a non-empty state signal is output and connected with 605. 604 is input data buffer FIFO, data bit width is 33 bits, buffer depth is 256 words, register file data output by other redundant cores are buffered, output data line is connected with third combinational logic circuit 606, and output non-empty state signal is connected with 605.

605 is an and gate, the inputs of which are the non-empty status signals of the FIFO 603 and the FIFO 604, respectively, and the output of which is connected to the third combinational logic circuit 606 as the trigger signal for triggering 606 operation.

606 is a third combinational logic circuit, which inputs the output data of the

FIFOs

603 and 604 and the output of the and gate 605, respectively, and has two

outputs

607 and 608. The function is to compare 603 and 604 output data to be equal when the output of the and gate 605 is '1', and if equal, the output signal 607 is set to '1', and the output signal 608 is set to '0'; if not, then output signal 607 is set to '0' and output signal 608 is set to '1'.

607 is the output signal line of the third combinational logic 606, and a '1' indicates that the register file is correct.

608 is the output signal line of third combinatorial logic 606, and a '1' indicates that the register file is incorrect.

609 is a tristate gate 601 output, 33-bit signal line, as a self redundant core register comparison output signal, to the second routing unit 171.

610 is the second routing unit 171 output signal (other redundant core register compare input) connected to the input of the FIFO 604.

611 is the input control signal of the tri-state gate 601, which is the signal after logical and operation of 201 bits and 203 bits.

611 is the input control signal of the tri-state gate 602, which is the 201 bit and 205 bit logically anded signal.

Fig. 7(a) (b) is a diagram of a second routing unit structure 171, and in fig. 7 (a):

an input data buffer FIFO with a data bit width of 33 bits, a buffer depth of 128 words, an input 704 and an output 706, are connected to the second arbitration logic unit 713 and the second crossbar unit 714, respectively.

702 is an input data buffer FIFO with a data bit width of 33 bits, a buffer depth of 128 words, an input of 705, and an output of 707, which are connected to a second arbitration logic unit 713 and a second crossbar unit 714, respectively.

703 is an input data buffer FIFO with a data bit width of 33 bits, a buffer depth of 128 words, an input of 711 and an output of 712, which are connected to the second arbitration logic unit 713 and the second crossbar unit 714, respectively.

704 is the input to the FIFO 701 and is 33 bits wide in data bits and is connected to the output 709 of the left adjacent second routing cell structure diagram.

705 is the input to the FIFO 702, 33 bits wide in data bits, connected to the output 708 of the next-to-the-right second routing cell structure diagram.

706 is the output of the FIFO 701, the data bit wide is 33 bits, and is connected to the second arbitration logic 713 and the second crossbar unit 714, respectively.

707 is the output of the FIFO 702, the data bit wide is 33 bits, which is connected to the second arbitration logic unit 713 and the second crossbar unit 714, respectively.

708 is the multiplexer 720 output, 33 bit signal line, also the first crossbar unit 714 output to the left.

709 is the output of the multiplexer 719, 33 bit signal line, also the output of the first cross bar switch unit 714 to the right.

710 is the multiplexer 718 output, 33-bit signal line, connected to 610 as the other redundant core register compare input signal output by the first crossbar unit 714.

711 is FIFO input signal, 33 bit signal line, directly connected to 609, as the output signal of the second interface unit output self redundant core register comparison.

712 is the output of the FIFO 703, which is 33 bits wide in data bit, and is connected to the second arbitration logic 713 and the second crossbar 714, respectively.

713 is a second arbitration logic unit with

inputs

706, 707, 712 respectively, and an output connected to a second crossbar unit 714. The function is to adopt a classic Round-Robin arbitration algorithm to realize the sorting of the output sequence of the five inputs from the perspective of fairness and priority.

714 is a second crossbar unit to which the output signals 706, 707, 712, and 713 are input and 708, 709, and 710 are output. The function is to realize the transmission path selection by using a register and a multiplexer. The structure is shown in FIG. 7 (b).

715 are 33-bit registers, the inputs are 712, and the outputs are connected to multiplexers 719, 720, respectively.

716 is a 33-bit register, the input is 705, and the output is connected to multiplexers 718, 720, respectively.

717 is a 33-bit register, with input 704 and output connected to multiplexers 718, 719 respectively.

718 is a multiplexer, the inputs are the outputs of

registers

716 and 717, and the output is 710.

719 is a multiplexer with inputs being the outputs of

registers

715 and 717 and an output 709.

720 is a multiplexer with inputs being the outputs of

registers

715 and 716 and an output of 708.

The structure of the invention is not only suitable for the multi-core processor based on the time-sharing bus, but also suitable for the multi-core processor based on the network on chip, and the number of cores integrated in the multi-core processor is not limited.

The structure of the invention can be applied to a 32-bit multi-core processor and can also be applied to a 64-bit multi-core processor, the data buffer FIFO in the structure is changed from 33 bits of data bit width to 65 bits, and only the 65 bits of data bit width of the FIFO 404 are changed to 97 bits.

Those skilled in the art will appreciate that the details of the invention not described in detail in the specification are within the skill of those skilled in the art.

Claims

1. A multi-core processor configurable dual modular redundancy architecture, comprising: the system comprises a microprocessor (101), a first interface unit (141), a first routing unit (151), a second interface unit (161), a second routing unit (171) and an on-chip shared storage unit (181);

the on-chip shared storage unit (181) is respectively connected with a plurality of first interface units (141), and each first interface unit (141) is respectively connected with a corresponding first routing unit (151) and a microprocessor (101); each microprocessor (101) is sequentially connected with a second interface unit (161) and a second routing unit (171);

a microprocessor (101) for executing instructions and processing data, comprising: a controller, an arithmetic logic unit ALU, a register file, a redundancy control register (121), a register file redundancy control unit (131); the controller is used for sending control information; the arithmetic logic unit ALU is used for operating data; the register file is used for storing an intermediate processing result; the redundancy control register (121) is used for setting the microprocessor (101) to be a master microprocessor or a slave microprocessor in a dual-mode redundancy mode; the register file redundancy control unit (131) is used for completing backup and recovery of register files in the microprocessor (101);

when the microprocessor (101) executes the load instruction load, the data input by the first interface unit (141) is received; when executing a store instruction store, the microprocessor (101) outputs data to the first interface unit (141); after the microprocessor (101) finishes executing a thread, the register file redundancy control unit (131) sends register file information to the second interface unit (161); when the two processors in the dual-mode redundancy mode respectively send out register file information to the second interface unit (161) to be the same, the register file redundancy control unit (131) copies the data in the register file to the backup register file; when the two processors in the dual-mode redundancy mode respectively send register file information to the second interface unit (161) to be different, the register file redundancy control unit (131) copies data in the register file which is internally backed up into the register file;

the first interface unit (141) is used for realizing the comparison of the output data of the execution Store instruction of the main microprocessor and the slave microprocessor under the dual-mode redundancy mode, and judging whether an error is detected;

the first interface unit (141) reads data from the on-chip shared memory unit (181) according to an address and a read signal input by the microprocessor (101) executing the load instruction load and transmits the data to the microprocessor (101);

the first interface unit (141) receives data corresponding to the storage instruction store executed by the microprocessor (101), and stores the data corresponding to the storage instruction store; judging whether the data corresponding to the storage instruction store executed by the master microprocessor and the slave microprocessor under the dual-mode redundancy mode are the same, if so, transmitting the data to an on-chip shared storage unit (181), and if not, indicating that an error is detected; when the microprocessor (101) connected with the first interface unit (141) is used as a master microprocessor in a dual-mode redundancy mode, receiving data fed back by the first routing unit (151) for comparison, wherein the data source is data corresponding to a storage instruction store executed by the slave microprocessor in the dual-mode redundancy mode; when the microprocessor (101) connected with the first interface unit (141) is used as a slave microprocessor in a dual-mode redundancy mode, the transmission microprocessor (101) executes data corresponding to the storage instruction store to the first routing unit (151);

the first routing units (151) are connected in pairs;

corresponding to any one first routing unit (151), receiving the data input by the first interface unit (141), and transmitting the data to the adjacent first routing unit (151); meanwhile, data input by an adjacent first routing unit (151) is received, when the address signal in the received data is judged to be matched with the address information of the first routing unit (151), the received data is transferred to the first interface unit (141), and when the address signal in the received data is judged not to be matched with the address information of the first routing unit (151), the received data is continuously transferred to the adjacent first routing unit (151);

the second interface unit (161) is used for comparing the data in the register file after the main microprocessor and the slave microprocessor finish a section of thread in the dual-mode redundancy mode, notifying the register file redundancy control unit (131) when finding different, restoring the register file to the state after the last section of thread is executed, and re-executing the thread with errors; after the microprocessor (101) finishes executing a thread, the second interface unit (161) sequentially receives data in the register file sent by the register file redundancy control unit (131) in the microprocessor (101); when the microprocessor (101) connected with the second interface unit (161) is used as a main microprocessor in a dual-mode redundancy mode, receiving data fed back by the second routing unit (171), and comparing the data with the received data in the register file sent by the register file redundancy control unit (131); when the microprocessor (101) connected with the second interface unit (161) is used as a slave microprocessor in a dual-mode redundancy mode, transmitting data in the register file sent by the register file redundancy control unit (131) to the second routing unit (171); judging whether register file data received by a second interface unit (161) connected with a master-slave microprocessor (101) in a dual-mode redundancy mode are the same or not, and feeding back a judgment result to respective register file redundancy control units (131);

the second routing unit (171) receives the data input by the second interface unit (161) and transmits the data to the corresponding second routing unit (171) in the dual-mode redundancy mode; and receiving data input by the adjacent second routing unit (171), transmitting the received data to the second interface unit (161) when judging that the address signal in the received data is matched with the address information of the own second routing unit (171), and continuously transmitting the received data to the adjacent second routing unit (171) when judging that the address signal in the received data is not matched with the address information of the own second routing unit (171).