CN111181551A

CN111181551A - Signal sampling method, logic device and network equipment

Info

Publication number: CN111181551A
Application number: CN202010071192.0A
Authority: CN
Inventors: 林贝贝; 林晖; 方春飞; 徐俊杰
Original assignee: New H3C Technologies Co Ltd Hefei Branch
Current assignee: New H3C Technologies Co Ltd Hefei Branch
Priority date: 2020-01-21
Filing date: 2020-01-21
Publication date: 2020-05-19
Anticipated expiration: 2040-01-21
Also published as: CN111181551B

Abstract

The disclosure provides a signal sampling method, a logic device and network equipment, and aims to solve the problem that the number of carry chain stages of the logic device is too high in the prior art. According to the signal sampling method provided by the disclosure, a plurality of sampling clock signals with the same frequency and different phases are generated through a clock management module, and the plurality of clock signals with the same frequency but different phases are output to different sampling modules, so that the sampling modules sample a plurality of signals to be sampled after delay through a delay chain according to the received clock signals, and because the number of the delay modules is determined by the period of the sampling clock, the delay generated by each level of the delay module and the parallel number of the sampling clock, the number of the stages of the delay chain can be reduced under the condition that a plurality of sampling clocks are used for sampling in parallel. Compared with the prior art, the method can adapt to lower sampling clock frequency under the condition of unchanged precision.

Description

Signal sampling method, logic device and network equipment

Technical Field

The present disclosure relates to network communication technologies, and in particular, to a signal sampling method, a logic device, and a network device.

Background

In a communication network, many services depend on time synchronization of the whole network, and particularly, the current network is evolving towards 5G, and a bearer network needs to have the functions of large bandwidth, low delay, high-precision time synchronization, flexible networking and the like. The ultra-high precision time synchronization requires that the synchronization precision of a single device node is within 5 ns.

In the processing process of a common 1588 time synchronization protocol, a clock synchronization signal of each device node is generally based on a Pulse Per Second (PPS) generated by a Global Positioning System (GPS) receiver, and when a device samples a PPS edge, time synchronization is triggered. Therefore, the sampling precision of the PPS rising edge is an important aspect which influences the overall synchronization precision of the equipment.

In the prior art, high-precision signal sampling is commonly used in a Field Programmable Gate Array (FPGA), which is abbreviated as FPGA, to delay a signal through a carry chain, generate tap signals with different delays, further sample the tap signals through a clock signal, and determine the position of a signal edge according to a sampling result. Fig. 1 is a schematic diagram of a signal sampling scheme commonly used in the prior art, as shown in fig. 1, a signal T is input to a CARRY chain (CARRY chain) composed of a plurality of CARRY modules CARRY, wherein an upper stage CARRY is output and input to a lower stage CARRY, thereby generating N +1 tap signals T (0), T (1) … … T (N) in total, the N +1 tap signals are input to a sampling processing module, the sampling processing module samples the N +1 tap signals according to a sampling clock, and the sampling processing module outputs a position of an edge of the signal T according to a sampling result.

However, the above-mentioned techniques have the following technical problems: because the signal edge may be at any position in a sampling clock cycle, the delay of the carry chain is required to cover one sampling clock cycle, and assuming that the delay of the first-stage carry module is Dc and the sampling clock cycle is T, the stage number of the carry chain should be at least T/Dc, and when the sampling frequency is low, for example, 200MHz, if the required sampling precision is higher, for example, 40ps, the stage number of the carry chain is 125, which is too high, and it is difficult to implement in an actual FPGA.

Disclosure of Invention

The disclosure provides a signal sampling method to solve the problem of too high carry chain level in the prior art.

A first aspect of the present disclosure provides a signal sampling method, including: generating M clock signals according to a source signal of a sampling clock, wherein the frequency of the M clock signals is the same as that of the source signal, the phase distribution of the M clock signals is in arithmetic progression distribution, and the phase distribution of the M clock signals covers one clock period;

carrying out time delay processing on a signal to be sampled, and outputting N signals with different time delays;

sampling N +1 signals with different delays including the signal to be sampled according to a clock signal to obtain a sampling signal;

determining the edge position of a signal to be sampled according to the sampling signal;

wherein M and N are integers greater than or equal to 2.

According to the method, a plurality of clock signals with the same frequency but different phases are output to different sampling modules, so that the sampling modules sample a plurality of signals to be sampled after delay through a delay chain according to the received clock signals, and the number of the delay modules is determined by the period of the sampling clock, the delay generated by each level of delay module and the number of parallel sampling clocks, so that the number of stages of the delay chain can be reduced under the condition that a plurality of sampling clocks are used for sampling in parallel. Compared with the prior art, the method can adapt to lower sampling clock frequency under the condition of unchanged precision.

The second aspect of the present disclosure also provides a signal sampling method, including:

step 100, generating an error measurement signal;

step 102, changing the phase of the error measurement signal, and executing steps 104 to 110 until the changed phase of the error measurement signal covers the period of the error measurement signal;

104, generating M clock signals according to a source signal of a sampling clock, wherein the frequency of the M clock signals is the same as that of the source signal, the phase distribution of the M clock signals is in arithmetic progression distribution, and the phase distribution of the M clock signals covers one clock period;

106, performing delay processing on the error measurement signals, and outputting N signals with different delays;

step 108, sampling N +1 signals with different delays including the error measurement signal according to a clock signal to obtain a first sampling signal;

step 110, determining an edge position of an error measurement signal according to the first sampling signal; wherein M and N are integers greater than or equal to 2;

step 112, generating a mapping relationship between the corrected edge position and the sampled edge position according to the changed phase of the error measurement signal and the determined edge position of the error measurement signal.

In a signal sampling method provided by the second aspect of the present disclosure, the clock management module adjusts the phase of the error measurement signal, and by repeatedly performing steps 104 to 110, a mapping table including a plurality of changed phases and the position of the edge finally obtained by sampling is generated, where the mapping table is equivalent to store the corresponding relationship between the actual position of the edge (the actual position of the edge can be determined by the changed phases) and the position of the edge obtained by sampling. On the basis of the method provided by the second aspect, a third aspect of the present disclosure provides a signal sampling method, including:

when a signal to be sampled is received, carrying out time delay processing on the signal to be sampled, and outputting N signals with different time delays;

generating M clock signals according to a source signal of a sampling clock, wherein the frequency of the M clock signals is the same as that of the source signal, the phase distribution of the M clock signals is in arithmetic progression distribution, and the phase distribution of the M clock signals covers one clock period;

sampling N +1 signals with different delays including the signal to be sampled according to a clock signal to obtain a second sampling signal;

determining the edge position of the signal to be sampled according to the second sampling signal;

and searching the mapping relation according to the edge position of the signal to be sampled, and outputting a hit corrected edge position when the edge position of the signal to be sampled hits the edge position obtained by sampling in the mapping relation.

By the method provided by the disclosure, in a sampling mode, the edge position of the sampling signal can be corrected by searching the mapping table, and the corrected edge position is output, so that the system error is eliminated, and the sampling precision is improved.

A fourth aspect of the present disclosure provides a signal sampling method based on the method provided in any of the first to third aspects, where the delay chain may include one delay chain, or may include a plurality of delay chains, and the plurality of delay chains are connected in parallel with each other, and a delay difference between the delay chains is not zero.

By using multiple delay chains, higher sampling accuracy can be achieved.

In a fifth aspect of the present disclosure, a logic device is provided, which may be used to perform the sampling method provided in the first to fourth aspects, and the logic device includes: the device comprises a clock management module, a delay chain, a sampling module and a data processing module; the clock management module and the delay chain are connected with the sampling module, and the data processing module is connected with the sampling module;

in the case of a logic device operating in sampling mode,

the clock management module is used for generating M clock signals according to a source signal of a received sampling clock, wherein the frequency of the M clock signals is the same as that of the source signal, the phase distribution of the M clock signals is in arithmetic progression distribution, and the phase distribution of the M clock signals covers one clock period;

the delay chain composed of N delay modules is used for outputting N signals with different delays after the signals to be sampled are subjected to delay processing;

each sampling module in the M sampling modules is used for receiving N +1 signals with different delays including the signal to be sampled and a clock signal;

each sampling module samples N +1 received signals with different delays according to a clock signal;

the data processing module is used for receiving the sampling signals output by each sampling module and determining the edge position of the signal to be sampled according to the received sampling signals;

wherein M and N are integers greater than or equal to 2.

In a fifth aspect of the present disclosure, a logic device is provided, which includes: the device comprises a clock management module, a delay chain, a sampling module, a data processing module, a control module and a signal selection module;

in the case where the logic device is operating in an error measurement mode,

the signal selection module selects an error measurement signal to be input into the first delay chain;

the control module controls the clock management module to change the phase of the error measurement signal;

the clock management module outputs M clock signals according to source signals of the sampling clock, the frequency of the M clock signals is the same as that of the source signals, and the phase distribution of the M clock signals is in arithmetic progression distribution;

a first delay chain consisting of N delay modules delays the error measurement signal E and outputs N signals with different delays;

each sampling module in the M sampling modules receives N +1 signals with different delays including error measurement signals and clock signals, and each sampling module samples the received N +1 signals with different delays according to the clock signals;

the data processing module receives the sampling signals output by each sampling module, and determines the edge position of the error measurement signal according to the received sampling signals;

the steps after changing the phase of the error measurement signal are repeated until the edge positions determined by the different phases within one complete cycle of the error measurement signal are recorded.

Drawings

FIG. 1 is a schematic diagram of a signal sampling scheme commonly used in the prior art;

FIG. 2 is a schematic diagram of a logic device according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a logic device according to another embodiment of the present invention;

FIG. 4 is a schematic diagram of a logic device according to yet another embodiment of the present invention;

fig. 5 is a flowchart of a signal sampling method according to a first embodiment of the disclosure;

fig. 6 is a flowchart of a sampling method according to another embodiment of the present disclosure.

Detailed Description

Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. In the drawings, like reference numbers can indicate functionally identical or similar elements. While the various aspects of the embodiments are presented in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

The word "exemplary" is used exclusively herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

The problem that the number of carry chain stages is too high in the prior art is solved. According to the signal sampling method provided by the disclosure, a plurality of sampling clock signals with the same frequency and different phases are generated through a clock management module, and the plurality of clock signals with the same frequency but different phases are output to different sampling modules, so that the sampling modules sample a plurality of signals to be sampled after delay through a delay chain according to the received clock signals, and because the number of the delay modules is determined by the period of the sampling clock, the delay generated by each level of the delay module and the parallel number of the sampling clock, the number of the stages of the delay chain can be reduced under the condition that a plurality of sampling clocks are used for sampling in parallel. Compared with the prior art, the method can adapt to lower sampling clock frequency under the condition of unchanged precision.

Fig. 2 shows a schematic structure diagram of a logic device that can execute the above method of the present disclosure. The logic means may include, but are not limited to: an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), a Complex Programmable Logic Device (CPLD), or any other Programmable Logic Device. As shown in fig. 2, the logic device includes: a first clock management module 21, a first delay chain 22, a plurality of sampling modules 23-1 to 23-M and a data processing module 24.

It should be noted that the logic device may report a plurality of delay chains, and in this embodiment, one delay chain is taken as an example, i.e., the first delay chain 22 is described.

The delay chain is formed by first-stage end-to-end connection of a plurality of delay modules, and in fig. 2, the first delay chain 22 includes the delay modules 22-1 to 22-N as an example. The delay module is used for delaying a signal to be sampled, so that resources which can achieve the purpose of delay can be used for implementation of the module, for example, a Look-Up-Table (Look-Up-Table) of a logic device can be selected for implementation, a CARRY can be selected for implementation, and an input/output delay unit IODELAY can also be selected for implementation. Because the delay precision of each stage of delay module directly determines the minimum sampling precision which can be theoretically reached, the delay modules realized by different resources have different delays, but the smaller the delay, the higher the stage number, and the choice can be made according to the actual situation. In a preferred embodiment, the CARRY is used as a delay module, and the delay consistency of each stage of CARRY is better.

The first clock management module 21 may be implemented by a Mixed Mode clock manager (MMCM for short).

The logic device may execute the method shown in fig. 5, and fig. 5 is a flowchart of a signal sampling method provided in a first embodiment of the disclosure, and as shown in fig. 5, the method includes:

step 210, generating M clock signals according to a source signal of a sampling clock, wherein the M clock signals have the same frequency as the source signal, the phase distribution of the M clock signals is in arithmetic progression distribution, and the phase distribution of the M clock signals covers one clock period;

step 212, performing delay processing on the signal to be sampled, and outputting N signals with different delays;

step 214, sampling N +1 signals with different delays including the signal to be sampled according to a clock signal to obtain a first sampling signal;

and step 216, determining the edge position of the signal to be sampled according to the first sampling signal. Wherein M and N are integers greater than or equal to 2.

For convenience of understanding, the present embodiment describes the above method in detail with reference to specific modules of the logic device in fig. 2, specifically, the method includes:

in step 310, the first clock management module 21 outputs M clock signals according to the source signal of the received sampling clock, where the M clock signals have the same frequency as the source signal, the phase distributions of the M clock signals are distributed in an arithmetic progression, and the phase distributions of the M clock signals cover one clock cycle.

In step 312, after the first delay chain composed of the N delay modules performs delay processing on the signal to be sampled, the first delay chain outputs N signals with different delays.

Step 314, each sampling module of the M sampling modules receives N +1 signals with different delays including the signal to be sampled and a clock signal, and each sampling module samples the received N +1 signals with different delays according to the clock signal;

in step 316, the data processing module 24 receives the sampling signals output by the sampling modules, and determines the edge positions of the signals to be sampled according to the received sampling signals.

In this embodiment, on one hand, the first clock management module 21 is configured to output a plurality of clock signals having the same frequency as the sampling clock source signal but different phases, and on the other hand, the first delay chain delays the signal to be sampled. Finally, the sampling module performs edge sampling on the signal to be sampled after the delay according to the frequency indicated by the clock signal output to each sampling module by the first clock management module 21.

In the first aspect indicated in the above paragraph, the clock signal output by the first clock management module 21 will be described in this embodiment by taking M-4 as an example. The first clock management module 21 receives a source signal S _ CLK of the sampling clock and outputs 4 clock signals, CLK-1, CLK-2, CLK-3, CLK-4, having the same frequency as the source signal. The phases of CLK-1 to CLK-4 are distributed in an arithmetic progression and the phase distribution of the M clock signals covers one clock cycle.

In an alternative embodiment, the phase difference of the clock signals is 90 degrees:

the phase of CLK-1 is consistent with S _ CLK;

the phase of CLK-2 is 90 degrees different from that of S _ CLK, namely the rising edge of S _ CLK is shifted to the right by 90 degrees;

the phase of CLK-3 is 180 degrees different from that of S _ CLK, namely the rising edge of S _ CLK is shifted to the right by 180 degrees;

CLK-4 is 270 degrees out of phase with S _ CLK, i.e., the rising edge of S _ CLK is shifted to the right by 270 degrees.

Of course, in order to further reduce the number of delay modules, M may also be equal to 8 in another alternative embodiment, that is, the first clock management module 21 generates 8 clock signals (CLK-11, CLK-12, CLK-21, CLK-22, CLK-31, CLK-32, CLK-41, and CLK42), and the phase difference of each clock signal may also be 45 degrees:

the phase of CLK-11 is consistent with S _ CLK;

the phase of CLK-12 is 45 degrees different from that of S _ CLK, i.e. the rising edge of S _ CLK is shifted to the right by 45 degrees;

the phase of CLK-21 is 90 degrees different from that of S _ CLK, i.e. the rising edge of S _ CLK is shifted to the right by 90 degrees;

the phase of CLK-22 is 135 degrees different from that of S _ CLK, i.e. the rising edge of S _ CLK is shifted to the right by 135 degrees;

the phase of CLK-31 is 180 degrees different from that of S _ CLK, i.e. the rising edge of S _ CLK is shifted to the right by 180 degrees;

the phase of CLK-32 is 225 degrees from that of S _ CLK, i.e., the rising edge of S _ CLK is shifted to the right by 225 degrees;

the phase of CLK-41 is 270 degrees different from that of S _ CLK, i.e. the rising edge of S _ CLK is shifted to the right by 270 degrees;

the phase of CLK-42 is 315 degrees from S _ CLK, i.e., the rising edge of S _ CLK is shifted to the right by 315 degrees.

Further, as shown in fig. 2, M clock signals output by the first clock management module 21 are respectively output to M sampling modules in a one-to-one correspondence manner, as shown in fig. 2, the first clock management module 21 outputs the clock signal CLK-1 to the sampling module 23-1, and outputs the clock signal CLK-2 to the sampling module 23-2 … …, and outputs the clock signal CLK-M to the sampling module 23-M.

Another aspect to the foregoing is achieved by step 312. Specifically, a signal T to be sampled is input into the delay module 21-1, after the delay module 21-1 delays the signal T, on one hand, the delayed signal T (1) is output to the sampling module 23-1 to the sampling module 23-M, on the other hand, the delayed signal T (1) is output to the next-stage delay module 21-2, after the next-stage delay module 21-2 delays the received signal T (1), the delayed signal T (2) is output to the next-stage delay module 21-3, and the T (2) is output to the sampling module 23-1 to the sampling module 23-M … …, and so on, and N signals with different delays are obtained through N delay modules: t (1) … T (N). Meanwhile, each of the M sampling modules receives the N delayed signals and the non-delayed signal T to be sampled. And each sampling module samples the N +1 signals with different delays according to the sampling signal output by the first clock management module.

The sampling module 23-1 samples N +1 signals with different delays to obtain sampling data:

S_0(0)、S_0(1)…S_0(N)；

the sampling module 23-2 samples N +1 signals with different delays to obtain sampling data:

S_1(0)、S_1(1)…S_1(N)；

the sampling module 23-3 samples N +1 signals with different delays to obtain sampling data as follows:

S_2(0)、S_2(1)…S_2(N)；

……

the sampling module 23-M samples N +1 signals with different delays to obtain sampling data as follows: s _ M (0), S _ M (1) … S _ M (N).

It should be noted that, for the convenience of description, the N +1 signals with different delays in step 314 actually include the signal T to be sampled without delay, i.e., the signal T (1) ….. T (N) after being actually subjected to the delay processing by the delay module and the signal T to be sampled without being subjected to the delay processing by the delay module need to be output to the sampling module, which is the N +1 signals with different delays including the signal T to be sampled in step 314.

The number N of delay modules, which may also be referred to as a number of delay stages, needs to be determined according to a period TS _ CLK of the sampling clock, a delay D generated by each stage of delay module, and a parallel number M of clock signals, and is specifically calculated as N ═ TS _ CLK/D/M.

Therefore, under the condition that the period of the sampling clock is determined, the sampling method adopted by the embodiment adopts a plurality of sampling clock signals with the same frequency and different phases, so that the sampling module can sample the signals processed by the delay module in parallel. Under the condition of a certain resource (namely under the condition of a certain number N of delay modules), the larger the parallel number M of the clock signals is, the larger the period TS _ CLK of the sampling clock signal is (the smaller the frequency of the sampling clock signal is), so that the sampling clock signal can adapt to a lower sampling clock frequency under the condition of unchanged precision, and the time sequence can better converge. From another perspective, the greater the number M of clock signals in parallel, the smaller the number N of delay modules required, given the period TS _ CLK of the sampling clock.

In addition, since the delay of each stage of delay module is not made to be identical, in an alternative implementation, several stages of delay modules may be added according to actual situations.

In step 316, the sampling modules 23-1 to 23-M output the sampled sampling data to the data processing module 24, and the data processing module 24 determines the edge position of the signal to be sampled.

The determination of the position of the edge is to find out whether there is an edge transition in the current sample data, and the relative position of the edge with respect to the rising edge of the sampling clock.

One algorithm that can be implemented to determine the edge position is to search sequentially from the sampled data of S _0(0), S _0(1) … S _0(N), S _1(0), S _1(1) … S _ M (N), and find the position of the first level transition, i.e., consider the edge.

In practical situations, because each stage of bit chain cannot always delay the same time, the sampling precision of different versions will be different finally; in addition, due to the influence of environmental factors such as temperature and voltage, the delay of each stage of carry chain and internal routing changes, which causes an error between the edge position of the output and the actual position, which is referred to as a system error in the present disclosure.

In an alternative embodiment, the systematic error may be measured and corrected using the measured systematic error to determine the exact edge position of the signal to be sampled.

Specifically, fig. 6 is a flowchart of a sampling method according to yet another embodiment of the present disclosure, and as shown in fig. 6, the data processing module 24 may search a mapping relationship between a stored corrected edge position and a sampled edge position according to the edge position determined in step 316, and output the corrected edge position when the edge position determined in step 316 hits the sampled edge position in the mapping relationship.

How the mapping relationship is generated is described in the following embodiments, and details are not described here.

Example two

On the basis of the signal sampling method provided by the above embodiment, in order to improve the accuracy of determining the edge, the present disclosure also provides a signal sampling method, which corrects a systematic error existing in the process of determining the edge. In this embodiment, the phase of the error measurement signal is adjusted by the clock management module, and since the amount of the adjusted phase can be known, it is equivalent to that the edge position of the error measurement signal is known in advance, and by changing the phase for a plurality of times, a mapping table including a plurality of changed phases and the edge position obtained by final sampling is generated, and the mapping table is equivalent to that the corresponding relationship between the actual position of the edge (the actual position of the edge can be determined by the changed phase) and the edge position obtained by sampling is stored. By means of the mapping table, the corrected edge positions can be determined, so that systematic errors can be corrected.

Fig. 3 is a schematic structural diagram of a logic device that can execute the above logic device for error correction according to the present disclosure, and as shown in fig. 3, the logic device further includes: a signal selection module 31, a second clock management module 32, and a control module 33.

The control module 33 is configured to trigger entering the error measurement mode, where the trigger condition may be any one of the following conditions:

when the system is electrified and initialized, the temperature and humidity change of the device meets a preset threshold value, the voltage fluctuation range meets the preset threshold value, and a preset error detection period is met.

When the control module 33 determines that the above triggering condition is satisfied, the control module 33 triggers the second clock management module 32 to generate an error measurement signal according to the generated error measurement signal. In an alternative embodiment, a central processing Unit may be used to implement the functions of the control module 33.

The signal selection module 31 is configured to select a signal to be input into the carry chain, and if the signal to be sampled is selected, the logic device enters a sampling mode, where the sampling mode is that the signal selection module 31 selects the signal to be sampled T to be input into the carry chain, and then performs the sampling mode for sampling the signal to be sampled as described in the first embodiment. If the error measurement signal is selected, the logic device enters an error measurement mode, that is, the signal selection module 31 selects the error measurement signal E to be input to the carry chain, and further performs the sampling process described in this embodiment.

The second clock management block 32 is also arranged to change the phase of the error measurement signal under the control of the control block. Wherein the frequency E of the error measurement signal is the same as the frequency of the sampling clock.

Of course, in a specific implementation, in the case of the error measurement mode, the first clock management module 21 and the second clock management module 32 may be the same hardware entity, and from the aspect of simplicity and convenience of implementation, two clock management modules (two hardware entities) may be respectively adopted, where the first clock management module 21 is configured to operate in the sampling mode, and the second clock management module 32 is configured to operate in the error measurement mode.

In this embodiment, the second clock management module 32 is used to change the phase of the error measurement signal, and the first clock management module 21 is used to generate a plurality of parallel clock signals according to the source signal.

Next, the present embodiment will explain how to obtain the system error by using a specific example.

Step 410, the signal selection module 31 selects the error measurement signal E to be input to the first delay chain;

in step 412, the control module 33 controls the second clock management module 32 to change the phase of the error measurement signal E.

The initial phase coincides with the phase of the source signal S _ CLK in step S310;

step 414, the first clock management module 21 outputs M clock signals according to a source signal of the sampling clock, where the M clock signals have the same frequency as the source signal, and the phase distributions of the M clock signals are distributed in an arithmetic progression;

in step 416, after the error measurement signal E is delayed by the first delay chain composed of N delay modules, N signals with different delays are output.

In step 418, each of the M sampling modules receives N +1 signals with different delays including the error measurement signal E and a clock signal, and each sampling module samples the N +1 signals with different delays according to the clock signal.

In step 420, the data processing module 24 receives the sampling signals output by the sampling modules, and determines an edge position P0 of the error measurement signal E according to the received sampling signals.

Step 422, the control module 33 controls the initial phase of the error measurement signal E to differ from S _ CLK by 90 degrees;

the steps 412-420 are repeated until the edge positions determined by the different phases within one complete cycle of the recorded error measurement signal are P1, P2, P3 … … Pr, where r is a positive integer, and the value of r is determined by the sampling accuracy, e.g., if the sampling accuracy f is 50ps, the phase of each change in step 412 cannot exceed 2 pi f/T1, where T1 is the period of the sampling clock.

In an alternative embodiment, the precision of the phase adjustment of the second clock management module 32 is smaller than that of the delay module, so that the problem that when the second clock management module 32 adjusts one phase, the actual edge position crosses multiple delay modules, and the edge position cannot be determined can be avoided.

In step 412, the phase of the error measurement signal is adjusted by the second clock management module 32, and since how much the phase is adjusted is known, it is equivalent to knowing the edge position of the error measurement signal in advance.

Thus, a mapping table may be generated according to the phase changed in step 412 and the edge position finally obtained by sampling, and the mapping table is equivalent to store the corresponding relationship between the actual position of the edge (the actual position of the edge can be determined by the changed phase) and the position of the edge obtained by sampling. Table 1 is a mapping table storing the correspondence between the corrected edge positions and the edge positions obtained by sampling. The corrected edge position can be considered as the actual position of the edge.

TABLE 1

When the logic device operates in the sampling mode, the corrected edge position may be determined by looking up a mapping table as shown in table 1, for example, when the edge position output in step 316 is P3, the corrected edge position may be determined to be F3 by the mapping table, and thus the data processing module 24 outputs the corrected edge position F3, that is, the true edge position of the signal T to be sampled is considered to be F3.

The mapping table of table 1 may be stored in a storage medium, for example, written into a Random Access Memory (RAM).

EXAMPLE III

On the basis of the first embodiment and the second embodiment, in order to achieve higher sampling accuracy, the sampling method can be implemented by adopting a plurality of delay chains. The difference in delay between the parallel delay chains is not zero. In an alternative implementation, on the basis that there is one delay chain, i.e. the first delay chain 22, in the first and second embodiments, for convenience of description, the delay chain added in this embodiment is referred to as a second delay chain, and the second delay chain may be multiple.

The second delay chain also comprises a delay submodule which delays the signal to be sampled by D/P and then inputs the signal to the subsequent delay module of the delay chain to be matched with the first delay chain, so that although the delay of each stage of delay module is not changed, the theoretical sampling precision is improved by one time. Wherein, P is the total number of the delay chains, and D is the delay of each stage of the delay module.

For example, if the number of the second delay chains is 2, which are respectively recorded as the delay chain 43 and the delay chain 44, that is, the total number of the delay chains is 3, the delay submodule 43-0 delays D/3 to input to the subsequent delay module of the delay chain 43, and the delay submodule 44-0 delays 2D/3 to input to the subsequent delay module of the delay chain 44, so that the delay difference of each delay chain is not zero. Thereby realizing that a plurality of delay chains output signals with different delays.

Fig. 4 is a schematic diagram of a logic device with two delay chains, which is illustrated by taking an example that a delay chain includes 3 delay modules, where the delay chain includes a delay module 21-1 to a delay module 21-3, the delay chain includes a delay module 53-1 to a delay module 53-3, and a delay submodule 53-0. The delay modules 53-1 to 53-3 of the delay chain may be identical to the delay modules 21-1 to 21-3 of the delay chain. If two delay chains coexist in the logic device, the delay submodule 53-0 delays D/2 and then inputs the delayed signal to the delay module 53-1. Fig. 4 illustrates only one sampling module as an example, but it should be understood that a plurality of sampling modules are included in the logic device.

The logic apparatus provided in any of the above embodiments may be applied to a network device, for example, a router, a switch, a base station, and the like. Of course, the method can also be applied to oscilloscope products during testing so as to measure time and collect signals.

In order to further clarify the technical solutions and technical effects achieved by the present disclosure, the present disclosure further describes the above signal sampling method through the following embodiments. Furthermore, in the following detailed description, numerous specific details are set forth in order to provide a better understanding of the present disclosure. It will be understood by those skilled in the art that the present disclosure may be practiced without some of these specific details. In some instances, methods, means, elements and circuits that are well known to those skilled in the art have not been described in detail so as not to obscure the present disclosure.

In the embodiments provided in the present disclosure, it should be understood that the disclosed apparatus and method may be implemented in other ways. The apparatus embodiments described above are merely illustrative, and for example, the flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

In addition, functional modules in the embodiments of the present disclosure may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

The above description is only exemplary of the present disclosure and should not be taken as limiting the disclosure, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present disclosure should be included in the scope of the present disclosure.

Claims

1. A method of sampling a signal, the method comprising:

wherein M and N are integers greater than or equal to 2.

2. The method of claim 1, further comprising:

and searching a mapping relation between the stored corrected edge position and the edge position obtained by sampling according to the edge position, and outputting the hit corrected edge position when the edge position hits the edge position obtained by sampling in the mapping relation.

3. The method of claim 1 or 2, wherein the delay chain comprises a delay chain; or the delay chain comprises a plurality of parallel delay chains, and the delay difference between the parallel delay chains is not zero.

4. A method of sampling a signal, the method comprising:

step 100, generating an error measurement signal;

5. The method of claim 4, further comprising:

6. The method of claim 4 or 5, wherein the delay chain comprises a delay chain;

or the delay chain comprises a plurality of parallel delay chains, and the delay difference between the parallel delay chains is not zero.

7. A logic device, comprising: the device comprises a clock management module, a delay chain, a sampling module and a data processing module;

the delay chain composed of N delay modules is used for outputting N signals with different delays after the delay processing is carried out on the signal to be sampled or the error measurement signal;

each sampling module in the M sampling modules is used for receiving N +1 signals with different delays and clock signals including the signals to be sampled or error measurement;

wherein M and N are integers greater than or equal to 2.

8. The logic device as recited in claim 7,

the data processing module is further configured to search a stored mapping relationship between the corrected edge position and the edge position obtained by sampling according to the edge position of the signal to be sampled, and when the edge position of the signal to be sampled hits the edge position obtained by sampling in the mapping relationship, the data processing module outputs the hit corrected edge position.

9. The logic device of claim 7, wherein the delay chain comprises a delay chain; or the delay chain comprises a plurality of parallel delay chains, and the delay difference between the parallel delay chains is not zero.

10. The logic device according to any of claims 7-9, further comprising: the device comprises a control module and a signal selection module;

the control module is used for triggering and generating an error measurement signal when a triggering condition is met;

the signal selection module is used for selecting a signal to be input into the carry chain under the control of the control module, wherein the signal to be input into the carry chain comprises a signal to be sampled or an error measurement signal;

the clock management module is used for changing the phase of the error measurement signal under the control of the control module.

11. A network device, characterized in that it comprises the logic means of any of claims 7-10.