CN111181512A - Amplifier, tail current stabilizing method, input receiver and chip - Google Patents
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- CN111181512A CN111181512A CN201811330501.0A CN201811330501A CN111181512A CN 111181512 A CN111181512 A CN 111181512A CN 201811330501 A CN201811330501 A CN 201811330501A CN 111181512 A CN111181512 A CN 111181512A
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- 238000000034 method Methods 0.000 title claims abstract description 16
- 230000000087 stabilizing effect Effects 0.000 title abstract description 14
- 230000003321 amplification Effects 0.000 claims description 21
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 21
- 239000000872 buffer Substances 0.000 claims description 8
- 230000006641 stabilisation Effects 0.000 claims description 2
- 238000011105 stabilization Methods 0.000 claims description 2
- 230000006903 response to temperature Effects 0.000 claims 1
- 230000003313 weakening effect Effects 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 3
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
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Abstract
The invention provides an amplifier, a tail current stabilizing method, an input receiver and a chip. The amplifier comprises a first transistor, a second transistor and a temperature control unit, wherein the grid electrode of the first transistor is connected with bias voltage, one end of the first transistor is connected with the source electrode of the input geminate transistor, the other end of the first transistor is grounded, and the first transistor is used for generating first tail current; one end of the second transistor is connected between the first transistor and a source electrode connecting wire of the input geminate transistor, the other end of the second transistor is grounded, and the second transistor is used for generating a second tail current; the temperature control unit is connected with the grid electrode of the second transistor and used for adjusting the voltage connected to the grid electrode of the second transistor according to the detected temperature of the first transistor, so that the sum of the first tail current and the second tail current is kept at a constant value. The invention keeps the stability of the whole tail current by adjusting the second tail current, thereby weakening or eliminating the influence of the temperature of the first transistor on the tail current and stabilizing the working state of the amplifier circuit at the required performance.
Description
Technical Field
The invention relates to a semiconductor memory, in particular to an amplifier, a tail current stabilizing method, an input receiver and a chip.
Background
In an Input Receiver (Input Receiver) of a Dynamic Random Access Memory (DRAM), a small Input signal is amplified into a Full Swing signal of Rail-to-Rail (Rail-to-Rail) through two-stage Input buffers (Input buffers) so that an internal circuit normally operates. The two-stage input buffer is an amplifier with different structures.
However, since the current of the MOS transistor is affected by temperature variation, the tail current of the amplifier varies with the temperature variation, which causes the quiescent operating voltage of the amplifier to be different from the expected value, thereby affecting the performance of the amplifier, and causing a certain error in the performance of the input receiver and the expected value.
Disclosure of Invention
The invention provides an amplifier, a tail current stabilizing method, an input receiver and a chip, which are used for relieving or solving at least one technical problem in the prior art.
In a first aspect, an embodiment of the present invention provides an amplifier, including:
a first transistor, wherein a gate of the first transistor is connected with a bias voltage (EN), one end of the first transistor is connected with a source (U) of an input pair transistor, the other end of the first transistor is Grounded (GND), and the first transistor is used for generating a first tail current;
one end of the second transistor is connected between the first transistor and a source electrode connecting wire of the input geminate transistor, the other end of the second transistor is grounded, and the second transistor is used for generating a second tail current;
and the temperature control unit is connected with the grid electrode of the second transistor and used for adjusting the voltage connected to the grid electrode of the second transistor according to the temperature of the first transistor detected by the temperature sensor so as to keep the sum of the first tail current and the second tail current at a constant value.
In one embodiment, further comprising a differential unit, the differential unit comprising:
a first resistor having one end connected to a power supply Voltage (VCC);
one end of the second resistor is connected with a power supply voltage;
the drain electrode of the third transistor is connected with the other end of the first resistor, and the grid electrode of the third transistor is connected with an input voltage;
a fourth transistor, a drain of which is connected to the other end of the second resistor, a gate of which is connected to a reference voltage (Vref), and a connection point between a source of the third transistor and a source of the fourth transistor, which is used as a source of the pair of input transistors, is connected to the drain of the first transistor;
a first amplification output terminal disposed on a connection line of the first resistor and the third transistor;
and the second amplification output end is arranged on a connecting line of the second resistor and the fourth transistor.
In one embodiment, the apparatus further comprises an operational amplification unit, the operational amplification unit comprising:
a fifth transistor, a gate of which is connected to the first amplification output terminal;
a sixth transistor, a gate of which is connected to the second amplification output terminal, and a connection point between a source of the fifth transistor and a source of the sixth transistor is connected to a drain of the first transistor as a source of the input pair transistor;
a seventh transistor, a source of which is connected to a power supply voltage, and a drain of which is connected to a drain of the fifth transistor;
a sixth transistor, a source of which is connected to a power supply voltage, a drain of which is connected to a drain of the sixth transistor, a gate of which is connected to a gate of the seventh transistor, and a gate of which is shorted with the drain;
and the third amplification output end is arranged on a connecting line of the fifth transistor and the seventh transistor.
In one embodiment, the first transistor is an NMOS transistor, a drain of the first transistor is connected to a source of the input pair transistor, and a source of the first transistor is grounded.
In one embodiment, the second transistor is an NMOS transistor, a drain of the second transistor is connected between a drain of the first transistor and a source connection line of the input pair transistor, and a source of the second transistor is grounded.
In a second aspect, an embodiment of the present invention provides an amplifier tail current stabilizing method, including:
detecting a temperature of the first transistor;
when the first transistor has temperature change, the voltage connected to the grid electrode of the second transistor is adjusted according to the temperature change, so that the sum of the second tail current and the first tail current is kept at a constant value.
In one embodiment, the method for adjusting the voltage applied to the gate of the second transistor according to the temperature change when the first transistor has the temperature change comprises the following steps:
when the temperature change causes the first tail current of the first transistor to increase, the voltage connected to the grid electrode of the second transistor is reduced so as to reduce the second tail current generated by the second transistor;
when the temperature change enables the first tail current of the first transistor to be reduced, the voltage connected to the grid electrode of the second transistor is increased, and therefore the second tail current generated by the second transistor is increased.
To achieve the above object, a third aspect of the present embodiment provides an input receiver including an amplifier as described in any of the above embodiments.
In order to achieve the above object, a fourth aspect of the present invention provides an input receiver, including two stages of output buffers, where the two stages of output buffers are formed by connecting the two amplifiers with different structures, where the first amplification output terminal is connected to a gate of the fifth transistor, and the second amplification output terminal is connected to a gate of the sixth transistor;
the amplifier further comprises:
and a bias transistor, one end of which is connected to the source of the third transistor, the source of the fourth transistor, and the drain of the second transistor, respectively, the other end of which is connected to the drain of the first transistor, and the gate of which is connected to a bias voltage.
To achieve the above object, a fifth aspect of the present embodiment provides a chip including the input receiver as described above.
The invention keeps the stability of the whole tail current by generating and adjusting the second tail current, thereby weakening or eliminating the influence of the temperature of the first transistor on the tail current, stabilizing the working state of the amplifier circuit at the required performance and weakening or eliminating the change of the output of the input receiver along with the temperature.
The foregoing summary is provided for the purpose of description only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features of the present invention will be readily apparent by reference to the drawings and following detailed description.
Drawings
In the drawings, like reference numerals refer to the same or similar parts or elements throughout the several views unless otherwise specified. The figures are not necessarily to scale. It is appreciated that these drawings depict only some embodiments in accordance with the disclosure and are therefore not to be considered limiting of its scope.
FIG. 1 is a circuit diagram of an amplifier according to an embodiment of the present invention
FIG. 2 is a circuit diagram of a differential unit in an amplifier according to an embodiment of the present invention;
FIG. 3 is a circuit diagram of an operational amplifier unit in the amplifier according to the embodiment of the present invention;
FIG. 4 is another circuit diagram of an amplifier according to an embodiment of the present invention;
FIG. 5 is a flow chart of a method for stabilizing tail current by an amplifier according to an embodiment of the present invention;
FIG. 6 is another flow chart of a method for stabilizing tail current for an amplifier according to an embodiment of the present invention;
reference numerals:
100 a first transistor;
210 a second transistor;
220 a temperature control unit;
230 a temperature sensor;
300 a differential cell;
310 a first resistance;
320 a second resistor;
330 a third transistor;
340 a fourth transistor;
350 a first amplified output;
360 a second amplified output;
400 operational amplification means;
410 a fifth transistor;
420 a sixth transistor;
430 a seventh transistor;
440 an eighth transistor;
450 a third amplified output;
500 bias the transistor.
Detailed Description
In the following, only certain exemplary embodiments are briefly described. As those skilled in the art will recognize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.
A first aspect of the present embodiments provides an amplifier.
Referring to fig. 1, the amplifier includes: a first transistor 100, a second transistor 210 and a temperature control unit 220.
The gate of the first transistor 100 is connected to a bias voltage, one end of the first transistor 100 is connected to the source of the input pair transistor, the other end of the first transistor 100 is grounded, and the first transistor 100 is configured to generate a first tail current. The first transistor 100 has a temperature-dependent characteristic, and the generated first tail current varies with the temperature.
One end of the second transistor 210 is connected between the first transistor 100 and the source connection line of the input pair transistor, the other end of the second transistor 210 is grounded, and the second transistor 210 is used for generating a second tail current.
The temperature control unit 220 is connected to the gate of the second transistor 210, and the temperature control unit 220 is configured to adjust a voltage applied to the gate of the second transistor 210 according to the temperature of the first transistor 100 detected by the temperature sensor 230, so that the sum of the first tail current and the second tail current is kept at a constant value. The temperature sensor 230 is an internally existing unit, so that the area of the amplifier can be reduced. For example: when the amplifier is applied to a semiconductor memory, the temperature sensor 230 may be a unit for controlling a self-refresh frequency inside the semiconductor memory. Where the constant value includes, but is not limited to, a set operating current range or an exact value. For example: allowing a constant value within the error range.
Thus, when the temperature of the first transistor 100 changes, the temperature control unit 220 adjusts the voltage connected to the gate of the second transistor 210 according to the temperature change to generate the second tail current, so that the overall tail current (the sum of the first tail current and the second tail current) of the amplifier can be kept stable even when the first tail current changes, and the stability of the performance of the amplifier is further ensured.
Further, the first transistor 100 is an NMOS transistor, a drain of the first transistor 100 is connected to a source of the input pair transistor, and a source of the first transistor 100 is grounded.
Further, the second transistor 210 is an NMOS transistor, the drain of the second transistor 210 is connected between the drain of the first transistor 100 and the source of the input pair transistor, and the source of the second transistor 210 is grounded.
In this embodiment, when the first transistor 100 is subjected to temperature variation, the sum of the second tail current generated by the second transistor 210 and the first point tail current generated by the second transistor 210 is controlled to keep a constant value by adjusting the on-state voltage accessed to the gate of the second transistor 210, so as to ensure that the tail current of the amplifier is not affected by temperature, and the low-end drive of the NMOS transistor is adopted to ensure the power of the amplifier.
In one embodiment, referring to fig. 2, the amplifier further comprises a difference unit 300.
The difference unit 300 includes: a first resistor 310, a second resistor 320, a third transistor 330, a fourth transistor 340, a first amplified output terminal 350 and a second amplified output terminal 360.
The first resistor 310 is connected to a power supply voltage at one end. One end of the second resistor 320 is connected to the power supply voltage. The drain of the third transistor 330 is connected to the other end of the first resistor 310, and the gate of the third transistor 330 is connected to the input voltage. The drain of the fourth transistor 340 is connected to the other end of the second resistor 320, the gate of the fourth transistor 340 is connected to the reference voltage, and the connection point between the source of the third transistor 330 and the source of the fourth transistor 340 is connected to the drain of the first transistor 100 as the source of the pair of input transistors. The first amplified output terminal 350 is disposed on the connection line of the first resistor 310 and the third transistor 330. The second amplifying output terminal 360 is disposed on the connection line of the second resistor 320 and the fourth transistor 340.
In one embodiment, referring to fig. 3, the amplifier further comprises an operational amplification unit 400.
The operational amplification unit 400 includes: a fifth transistor 410, a sixth transistor 420, a seventh transistor 430, an eighth transistor 440, and a third amplified output 450.
Referring to fig. 4, the gate of the fifth transistor 410 is connected to the first amplified output terminal 350. The gate of the sixth transistor 420 is connected to the second amplification output terminal 360, and a connection point between the source of the fifth transistor 410 and the source of the sixth transistor 420 is connected to the drain of the other first transistor 100 as the source of the pair input transistors. A source of the seventh transistor 430 is connected to the power supply voltage, and a drain of the seventh transistor 430 is connected to a drain of the fifth transistor 410. The source of the eighth transistor 440 is connected to the supply voltage, the drain of the eighth transistor 440 is connected to the drain of the sixth transistor 420, the gate of the eighth transistor 440 is connected to the gate of the seventh transistor 430, and the gate and drain of the eighth transistor 440 are shorted. The third amplified output 450 is disposed on the connection line of the fifth transistor 410 and the seventh transistor 430.
In this embodiment, the two different amplifier circuit structures maintain the stability of the overall tail current by generating and adjusting the second tail current, thereby reducing or eliminating the influence of the temperature of the first transistor 100 on the tail current, and stabilizing the operating state of the amplifier circuit at the required performance.
The second aspect of the present embodiment provides a method for stabilizing the tail current of an amplifier.
Referring to fig. 5, the amplifier tail current stabilization method includes:
step S110: the temperature of the first transistor 100 is detected.
Step S120: when the first transistor 100 has a temperature change, the voltage connected to the gate of the second transistor 210 is adjusted according to the temperature change, so that the sum of the second tail current and the first tail current is kept at a constant value.
The sum of the second tail current and the first tail current is the overall tail current of the amplifier. Therefore, when the first tail current changes along with the temperature change, the second tail current is controlled by the temperature control unit 220, so that the sum of the first tail current and the second tail current is kept stable, the integral tail current of the amplifier is a constant value, and the stability of the performance of the amplifier is ensured.
Further, referring to fig. 6, the method for adjusting the voltage applied to the gate of the second transistor 210 according to the temperature change when the first transistor 100 has the temperature change in step S120 includes:
step S121: when the temperature variation increases the first tail current of the first transistor 100, the voltage coupled to the gate of the second transistor 210 is reduced to reduce the second tail current generated by the second transistor 210.
Step S122: when the temperature change decreases the first tail current of the first transistor 100, the voltage coupled to the gate of the second transistor 210 is increased to increase the second tail current generated by the second transistor 210.
In this embodiment, the gate voltage connected to the second transistor 210 is reversely adjusted along with the temperature change, so as to control the magnitude of the second tail current, and keep the sum of the first tail current and the second tail current as a constant value, thereby making the tail current of the whole amplifier be a constant value, and ensuring the stability of the performance of the amplifier without being influenced by temperature.
A third aspect of the present embodiments provides an input receiver.
The input receiver comprises the amplifier of any of the above embodiments.
The input receiver of the present embodiment includes the amplifier described above, and the amplifier maintains the stability of the overall tail current by generating and adjusting the second tail current, thereby reducing or eliminating the influence of the temperature of the first transistor 100 on the tail current, stabilizing the operating state of the amplifier circuit at the desired performance, reducing or eliminating the variation of the output of the input receiver with temperature, and stabilizing the operating state of the input receiver at the desired performance without being influenced by the temperature when the amplifier is stably operated.
A fourth aspect of the present embodiments provides an input receiver. Referring to fig. 4, the input receiver includes two stages of output buffers, each of which is formed by connecting two different amplifiers in the above embodiments, wherein the first amplification output terminal 350 is connected to the gate of the fifth transistor 410, and the second amplification output terminal 360 is connected to the gate of the sixth transistor 420.
Further, the amplifier also includes a bias transistor 500.
One end of the bias transistor 500 is connected to the source of the third transistor 330, the source of the fourth transistor 340, and the drain of the second transistor 210, respectively, the other end of the bias transistor 500 is connected to one end of the first transistor 100, and the gate of the bias transistor 500 is connected to a bias voltage.
In the input receiver of the embodiment, a small input signal is amplified into a rail-to-rail full-swing signal through the two-stage amplifier, so that an internal circuit normally works, the working state of the amplifier circuit is stabilized at a required performance, and the performance of the input receiver is not influenced by temperature.
A fifth aspect of the present embodiment provides a chip. The chip includes the input receiver in the above embodiments.
The performance of the input receiver in the chip of the embodiment is not affected by temperature, so that the performance of the chip is improved.
While the invention has been described with reference to specific embodiments, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
In the description of the present invention, it is to be understood that the terms "central," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the invention and to simplify the description, and are not intended to indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and are not to be considered limiting of the invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; the connection can be mechanical connection, electrical connection or communication; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly above and obliquely above the second feature, or simply meaning that the first feature is at a lesser level than the second feature.
The above disclosure provides many different embodiments, or examples, for implementing different features of the invention. The components and arrangements of the specific examples are described above to simplify the present disclosure. Of course, they are merely examples and are not intended to limit the present invention. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, the present invention provides examples of various specific processes and materials, but one of ordinary skill in the art may recognize applications of other processes and/or uses of other materials.
Claims (10)
1. An amplifier, comprising:
the grid electrode of the first transistor is connected with bias voltage, one end of the first transistor is connected with the source electrode of the input geminate transistor, the other end of the first transistor is grounded, and the first transistor is used for generating first tail current;
one end of the second transistor is connected between the first transistor and a source electrode connecting wire of the input geminate transistor, the other end of the second transistor is grounded, and the second transistor is used for generating a second tail current;
and the temperature control unit is connected with the grid electrode of the second transistor and used for adjusting the voltage connected to the grid electrode of the second transistor according to the temperature of the first transistor detected by the temperature sensor so as to keep the sum of the first tail current and the second tail current at a constant value.
2. The amplifier of claim 1, further comprising a differential cell, the differential cell comprising:
one end of the first resistor is connected with a power supply voltage;
one end of the second resistor is connected with a power supply voltage;
the drain electrode of the third transistor is connected with the other end of the first resistor, and the grid electrode of the third transistor is connected with an input voltage;
a fourth transistor, a drain of which is connected to the other end of the second resistor, a gate of which is connected to a reference voltage, and a connection point between a source of the third transistor and a source of the fourth transistor, which is used as a source of the input pair transistor, is connected to a drain of the first transistor;
a first amplification output terminal disposed on a connection line of the first resistor and the third transistor;
and the second amplification output end is arranged on a connecting line of the second resistor and the fourth transistor.
3. The amplifier of claim 2, further comprising an operational amplification unit comprising:
a fifth transistor, a gate of which is connected to the first amplification output terminal;
a sixth transistor, a gate of which is connected to the second amplification output terminal, and a connection point between a source of the fifth transistor and a source of the sixth transistor is connected to a drain of the first transistor as a source of the input pair transistor;
a seventh transistor, a source of which is connected to a power supply voltage, and a drain of which is connected to a drain of the fifth transistor;
a sixth transistor, a source of which is connected to a power supply voltage, a drain of which is connected to a drain of the sixth transistor, a gate of which is connected to a gate of the seventh transistor, and a gate of which is shorted with the drain;
and the third amplification output end is arranged on a connecting line of the fifth transistor and the seventh transistor.
4. The amplifier according to any of claims 1-3, wherein the first transistor is an NMOS transistor, a drain of the first transistor is connected to a source of the input pair transistor, and a source of the first transistor is grounded.
5. The amplifier of claim 4, wherein the second transistor is an NMOS transistor, a drain of the second transistor is connected between a drain of the first transistor and a source connection line of the input pair transistor, and a source of the second transistor is grounded.
6. A method for amplifier tail current stabilization, comprising:
detecting a temperature of the first transistor;
when the first transistor has temperature change, the voltage connected to the grid electrode of the second transistor is adjusted according to the temperature change, so that the sum of the second tail current and the first tail current is kept at a constant value.
7. The method of claim 6, wherein the step of adjusting the voltage applied to the gate of the second transistor in response to temperature changes in the first transistor comprises:
when the temperature change causes the first tail current of the first transistor to increase, the voltage connected to the grid electrode of the second transistor is reduced so as to reduce the second tail current generated by the second transistor;
when the temperature change enables the first tail current of the first transistor to be reduced, the voltage connected to the grid electrode of the second transistor is increased, and therefore the second tail current generated by the second transistor is increased.
8. An input receiver comprising an amplifier as claimed in any one of claims 1 to 5.
9. An input receiver comprising a two-stage output buffer, said two-stage output buffer comprising said amplifier of claim 2 and said amplifier of claim 3 connected, wherein said first amplified output terminal is connected to a gate of said fifth transistor and said second amplified output terminal is connected to a gate of said sixth transistor;
the amplifier further comprises:
and a bias transistor, one end of which is connected to the source of the third transistor, the source of the fourth transistor, and the drain of the second transistor, respectively, the other end of which is connected to the drain of the first transistor, and the gate of which is connected to a bias voltage.
10. A chip, characterized in that it comprises an input receiver as claimed in claim 8 or 9.
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| CN201811330501.0A CN111181512A (en) | 2018-11-09 | 2018-11-09 | Amplifier, tail current stabilizing method, input receiver and chip |
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| CN201811330501.0A CN111181512A (en) | 2018-11-09 | 2018-11-09 | Amplifier, tail current stabilizing method, input receiver and chip |
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