Shutter control circuit for bullet time shooting
Technical Field
The invention relates to the technical field of camera shutter control, in particular to a shutter control circuit for bullet time shooting.
Background
Bullet time is a photographic technique used in movies, television advertisements, or computer games to simulate variable speed special effects such as enhanced slow shots, time-stationary, etc. This technique is widely used in the fields of film and television, advertising, creative campaigns, etc.
Bullet time was originally achieved with a series of still cameras (rather than video cameras) surrounding the object. These camera arrays are typically triggered by shutters either simultaneously or sequentially. Combining each picture taken by each camera can create a perspective rotation effect on a stationary object, or a super slow lens effect. Concerning simultaneous control and sequential control, it is difficult to satisfy simultaneous or partial simultaneous in sequence if the control is solely MCU (micro control unit) control.
The existing bullet time shooting shutter controller is generally controlled directly by a single chip microcomputer and MOS, the control effect is directly related to the processing speed of the single chip microcomputer, and the single chip microcomputer cannot achieve complete synchronization of group-crossing IO.
Disclosure of Invention
1. Technical problem to be solved
Aiming at the problems existing in the prior art, the invention aims to provide a shutter control circuit for bullet time shooting, which adopts a singlechip to add a plurality of 8-bit latches, wherein two latches are in one group, a front-stage latch mainly releases data to realize data pre-locking, a rear-stage latch mainly realizes synchronous data release at specific time to realize complete synchronization, and the singlechip is in group-crossing IO complete synchronization.
2. Technical proposal
In order to solve the problems, the invention adopts the following technical scheme.
A shutter control circuit for bullet time shooting comprises an input terminal JP1, a singlechip, a plurality of groups of latches, wiring terminals K1-K100 and an output terminal J101, wherein the singlechip comprises a main control chip, and the main control chip is externally connected with a passive crystal oscillator and a reset key and further comprises a switching power supply chip U27.
Further, the input terminal JP1 is externally connected with a direct current voltage of 5-25V, and is preferably 12V supply voltage for stability of the system, the input terminal JP1 is further connected with an input filter capacitor C9, and the input filter capacitor C9 is used for guaranteeing stability of an input power supply.
Further, the main control chip adopts STM32RBT6 type chips.
Further, the network marks EN1-EN14 on the main control pins of the main control chip are used for controlling the enabling ends of the latches, and I1-I8 are used for feeding 8-bit parallel data to the latches.
Further, each set of latches includes a front stage latch D1-D8 and a rear stage latch Q1-Q8, the front stage latch mainly releasing data for realizing data pre-locking, and the rear stage latch mainly releasing data for realizing full-synchronization when a preset shutter is triggered.
Further, the connection terminals K1-K100 are used for being connected with cameras, and network labels J1-J100 corresponding to the 100 connection terminals K1-K100 are shutter control signals of 100 cameras.
Further, the com end of the wiring terminals K1-K100 is connected with a focusing signal of the camera, the com end of the input terminal J101 is connected with a focusing input signal of the shutter controller, the com ends of the wiring terminals K1-K100 are public ends, and the com ends of the wiring terminals K1-K100 are shared with the com end of the output terminal J101.
Furthermore, the switching power supply chip U27 adopts a buck structure, adopts an internal integrated mos tube for providing current output of about 3A, and the output end of the switching power supply chip U27 is also connected with an output filter capacitor C10, the two ends of the output filter capacitor C10 are enabled to obtain 3.3V voltage through the processing of the switching power supply chip U27, and the following C11-C36 is output high-frequency filtering for being connected near the power supply of each chip and used for restraining high-frequency interference.
Further, the circuit system of the shutter control circuit comprises a focusing signal receiving circuit, a shutter signal receiving circuit, a camera focusing circuit, a shutter control circuit and a serial port implementation timing delay time setting circuit;
the focusing signal receiving circuit is used for receiving a focusing signal to wake up the camera;
the shutter signal receiving circuit is used for receiving shutter signals to lock focusing, rapidly and synchronously triggering the shutter according to set time and releasing the shutter;
The camera focusing and shutter control circuit is used for receiving a trigger signal from the singlechip to control the latch, pre-latching to release the signal, and controlling the mos to realize the focusing of the camera and the control of the shutter;
the serial port implementation timing delay time setting circuit is used for the singlechip to communicate data with the computer through serial port ttl signals and store internal flash.
3. Advantageous effects
Compared with the prior art, the invention has the advantages that:
the existing bullet time shooting shutter controller is generally controlled directly by a single chip microcomputer and MOS, the control effect is directly related to the processing speed of the single chip microcomputer, and the single chip microcomputer cannot achieve complete synchronization of group-crossing IO. The invention aims to solve the problems of quick control and complete synchronization.
The shutter control circuit for bullet time shooting adopts the singlechip to add a plurality of 8-bit latches, the two latches are in one group, the front-stage latch mainly releases data to realize data pre-locking, and the rear-stage latch mainly realizes synchronous data release at specific time to realize complete synchronization, so that the singlechip group-crossing IO complete synchronization is realized, and the singlechip group-crossing IO complete synchronization is realized.
Drawings
FIG. 1 is a circuit diagram of a single chip microcomputer in the invention;
fig. 2 is a circuit diagram of a single chip microcomputer 101 according to the present invention;
FIG. 3 is a circuit diagram of a latch according to the present invention;
FIG. 4 is a circuit diagram of terminals K1-K100 according to the present invention;
fig. 5 is a circuit diagram of a power chip according to the present invention.
Detailed Description
The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, but not all embodiments, based on the embodiments of the present invention, and all other embodiments obtained by those skilled in the art without making any inventive effort are within the scope of the present invention.
In the description of the present invention, it should be noted that the positional or positional relationship indicated by the terms such as "upper", "lower", "inner", "outer", "top/bottom", etc. are based on the positional or positional relationship shown in the drawings, are merely for convenience of describing the present invention and simplifying the description, and do not indicate or imply that the apparatus or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, unless explicitly specified and limited otherwise, the terms "mounted," "configured to," "engaged with," "connected to," and the like are to be construed broadly, and include, for example, "connected to," whether fixedly connected to, detachably connected to, or integrally connected to, mechanically connected to, electrically connected to, directly connected to, indirectly connected to, and in communication with each other via an intermediate medium. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.
Example 1:
Referring to fig. 1-5, a shutter control circuit for shooting bullet time, in which JP1 is an input terminal, which can be externally connected with a direct-current voltage of 5-25V, for the stability of the system, a 12V supply voltage is generally selected, C9 is an input filter capacitor, so as to ensure the stability of the input power, a buck structure is adopted by a switching power supply chip U27, a mos tube is integrated inside, which can provide a current output of about 3A, the two ends of a capacitor C10 are subjected to processing of U27 to obtain a voltage of 3.3V, the function of C10 is an output filter, and the following C11-C36 are an output high-frequency filter for being connected near the power supply of each chip so as to inhibit high-frequency interference; STM1 is a master control chip, STM32RBT6 of an meaning semiconductor used by the master control chip is externally connected with an 8M passive crystal oscillator and a key as reset, so that a singlechip minimum system circuit is formed, network marks EN1-EN14 on the master control pin are used for controlling enabling ends of latches, I1-I8 are used for providing 8-bit parallel data to the latches, wiring terminals K1-K100 are used for connecting with a camera, a total of 100 Canon single-lens reflex cameras are connected, network marks J1-J100 corresponding to the 100 terminals K1-K100 are shutter control signals of 100 cameras, COM ends of the 100 terminals are common and are shared with COM ends of an output terminal J101, the COM ends of the just-mentioned input terminal J101 are focusing input signals of a shutter controller, that is to say, focusing of the shutter controller directly controls the camera;
The focusing signal is directly connected to a focusing trigger port of the camera, the camera focusing is directly triggered by the detected focusing signal, once the shutter signal is pressed down, the singlechip K101 detects low level, the first step of triggering is started to be executed by locking focusing, the trigger port EN14 is directly released, the actual circuit needs to trigger that the displayed signal data are displayed on Q1-Q8 of U1 before triggering, the enabled LE (network EN 14) of U2 is released after triggering and is immediately Ma Suocun, LE is an output end state change enabled end, when LE is low level, the output end Q always keeps the last stored signal (input from the D end), when LE is high level, Q is immediately changed along with the state of D, and the state of D is latched. And after the LE latch is locked, directly filling the next group of data, and releasing the latch again until the set time is up until the complete triggering is finished. And UART_TX and UART_RX of the singlechip are communicated with the computer end through serial ports to time delay data.
The above description is only of the preferred embodiments of the present invention, but the protection scope of the present invention is not limited thereto, any person skilled in the art should be able to make equivalent substitutions or modifications according to the technical solution and the modified concept thereof within the scope of the present invention.