CN111159933B - Modeling method for gate-surrounding capacitance of source-drain epitaxial field effect transistor - Google Patents
Modeling method for gate-surrounding capacitance of source-drain epitaxial field effect transistor Download PDFInfo
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Abstract
The invention discloses a modeling method of a gate-surrounding capacitor of a source-drain epitaxial field effect transistor, which divides the gate-surrounding capacitor of a source-drain epitaxial device into a grid and a plug coupling capacitor C CO Coupling capacitor C of grid electrode and bottom interconnection metal M1 PM And a gate-source-drain coupling capacitor C GSD And three types, four different test structures are designed for extracting the parasitic capacitance of the three types of gate electrodes. The grid electrode and the plug are coupled with the capacitor C step by step through the statistical analysis of the test values of the four test structures CO Coupling capacitor C of grid electrode and bottom interconnection metal M1 PM And a gate-source-drain coupling capacitor C GSD And (5) separating. The gate-surrounding capacitance indirect value obtained by analyzing and processing the test structure test value can be restored by a three-dimensional field simulator to obtain the true value of the gate-surrounding capacitance. And aiming at different device sizes, de-embedding and analyzing the grid surrounding capacitance, writing the obtained grid surrounding capacitance into an ITF file in a two-dimensional lookup table, and generating a layout parasitic library nxtgrd file by using an LPE tool StarRC to realize the accurate matching of the layout parasitic library file and the grid surrounding capacitance.
Description
Technical Field
The invention belongs to parasitic capacitance modeling in a Complementary Metal Oxide Semiconductor (CMOS) ultra-large integrated circuit (VLSI), and particularly relates to a gate-surrounding capacitance modeling method adopting an epitaxial source-drain field effect transistor.
Background
Along with the continuous forward progress of the semiconductor manufacturing process, the delay time of the field effect transistor is continuously reduced, however, the delay time of the interconnection capacitance, interconnection resistance, gate parasitic capacitance and parasitic resistance on the gate level circuit except the intrinsic delay of the transistor can be gradually close to the intrinsic delay of the transistor, and even be higher than the intrinsic delay of the device to a certain extent. The smaller metal line widths will lead to ever increasing parasitic resistance, the more compact metal line spacing will cause the parasitic capacitance to grow in a inversely proportional trend, and the more closely related gate-to-gate parasitic resistance and capacitance with transistor switches will severely exacerbate delay degradation. The occurrence of interconnect and gate periphery problems necessitates that the integrated circuit designer consider the effects of interconnect and gate periphery parasitics on circuit timing and functionality as early as possible in the chip design process, and the accuracy and efficiency of the layout parasitics parameter extraction tool (LPE: layout Parasitic Extraction) is indispensable for integrated circuit design and verification.
The modeling of the interconnection capacitance and the resistor of the metal post-passage in the current industry is relatively reliable, and the main problem is that the modeling method of the interconnection parasitic resistor and the interconnection parasitic resistor is repeated and improved on a new process node along with the continuous advancement of the manufacturing process. The modeling of the parasitic resistance of the gate periphery is carried out according to the resistivity of different gate linewidths, and the change rule is more linear. For the parasitic capacitance around the gate, with the aggravation of the short channel effect and the series resistance of the Source and the Drain of the device, the techniques of stress silicon engineering (LOD effect), epitaxial Source and Drain (Epi-Source/Drain), fully-depleted silicon on insulator (FD-SOI), fin field effect transistor (FinFET) and the like are applied to ensure the good electrical characteristics of the device. However, the above technology changes the structure of the device, so that the gate structure of the device is more and more complex, the LPE tools such as Calibre, starRC are difficult to accurately predict the gate parasitic capacitance when the new technology is applied, the calculation time of the three-dimensional finite element Field Solver (3D Field Solver) is too long, the method is difficult to be applied to hundreds of millions of gate-level integrated circuits, the existing modeling method is seriously dependent on the finite element Field Solver, no direct wafer test data exists, and a certain risk exists in the modeling method. In order to ensure that a very large scale integrated circuit (Tape-out) realizes functional integrity, a gate-surrounding parasitic capacitance test level modeling method aiming at various advanced silicon technologies, particularly a widely applied source-drain epitaxial technology, is urgently required to be developed.
Disclosure of Invention
The invention aims to provide a method for coupling a grid electrode and a plug to a capacitor (C C0 ) Gate-to-bottom interconnect metal M1 coupling capacitance (C PM ) Grid and source drain coupling capacitance (C) GSD ) And gate-to-active region fringe capacitance (C F ) The de-embedded test structures (testkeys) were individually designed and assisted with a three-dimensional finite element field solver based on a typical interconnect process format (ITF: interconnection Technology Format), on the basis of the existing LPE tool, accurately modeling the gate parasitic capacitance of the source-drain epitaxial field effect transistor.
The specific technical scheme for realizing the purpose of the invention is as follows;
a modeling method of gate-surrounding capacitance of a source-drain epitaxial field effect transistor comprises the following steps: the method comprises the following steps of obtaining capacitance values of the four types of device gate-surrounding capacitance test structures through testing, obtaining structural parameters of the four types of test structure gate-surrounding areas through transmission electron microscope slicing, and establishing an ITF file capable of representing the gate-surrounding parasitic capacitance of the source-drain epitaxial field effect transistor, wherein the four types of device gate-surrounding capacitance test structures are a common source-drain epitaxial field effect transistor structure, a field effect transistor de-embedding structure with a field oxide layer used for replacing an active area, a field effect transistor de-embedding structure with plugs on one side of a source electrode or a drain electrode and metal interconnection removed, and a field effect transistor de-embedding structure with plugs on one side of the source electrode or the drain electrode removed only, and the specific implementation method comprises the following steps:
step one: the method comprises the following steps of carrying out statistics and analysis on test values obtained by flow sheet tests of four types of test structures, namely a common source-drain epitaxial field effect transistor structure, a field effect transistor de-embedding structure which adopts a field oxide layer to replace an active region, a field effect transistor de-embedding structure which removes plugs at one side of a source electrode or a drain electrode and metal interconnection, and a field effect transistor de-embedding structure which only removes plugs at one side of the source electrode or the drain electrode, wherein the calculation formula is as follows:
C measure-4 -C measure-3 ＝C PM-1
C measure-2 ＝2×C PM +2×C CO-1
C measure-1 -C measure-3 ＝C PM +C CO +C GSD -C GSD-1 ；
wherein C is measure-1 Is the capacitance test value of the common source-drain epitaxial field effect transistor structure, C measure-2 The capacitance test value of the field effect transistor de-embedding structure adopting the field oxide layer to replace the active area is C measure-3 Is the capacitance test value of the field effect transistor de-embedded structure with the plug at the side of the source electrode or the drain electrode removed and the metal interconnection, C measure-4 Is the capacitance test value of the field effect transistor de-embedded structure with only the source electrode or the drain electrode side plug removed, C CO Is the coupling capacitance between the gate and the plug in the common transistor structure, C CO-1 The coupling capacitance between the grid electrode and the plug of the de-embedded structure of the active area is replaced by a field oxide layer, C PM Is the coupling capacitance between the gate and the interconnect metal in a common transistor structure, C PM-1 Is the coupling capacitance between the gate and the interconnect metal in the absence of a source or drain side plug, C GSD Is the coupling capacitance between the gate and the epitaxial source and drain in a common transistor structure, C GSD-1 Is the coupling capacitance between the gate and the epitaxial source and drain when the source or drain side plug is missing;
step two: using three-dimensional finite element field solver to construct plug and gold for removing source electrode or drain electrode side according to transmission electron microscope slice structure parametersThe coupling capacitance C between the grid electrode and the interconnection metal when the source electrode or the drain electrode side plug is missing is obtained by simulation calculation PM-1 Is a simulation value C of (2) PM-1-Solver The difference C between the capacitance test value of the field effect transistor de-embedded structure obtained in the step one and with the plugs on the source electrode side or the drain electrode side and the metal interconnection removed measure-4 -C measure-3 Simulation value C of coupling capacitance between gate and interconnect metal in the absence of source or drain side plug PM-1-Solver In contrast, if the error is less than 5%, the coupling capacitance C between the gate and the interconnect metal in a conventional transistor structure is built using the current structural parameters PM The coupling capacitance C between the grid electrode and the interconnection metal in the common transistor structure is calculated by a three-dimensional field simulator PM Is a value of (2); if the error is greater than or equal to 5%, modifying the structural parameters in the three-dimensional field simulator until the coupling capacitance C between the gate and the interconnect metal when the source or drain side plug is missing PM-1 After the error is satisfied, the coupling capacitance C between the grid electrode and the interconnection metal in the common transistor structure is calculated PM ；
Step three: constructing a field effect transistor de-embedding structure using a field oxide layer to replace an active area according to a transmission electron microscope slice structure parameter by using a three-dimensional finite element field solver, and coupling capacitance C between a simulation value of the field effect transistor de-embedding structure using the field oxide layer to replace the active area and a grid electrode and interconnection metal in a common transistor structure PM Subtracting to obtain coupling capacitance C between grid electrode and plug of de-embedded structure using field oxide layer to replace active region CO-1 Is a simulation value C of (2) CO-1-Solver C, the capacitance test value of the field effect transistor de-embedding structure obtained in the step one, wherein the field oxide layer is adopted to replace an active area measure-2 And the coupling capacitance C between the grid electrode and the interconnection metal in the common transistor structure obtained in the second step PM Difference of doing C measure-2 -C PM Double-sized 2 XC of coupling capacitance simulation value between gate and plug of de-embedded structure using field oxide layer to replace active region CO-1-Solver In contrast, if the error is less than 5%, the coupling capacitance C between the gate and the plug in a normal transistor structure is constructed using the current structural parameters CO The coupling capacitance C between the grid electrode and the plug in the common transistor structure is calculated by a three-dimensional field simulator CO Is a value of (2); if the error is greater than or equal to 5%, modifying the structural parameters in the three-dimensional field simulator until the coupling capacitance C between the gate and the plug of the de-embedded structure of the active region is replaced by a field oxide layer CO-1 After the error is satisfied, the coupling capacitance C between the grid electrode and the plug in the common transistor structure is calculated CO ；
Step four: constructing a common source-drain epitaxial field effect transistor structure and a field effect transistor de-embedding structure with plugs and metal interconnections on one side of a source electrode or a drain electrode removed according to the slice structure parameters of a transmission electron microscope by using a three-dimensional finite element field solver, performing simulation calculation on the two structures, and subtracting a coupling capacitance C between a grid electrode and interconnection metal in the common transistor structure obtained in the second step PM And the coupling capacitance C between the grid electrode and the plug in the common transistor structure obtained in the step three CO The coupling capacitance C between the grid electrode and the epitaxial source electrode and the epitaxial drain electrode in the common transistor structure can be obtained GSD And coupling capacitance C between the gate and the epitaxial source and drain when the source or drain side plug is missing GSD-1 Is a simulation value C of (2) GSD-Solver And C GSD-1-Solver Capacitance test value C of common source-drain epitaxial field effect transistor structure measure-1 Capacitance test value C of field effect transistor de-embedded structure with source electrode or drain electrode side plug removed and metal interconnection removed in sequence measure-3 Coupling capacitance C between gate and interconnect metal in a common transistor structure PM Coupling capacitance C between gate and plug in a normal transistor structure CO Calculating the obtained C measure-1 -C measure-3 -C PM -C CO Coupling capacitance C between gate and epitaxial source and drain in common transistor structure GSD And coupling capacitance C between the gate and the epitaxial source and drain when the source or drain side plug is missing GSD-1 Difference C of simulation values of (2) GSD-Solver -C GSD-1-Solver In contrast, if the error is less than 5%, the coupling capacitance C between the grid electrode and the epitaxial source electrode and drain electrode in the common transistor structure calculated by the three-dimensional field simulator is obtained GSD The method comprises the steps of carrying out a first treatment on the surface of the If the error is greater than or equal to 5%, the coupling capacitance C between the gate and the epitaxial source and drain in the common transistor structure in the three-dimensional field simulator is modified simultaneously GSD And coupling capacitance C between the gate and the epitaxial source and drain when the source or drain side plug is missing GSD-1 Up to C GSD-Solver -C GSD-1-Solver After the error is satisfied, the coupling capacitance C between the grid electrode and the epitaxial source electrode and the epitaxial drain electrode in the common transistor structure obtained by the three-dimensional field solver is obtained GSD ；
Step five: coupling capacitance C between grid electrode and interconnection metal in common transistor structure obtained in step two PM Coupling capacitance C between grid electrode and plug in common transistor structure obtained in step three CO And the coupling capacitance C between the grid electrode and the epitaxial source electrode and the epitaxial drain electrode in the common transistor structure obtained in the step four GSD And (3) according to different device width-to-length ratios, arranging the device width-to-length ratios into a two-dimensional lookup table, writing the ITF file, and generating a layout parasitic library file (nxtgrd file) by using an LPE tool StarRC, wherein the layout parasitic gate-to-surrounding capacitor can be extracted.
By the aid of the three-dimensional field solver, each part forming the gate-surrounding capacitor can be obtained through the mathematical relation between the sizes of the gate-surrounding capacitors of the test structure, and the gate-surrounding capacitor of the source-drain epitaxial field effect transistor can be accurately modeled from the interconnection metal M1 to the epitaxial source electrode and the epitaxial drain electrode from top to bottom, so that the aim of accurately matching the capacitance value of the test structure with the parasitic gate-surrounding capacitance value of the layout extracted by the StarRC is achieved. The test proves that the error of the gate-surrounding capacitance test value and the territory parasitic gate-surrounding capacitance extracted by StarRC can be reduced to be within 1 percent.
Drawings
FIG. 1 is a cross-sectional view of a first test structure of the present invention;
FIG. 2 is a layout of a first test structure of the present invention;
FIG. 3 is a cross-sectional view of a second test structure of the present invention;
FIG. 4 is a layout of a test structure II of the present invention;
FIG. 5 is a cross-sectional view of a third test structure of the present invention;
FIG. 6 is a layout of a test structure III of the present invention;
FIG. 7 is a cross-sectional view of a fourth test structure of the present invention;
fig. 8 is a layout of a fourth test structure of the present invention.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings and examples.
The field effect transistor structure adopting the source-drain epitaxy technology is not completely consistent, but the upper edge of a source electrode and the lower edge of a grid electrode are not positioned on the same horizontal line due to the structure of the source-drain epitaxy, and the parasitic structure of the grid electrode is basically the same. In fig. 1, the gate parasitic capacitance mainly includes a gate, a plug coupling capacitance, a gate-bottom interconnection metal coupling capacitance, and a gate-source-drain coupling capacitance, but the test structure shown in fig. 1 includes a gate and an active region fringe capacitance which are difficult to remove during a test, and a field effect transistor is turned on when a voltage bias applied by the gate is raised, so that the gate and the active region fringe capacitance is increased, and the gate parasitic capacitance can be submerged by the magnitude of the fringe capacitance. For the first test structure (shown in figure 1), the layout shown in figure 2 is used for conducting the flow sheet test, and the capacitance test value of the structure under any voltage bias condition is 2 x (C CO +C PM +C GSD +C f )。
For the second test structure (fig. 3), the layout of fig. 4 is used for carrying out the flow sheet test, the sectional view of the test structure is shown in fig. 3, a is a grid electrode, b is a tungsten plug (Contact), C is a grid electrode through hole (Via), d is bottom metal M1, and the capacitance test value of the structure under any voltage bias condition is 2× (C) CO-1 +C PM )。
For a test structure III (shown in FIG. 5), the layout shown in FIG. 6 is used for carrying out flow sheet test, the sectional view of the test structure is shown in FIG. 5, a is a grid electrode, b is a tungsten plug (Contact), C is a grid electrode through hole (Via), d is bottom metal M1 and e is an active region, and the capacitance test value of the structure under any voltage bias condition is C CO +C CO-1 +C PM +C GSD +C GSD-1 +2×C f 。
For the fourth test structure (fig. 7), the layout of fig. 8 is used for carrying out the flow sheet test, the sectional view of the test structure is shown in fig. 7, a is a grid electrode, b is a tungsten plug (Contact), C is a grid electrode through hole (Via), d is a bottom metal M1, e is an active region, and the capacitance test value of the structure under any voltage bias condition is C CO +C PM +C PM-1 +C GSD +C GSD-1 +2×C f 。
The test values obtained by testing the four types of test structures are counted and calculated, and are analyzed as follows:
C measure-4 -C measure-3 ＝C PM-1
C measure-2 ＝2×C PM +2×C CO-1
C measure-1 -C measure-3 ＝C PM +C CO +C GSD -C GSD-1
coupling capacitor C of interconnection metal M1 between grid electrode and bottom layer PM Referring to the electron transmission microscope slice structure and the structural parameter values, the true values are restored by means of a three-dimensional field solver: firstly, restoring a test structure III and a test structure IV by using a three-dimensional field solver, and performing three-dimensional finite element analysis to obtain a simulation value C simualtion-3 And C simulation-4 The two are subtracted to obtain C calculated by a field solver PM-1-Solver The method comprises the steps of carrying out a first treatment on the surface of the Secondly, the first step of the method comprises the steps of,c is C PM-1-Solver And (C) measure-4 -C measure-3 ) If the error is less than 5%, the next operation is carried out, if the error is greater than or equal to 5%, the structural parameters of the test structure are modified in the last step, and the solution is carried out again until the error is less than 5%; finally, C is restored on the premise of the currently used structural parameters PM The structure presented in the actual preparation, thus obtaining C PM Is of a size of (a) and (b).
Coupling capacitor C between gate and plug C0 Referring to the electron transmission microscope slice structure and the structural parameter values, the true values are restored by means of a three-dimensional field solver: firstly, restoring a test structure II by using a three-dimensional field solver, and performing three-dimensional finite element analysis to obtain a simulation value C simualtion-2 C is carried out by simualtion-2 And C PM The true values are subtracted to obtain C calculated by a field solver CO-1-Solver The method comprises the steps of carrying out a first treatment on the surface of the Next, C is CO-1-Solver And (C) measure-2 -C PM ) Comparing the values of/2, if the error is less than 5%, performing the next operation, if the error is greater than or equal to 5%, returning to the previous step for modifying the structural parameters of the test structure, and solving again until the error is less than 5%; finally, C is restored on the premise of the currently used structural parameters C0 The structure presented in the actual preparation, thus obtaining C C0 Is of a size of (a) and (b).
To grid and source drain coupling capacitor C GSD Referring to the electron transmission microscope slice structure and the structural parameter values, the true values are restored by means of a three-dimensional field solver: firstly, restoring the first test structure and the third test structure by using a three-dimensional field solver, and performing three-dimensional finite element analysis to obtain a simulation value C simualtion-1 And C simualtion-3 C is carried out by simualtion-1 And C simualtion-3 And C PM And C C0 The true values are subtracted and C is calculated by using a field solver according to the same structural parameters GSD-Solver -C GSD-1-Solver Is of a size of (2); next, C is GSD-Solver -C GSD-1-Solver And (C) measure-1 -C measure-3 -C PM -C CO ) The values of (2) are compared, if the error is less than 5%, thenCarrying out the next operation, if the error is greater than or equal to 5%, returning to the previous step to modify the structural parameters of the test structure, and solving again until the error is less than 5%; finally, directly obtaining the value C GSD-Solver Thereby obtaining C GSD Is of a size of (a) and (b).
Under the condition of different channel lengths and channel widths of the field effect transistor, the method is adopted to respectively obtain the coupling capacitance C of the grid electrode and the plug C0 Coupling capacitor C of grid electrode and bottom interconnection metal M1 PM And a gate-source-drain coupling capacitor C GSD And C is selected according to different channel lengths and channel widths C0 、C PM And C GSD Converting into a two-dimensional lookup table format, writing in an ITF file, and generating a layout parasitic library file (nxtgrd file) by using an existing LPE tool StarRC. And using the StarRC and the circuit layout, the size of the parasitic capacitance around the grid in the circuit layout can be extracted, and a standard delay exchange file (spaf file) is generated, so that the time sequence delay of the circuit is evaluated.
Claims (1)
1. The modeling method of the gate-surrounding capacitance of the source-drain epitaxial field effect transistor is characterized by comprising the following steps of:
step one: the method comprises the following steps of carrying out statistics and analysis on test values obtained by flow sheet tests of four types of test structures, namely a common source-drain epitaxial field effect transistor structure, a field effect transistor de-embedding structure which adopts a field oxide layer to replace an active region, a field effect transistor de-embedding structure which removes plugs at one side of a source electrode or a drain electrode and metal interconnection, and a field effect transistor de-embedding structure which only removes plugs at one side of the source electrode or the drain electrode, wherein the calculation formula is as follows:
C measure-4 -C measure-3 ＝C PM-1
C measure-2 ＝2×C PM +2×C CO-1
C measure-1 -C measure-3 ＝C PM +C CO +C GSD -C GSD-1 ；
wherein C is measure-1 Is the capacitance test value of the common source-drain epitaxial field effect transistor structure, C measure-2 The capacitance test value of the field effect transistor de-embedding structure adopting the field oxide layer to replace the active area is C measure-3 Is the capacitance test value of the field effect transistor de-embedded structure with the plug at the side of the source electrode or the drain electrode removed and the metal interconnection, C measure-4 Is the capacitance test value of the field effect transistor de-embedded structure with only the source electrode or the drain electrode side plug removed, C CO Is the coupling capacitance between the gate and the plug in the common transistor structure, C CO-1 The coupling capacitance between the grid electrode and the plug of the de-embedded structure of the active area is replaced by a field oxide layer, C PM Is the coupling capacitance between the gate and the interconnect metal in a common transistor structure, C PM-1 Is the coupling capacitance between the gate and the interconnect metal in the absence of a source or drain side plug, C GSD Is the coupling capacitance between the gate and the epitaxial source and drain in a common transistor structure, C GSD-1 Is the coupling capacitance between the gate and the epitaxial source and drain when the source or drain side plug is missing;
step two: constructing a field effect transistor de-embedding structure for removing a plug at one side of a source electrode or a drain electrode and metal interconnection and a field effect transistor de-embedding structure for removing only the plug at one side of the source electrode or the drain electrode according to the slice structure parameters of a transmission electron microscope by using a three-dimensional finite element field solver, and obtaining the coupling capacitance C between a grid electrode and interconnection metal when the plug at one side of the source electrode or the drain electrode is missing through simulation calculation PM-1 Is a simulation value C of (2) PM-1-Solver The difference C between the capacitance test value of the field effect transistor de-embedded structure obtained in the step one and with the plugs on the source electrode side or the drain electrode side and the metal interconnection removed measure-4 -C measure-3 Simulation value C of coupling capacitance between gate and interconnect metal in the absence of source or drain side plug PM-1-Solver In contrast, if the error is less than 5%, the coupling capacitance C between the gate and the interconnect metal in a conventional transistor structure is built using the current structural parameters PM The three-dimensional field simulator calculates the space between the grid electrode and the interconnection metal in the common transistor structureCoupling capacitance C of (2) PM Is a value of (2); if the error is greater than or equal to 5%, modifying the structural parameters in the three-dimensional field simulator until the coupling capacitance C between the gate and the interconnect metal when the source or drain side plug is missing PM-1 After the error is satisfied, the coupling capacitance C between the grid electrode and the interconnection metal in the common transistor structure is calculated PM ；
Step three: constructing a field effect transistor de-embedding structure using a field oxide layer to replace an active area according to a transmission electron microscope slice structure parameter by using a three-dimensional finite element field solver, and coupling capacitance C between a simulation value of the field effect transistor de-embedding structure using the field oxide layer to replace the active area and a grid electrode and interconnection metal in a common transistor structure PM Subtracting to obtain coupling capacitance C between grid electrode and plug of de-embedded structure using field oxide layer to replace active region CO-1 Is a simulation value C of (2) CO-1-Solver C, the capacitance test value of the field effect transistor de-embedding structure obtained in the step one, wherein the field oxide layer is adopted to replace an active area measure-2 And the coupling capacitance C between the grid electrode and the interconnection metal in the common transistor structure obtained in the second step PM Difference of doing C measure-2 -C PM Double-sized 2 XC of coupling capacitance simulation value between gate and plug of de-embedded structure using field oxide layer to replace active region CO-1-Solver In contrast, if the error is less than 5%, the coupling capacitance C between the gate and the plug in a normal transistor structure is constructed using the current structural parameters CO The coupling capacitance C between the grid electrode and the plug in the common transistor structure is calculated by a three-dimensional field simulator CO Is a value of (2); if the error is greater than or equal to 5%, modifying the structural parameters in the three-dimensional field simulator until the coupling capacitance C between the gate and the plug of the de-embedded structure of the active region is replaced by a field oxide layer CO-1 After the error is satisfied, the coupling capacitance C between the grid electrode and the plug in the common transistor structure is calculated CO ；
Step four: constructing a common source-drain epitaxial field according to the slice structural parameters of a transmission electron microscope by using a three-dimensional finite element field solverThe simulation calculation is carried out on the two structures, and the coupling capacitance C between the grid electrode and the interconnection metal in the common transistor structure obtained in the second step is subtracted PM And the coupling capacitance C between the grid electrode and the plug in the common transistor structure obtained in the step three CO Obtaining the coupling capacitance C between the grid electrode and the epitaxial source electrode and the epitaxial drain electrode in the common transistor structure GSD And coupling capacitance C between the gate and the epitaxial source and drain when the source or drain side plug is missing GSD-1 Is a simulation value C of (2) GSD-Solver And C GSD-1-Solver Capacitance test value C of common source-drain epitaxial field effect transistor structure measure-1 Capacitance test value C of field effect transistor de-embedded structure with source electrode or drain electrode side plug removed and metal interconnection removed in sequence measure-3 Coupling capacitance C between gate and interconnect metal in a common transistor structure PM Coupling capacitance C between gate and plug in a normal transistor structure CO Calculating the obtained C measure-1 -C measure-3 -C PM -C CO Coupling capacitance C between gate and epitaxial source and drain in common transistor structure GSD And coupling capacitance C between the gate and the epitaxial source and drain when the source or drain side plug is missing GSD-1 Difference C of simulation values of (2) GSD-Solver -C GSD-1-Solver In contrast, if the error is less than 5%, the coupling capacitance C between the grid electrode and the epitaxial source electrode and drain electrode in the common transistor structure calculated by the three-dimensional field simulator is obtained GSD The method comprises the steps of carrying out a first treatment on the surface of the If the error is greater than or equal to 5%, the coupling capacitance C between the gate and the epitaxial source and drain in the common transistor structure in the three-dimensional field simulator is modified simultaneously GSD And coupling capacitance C between the gate and the epitaxial source and drain when the source or drain side plug is missing GSD-1 Up to C GSD-Solver -C GSD-1-Solver After the error is satisfied, acquiring a grid electrode in a common transistor structure obtained by a three-dimensional field solverCoupling capacitance C with epitaxial source and drain GSD ；
Step five: coupling capacitance C between grid electrode and interconnection metal in common transistor structure obtained in step two PM Coupling capacitance C between grid electrode and plug in common transistor structure obtained in step three CO And the coupling capacitance C between the grid electrode and the epitaxial source electrode and the epitaxial drain electrode in the common transistor structure obtained in the step four GSD And (3) according to different device width-to-length ratios, arranging the device width-to-length ratios into a two-dimensional lookup table, writing the ITF file, and then using an LPE tool StarRC to generate a layout parasitic library file, namely an nxtgrd file, for extracting the layout parasitic gate-to-surrounding capacitance.
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| JP2003101015A (en) * | 2001-09-27 | 2003-04-04 | Takehide Shirato | Mis field-effect transistor and manufacturing method therefor |
| JP2011082223A (en) * | 2009-10-02 | 2011-04-21 | Renesas Electronics Corp | Semiconductor integrated circuit device |
| WO2018032713A1 (en) * | 2016-08-16 | 2018-02-22 | 南京展芯通讯科技有限公司 | Field effect transistor small-signal equivalent circuit model having channel advanced parasitic element |
| CN110416104A (en) * | 2019-07-25 | 2019-11-05 | 华东师范大学 | A kind of grid of source and drain lifting FDSOI device enclose parasitic interconnection capacitance extracting method |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003101015A (en) * | 2001-09-27 | 2003-04-04 | Takehide Shirato | Mis field-effect transistor and manufacturing method therefor |
| JP2011082223A (en) * | 2009-10-02 | 2011-04-21 | Renesas Electronics Corp | Semiconductor integrated circuit device |
| WO2018032713A1 (en) * | 2016-08-16 | 2018-02-22 | 南京展芯通讯科技有限公司 | Field effect transistor small-signal equivalent circuit model having channel advanced parasitic element |
| CN110416104A (en) * | 2019-07-25 | 2019-11-05 | 华东师范大学 | A kind of grid of source and drain lifting FDSOI device enclose parasitic interconnection capacitance extracting method |
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