CN111159628B - Hardware SAT solver for multi-thread parallel execution - Google Patents
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Abstract
The invention provides a hardware SAT solver for multi-thread parallel execution, which comprises a first register module, a first evaluation module group, a buffer module group, a counter module, a argument overturn module, a probability mapping table, an FIFO tree group, a second register module group, a second evaluation module and a third register module. According to the hardware SAT solver with the multithreading parallel execution, all data are stored in the on-chip memory of the FPGA, so that time overhead caused by reading of off-chip data is avoided, meanwhile, a multithreading strategy is utilized, different threads interact the same address mapping table and the clause mapping table, resource overhead of the on-chip memory is greatly reduced, total turnover per second is increased in a multiple mode due to the fact that the multithreading strategy is used, a solution of the problem can be found in a specified time more possibly, and the SAT problem in a relatively large scale can be solved more efficiently and conveniently.
Description
Technical Field
The invention belongs to the technical field of computers, particularly relates to an SAT solver, and particularly relates to a hardware SAT solver for multi-thread parallel execution.
Background
In the SAT problem (boolean satisfiability problem), a finite set of arguments X is given as { X } 1 ,x 2 ,…,x n }，x n Can be assigned a true (1) or a false (0), the letter l i Is argument x i Or negation thereof
And is provided with
Clause C is formed by extracting words (meaning "OR"), and is a conjunctive normal form CNF (conditioned normal form)
Formed by combining a plurality of clauses, e.g.
I.e. a CNF formula consisting of 5 arguments and 4 clauses. If any character in the clause is evaluated as true, the clause is true or satisfied; if all the characters in the clause are assigned with false values at the same time, the clause is called false by assigning the values, or the clause is not satisfied by assigning the values, and the formula
Is satisfied if and only if all clauses are satisfied at the same time. The SAT problem refers to finding a set of assignments X' for all the arguments on X, X → {0,1} such that
Is true. If such an assignment exists, then
Is satisfactory; if no such assignment exists, then
Are not satisfactory.
The SAT problem was demonstrated by stevens couk (Steven Cook) in 1971 as an NP-complete problem, which means that it can be solved very quickly in polynomial time, and all other problems of the NP class can be attributed to SAT problems in polynomial time. The most straightforward, crude way to solve the SAT problem is by enumeration, i.e. trying to enter all possible assignments of arguments, however, the solution time for such an algorithm grows exponentially as the number of arguments increases.
In the past decades, algorithms for solving the SAT problem, also known as SAT solvers, have made tremendous progress. Problems that were thought to be unsolvable more than a decade ago can now be solved in a matter of seconds using advanced SAT solvers. Modern SAT solvers can integrate more advanced solution techniques, and software solvers developed by these techniques can solve even the difficult SAT problem of millions of arguments.
When the SAT solver attempts to solve a problem, it assigns initial values (denoted α and β, respectively) to the arguments, either in whole or in part. To formula
A full assignment is to assign 0 or 1 to each argument in the formula, e.g., α ═ x 1 ＝1,x 2 ＝0,x 3 ＝1,x 4 ＝1,x 5 1). In contrast, a partial assignment is an assignment to a subset of a set of formula arguments, such as β ═ x (x) 1 ＝1,x 2 0). The assignment of the formula should follow the rules of boolean logic. For example, if there are one or more words in a clause that are true (i.e., a value of 1), then the clause is satisfiable and can be deleted from the formula. If the formula is empty (i.e., there are no more clauses to satisfy), then the formula is satisfied. Conversely, if a word in a clause is false, the word may be deleted from the clause. Therefore, if a clause is empty, the clause cannot be satisfied, and the simplified formula is also not satisfied.
For a long period of time, during which SAT solvers were first widely used, single-processor systems have been dominating in computing. With the steady increase in performance of each generation of processors, researchers have generally thought how to use solution techniques for parallelized applications. However, with the progress of research, the reasons of processor capacity, memory constraints, power consumption problems, excessive utilization of instruction level parallelism, and optimization of memory delay fall into stagnation, so that the way of improving performance by only depending on a single-core processor is not obvious any more. As the processor industry has developed, the computational power of processors has no longer increased with increasing frequency, with higher computational power coming from more and more computational cores and processors.
Currently, software-based parallel SAT solvers typically employ one of the following strategies:
(1) the SAT problem is equated to a number of sub-problems containing n arguments and all sub-problems are assigned to different thread processes.
And mutually competing several different serial SAT solvers at the same time.
The first case is solved using a divide-and-conquer approach, and if any sub-problem finds a satisfiable assignment, it indicates that the original problem is satisfiable. In the second case, the next variable is selected by using the orthogonal parameters, how often to restart, learning clause database management, etc.
For a hardware solver based on a complete algorithm, the lack of sufficient fast memory is the main reason that previous work did not try a multi-threaded BCP in hardware. For SRAM based BCP accelerators, memory capacity is a limiting factor. The cost of copying the assignment of arguments (and possibly also the monitored literal list) is too large. External memory bandwidth can be easily exhausted for DRAM-based BCP accelerators, so multi-threaded systems will eventually share access to this slow memory.
Disclosure of Invention
The invention aims to solve the technical problem of providing a hardware SAT solver with multi-thread parallel execution aiming at the defects involved in the background technology, all data are stored in an on-chip memory of an FPGA, the time expense caused by reading off-chip data is avoided, simultaneously, different threads interact with the same address mapping table and clause mapping table by utilizing a multi-thread strategy, the resource expense of the on-chip memory is greatly reduced, and the total turnover per second is multiplied by using the multi-thread strategy, so that the problem solution can be found more possibly within the specified time.
In order to solve the technical problems, the invention adopts the following technical scheme:
a hardware SAT solver for multi-threaded parallel execution, comprising: the device comprises a first register module, a first evaluation module group, a buffer module group, a counter module, a argument overturning module, a probability mapping table, a FIFO tree group, a second register module group, a second evaluation module and a third register module.
The first register module is used for storing clauses corresponding to the CNF formula argument initial assignment.
And the first evaluation module group comprises a plurality of groups of parallel first evaluation modules and is used for multithread parallel storage of the clauses sent by the first register module and the clauses after argument inversion.
And the buffer module group comprises a plurality of groups of parallel buffer modules and is used for assigning the temporarily turned characters in the multithread parallel buffer.
And the counter module is used for calculating the break-value values of all the inverted variables in the buffer module group and sequencing the break-values.
And the probability mapping table is used for pre-storing break-value values corresponding to different turnover probabilities.
And the argument turning module is used for turning the clause argument according to the probability of the probability mapping table.
And the FIFO tree group comprises a plurality of groups of FIFO trees, each group of FIFO trees comprises a plurality of levels of FIFO, and the FIFO trees are used for storing sub-sentences which cannot be satisfied after being overturned by the argument overturning module in the multithread parallel buffer module group.
And the second register module group comprises a plurality of groups of parallel second register modules and is used for receiving unsatisfiable clauses from the FIFO tree group in a multithread parallel mode.
A second evaluation module, configured to randomly read a clause from the second register module group, and evaluate whether the clause is satisfiable or unsatisfiable, and if the clause is satisfiable, continue to randomly read a clause from the second register module group, and evaluate whether the clause is satisfiable or unsatisfiable; if the clause is unsatisfiable, the unsatisfiable clause is sent to a third register module.
And the third register module is used for storing the clauses which are evaluated to be unsatisfiable by the second evaluation module, searching the clauses containing the negative characters of the characters in the clauses in the first register module and sending the clauses to the first evaluation module group.
Further, the first register module includes an address mapping table and a clause mapping table, and the data of the clause corresponding to the initial assignment of the CNF formula argument is stored in the address mapping table and the clause mapping table.
Further, when unsatisfiable clauses are overturned by the argument overturning module in the FIFO tree group multithread parallel storage buffer module, the unsatisfiable clauses are randomly written into the FIFO.
Further, after the unsatisfiable clauses are written into the FIFO randomly when the unsatisfiable clauses are inverted by the argument inversion module in the FIFO tree group multithread parallel memory buffer module group, the method further comprises: and emptying the data in the buffer module group.
Furthermore, the clause data sent by the first register module to the first evaluation module group also includes a sign bit for indicating whether the first evaluation module group needs to evaluate the satisfiability or non-satisfiability of the clause data.
Further, the hardware SAT solver further comprises: and a random number generation module.
Turning the clause argument according to the probability of the probability mapping table, specifically comprising:
the counter module calculates break-value values of all the inverted variables in the first evaluation module group and sorts the break-value values; comparing the break-value values after the variable ordering with a probability mapping table, if the break-value values of the variables exist in the probability mapping table, generating random numbers by a random number generating module, and selecting the variables corresponding to the break-value values corresponding to the random numbers by a variable overturning module to overturn; and if the break-value of the argument does not exist in the probability mapping table, the argument overturning module selects the argument corresponding to the minimum break-value to overturn.
Further, the hardware SAT solver further comprises: and a random address generation module. The second evaluation module reads a clause from the address of the second register module group according to the random address generated by the random address generation module.
Further, the probability mapping table stores in advance a plurality of sets of break-value values corresponding to the highest occurrence probability.
Preferably, the probability mapping table pre-stores the corresponding 78 sets of break-value values with the highest probability of occurrence.
Preferably, the hardware SAT solver is implemented based on a Xilinx Virtex-6 FPGA chip.
The invention has the following beneficial effects: the invention provides a hardware SAT solver with multi-thread parallel execution, all data are stored in an on-chip memory of an FPGA, so that the time overhead caused by reading off-chip data is avoided, simultaneously, a multi-thread strategy is utilized, different threads interact the same address mapping table and clause mapping table, the resource overhead of the on-chip memory is greatly reduced, and the total turnover per second is multiplied by using the multi-thread strategy, so that the solving success rate is high.
Drawings
FIG. 1 is a block diagram of one embodiment of a multi-threaded parallel execution hardware SAT solver of the present invention;
FIG. 2 is a block diagram of a first register block of an embodiment of a multi-threaded parallel execution hardware SAT solver of the present invention.
Detailed Description
The present invention will be described in further detail below with reference to the drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the invention and do not limit the invention.
The hardware SAT solver with multi-thread parallel execution is realized by adopting the FPGA technology, all data of the solver is stored in an on-chip memory of the FPGA, so that the time overhead caused by reading off-chip data is avoided, and the maximum performance can be achieved. Meanwhile, a multithreading strategy is utilized, the resource overhead of the on-chip memory is greatly reduced, the total turnover amount per second is increased in multiples, and the solving success rate is high.
In an alternative embodiment, the present invention provides a structure of a hardware SAT solver with multi-thread parallel execution, as shown in fig. 1, including a first register module 1, a first evaluation module group 2, a buffer module group 3, a counter module 4, an argument flipping module 5, a probability mapping table 6, a FIFO tree group 8, a second register module group 9, a second evaluation module 10, and a third register module 11.
The first register module 1 is configured to store a clause corresponding to the initial assignment of the CNF formula argument. The first evaluation module group 2 comprises a plurality of groups of parallel first evaluation modules, and is used for storing the clauses sent by the first register module 1 and the clauses after argument reversal in a multithread-parallel manner. And the buffer module group 3 comprises a plurality of groups of parallel buffer modules and is used for assigning the temporarily turned characters through the multithread parallel buffer. The counter module 4 is used for calculating break-value values after each argument in the buffer module group 3 is turned over, and sorting the break-values. The probability mapping table 6 is used for storing break-value values corresponding to different flip probabilities in advance. And the argument overturning module 5 is used for overturning clause arguments according to the probability of the probability mapping table 6. The FIFO tree group 8 comprises a plurality of groups of parallel FIFO trees, each group of FIFO trees comprises a plurality of levels of FIFO, and the FIFO trees are used for storing the unsatisfied clauses in the multithread parallel buffer module group 3 after the clauses are overturned by the argument overturning module 5. And the second register module group 9 comprises a plurality of parallel second register modules and is used for receiving unsatisfiable clauses from the FIFO tree group 8 in a multithread parallel mode. A second evaluation module 10, configured to randomly read a clause from the second register module group 9, and evaluate whether the clause is satisfiable or unsatisfiable, and if the clause is satisfiable, continue to randomly read a clause from the second register module group 9, and evaluate whether the clause is satisfiable or unsatisfiable; if the clause is unsatisfiable, the unsatisfiable clause is sent to the third register module 11. The third register module 11 is configured to store the clauses that are evaluated as unsatisfiable by the second evaluation module 10, search for the clause in the first register module 1 that contains the negative characters of the characters in the clause, and send the clause to the first evaluation module group 2.
In this embodiment, the first register module 1 of the hardware SAT solver executed in parallel by multiple threads is used to store a clause corresponding to the initial assignment of the CNF formula argument. It is well known that as the complexity of the practical application of the SAT problem increases, the scale of the problem increases rapidly, and the number of arguments can reach tens of millions or even higher. Most of the random local search type algorithms and other incomplete algorithms that solve the SAT problem are designed to randomly generate a true value as the starting point for the search. And reasonable variable assignment can greatly reduce the complexity of the problem and improve the solving efficiency. It is possible to analyze the relationships between arguments in the problem library and the solution space of the SAT problem first and then assign the truth assignments of some arguments. By constraining initial assignment of all variables in the SAT example, the search trend assigned by the optimal truth value is guided in advance, so that the optimal solution is quickly found, the turnover times in the search process and the solution space of the search are reduced, the extra time overhead is reduced, and the solution process of the solver is accelerated.
In this embodiment, the hardware SAT solver for multi-thread parallel execution includes a plurality of parallel first evaluation module groups 2, buffer module groups 3, FIFO tree groups 8, and second register module groups 9, and is configured to implement multi-thread parallel processing.
In this embodiment, the probability mapping table 6 is used to store break-value values corresponding to different flip probabilities in advance. In the prior art, break-value of an argument is defined as: in a given CNF formula F, all arguments are assigned with a and x, when the argument x is flipped, the clauses that were satisfied before the flip may become unsatisfiable, and the number of these clauses that are true to false is the break-value of the argument x, which is denoted as break (x, F, α).
Realizing an exponential function or a polynomial function in an FPGA brings about a large time and area overhead, and therefore, how to quickly and effectively select the most suitable argument is a key in each argument flipping process. Theoretically, it is possible to generate 7 for the random 3-SAT problem 3 343 in combination, but in reality, when 3 arguments have the same break-value, the probability of each argument flipping is equal, all 0.33, such as (0,0,0), (1,1,1), etc. Similarly, the probability of argument flipping with the same break-value is also fixed for different permutations of the same set of break-value values. E.g. after flipping argument c 1 ＝(l 1 ,l 2 ,l 3 ) And c 2 ＝(l 4 ,l 5 ,l 6 ) The corresponding break-value values are (0,1,2) and (1,2,0), respectively, for the word l 1 And l 6 Which is the same for the argument flip probability. Likewise, l 2 And l 4 ，l 3 And l 5 The probability of flipping is also equal. Based on the two principles, the actually generated combination number is common to the random 3-SAT problem that the average maximum value of break-value is 6
For the random 3-SAT problem, the probability of occurrence of the break-value greater than or equal to 7 is extremely low, and even if the break-value is greater than or equal to 7 after the argument is turned, the probability of being selected is very low according to the calculation of a probability distribution function, because if the argument is turned, more unsatisfiable clauses are generated, which is the situation that an algorithm needs to avoid as much as possible. Conversely, for arguments with a small break-value, the probability of being selected is relatively greater and the search process converges more easily.
In order to optimize the probability data storage structure, before the solution is started, the probability mapping table 6 prestores a plurality of groups of break-value values corresponding to the highest probability of occurrence, and in particular, sequences the break-value values corresponding to the arguments in the 78 probability distributions with the highest probability of occurrence in the table, and then sequentially downloads all data into an on-chip memory of the FPGA, that is, the probability mapping table 6 prestores the 78 groups of break-value values corresponding to the highest probability of occurrence. The solving efficiency can be effectively improved by looking up the table instead of directly calculating the distribution function.
In this embodiment, the characters are temporarily turned over in parallel buffer modules of the buffer module group 3, and the hardware SAT solver further includes a random number generation module 7.
The argument overturning module overturns clause arguments according to the probability of the probability mapping table, and specifically comprises the following steps: the counter module 4 calculates break-value values of the inverted variables in the buffer module group 3 and sorts the break-values. Comparing the break-value values of the sorted arguments with a probability mapping table 6, if the break-value values of the arguments exist in the probability mapping table 6, generating a random number by a random number generating module 7, and selecting the arguments corresponding to the break-value values corresponding to the random number by an argument overturning module 5 for overturning; if the break-value of the argument does not exist in the probability mapping table, the argument flipping module 5 selects the argument corresponding to the minimum break-value to flip.
And when unsatisfiable clauses are overturned by the argument overturning module 5 in the FIFO tree group 8 multithread parallel storage buffer module group 3, the unsatisfiable clauses are randomly written into the FIFO.
In an optional embodiment, after the unsatisfiable clauses after being inverted by the argument inversion module 5 in the FIFO tree group 8 multithread parallel memory buffer module group 3 are written into the FIFO at random, the method further includes: the data in the buffer module group 3 is emptied.
The FIFO-tree group 8 then sends in parallel the unsatisfiable clauses thereof into the parallel sets of second register modules of the second register module group 9.
The second evaluation module 10 randomly reads a clause from the second register module group 9 and evaluates whether the clause is satisfiable or not, and if the clause is satisfiable, continues to randomly read a clause from the second register module group 9 and evaluates whether the clause is satisfiable or not; if the clause is unsatisfiable, the unsatisfiable clause is sent to the third register module 11.
In an alternative embodiment, to enable the second evaluation module 10 to randomly read a clause from the second register module group 9, the hardware SAT solver further comprises: the random address generating module 12, the second evaluation module 10 reads a clause from the address of the second register module group 9 according to the random address generated by the random address generating module 12.
The third register module 11 stores the clauses that are evaluated as unsatisfiable by the second evaluation module 10, searches for the clause containing the negative characters of the characters in the clause in the first register module 1, and sends the clause to the first evaluation module group 2. The clause data sent by the first register module 1 to the first evaluation module group 2 also includes a sign bit for indicating whether the first evaluation module group 2 needs to evaluate the clause data for satisfiability or non-satisfiability.
When the FIFO tree group 8 and the second register module group 9 are both empty, it is explained that the SAT solver finds a solution to the problem, the search is stopped, and the circuit is in an idle state.
In an optional embodiment, a structure diagram of a first register module of a hardware SAT solver executed in parallel by multiple threads is shown in fig. 2, in this embodiment, the first register module includes an address mapping table 101 and a clause mapping table 102, and data of a clause corresponding to an initial assignment of a CNF formula argument is stored in the address mapping table 101 and the clause mapping table 102.
In an alternative embodiment, a hardware SAT solver for multi-threaded parallel execution may be implemented based on a Xilinx Virtex-6 FPGA chip. The Virtex-6 FPGA is based on a 40nm manufacturing process adopting a third-generation Xilinx Advanced Silicon Module (ASMBL) architecture, and the ASMBL realizes the concept of supporting application platforms in multiple special fields by using a unique column-based structure. The Virtex-6 FPGA perfectly combines the advanced hardware chip technology, the innovative circuit design technology and the enhancement on the architecture, and compared with the prior Virtex device and the competitive FPGA product, the internal core voltage is only 1.0v, so the power consumption is greatly reduced, the performance is higher and the cost is lower. XC6VHX565T is logically resource rich, containing up to 88k slices, each slice consisting of 4 look-up tables and 8 flip-flops, and 32kb on-chip ROM.
In this embodiment, the hardware SAT solver executed in parallel by multiple threads can be implemented by using a Xilinx Virtex-6 FPGA chip, and the hardware SAT solver executed in parallel by multiple threads is compiled and downloaded to the Xilinx Virtex-6 FPGA chip, that is, the SAT problem can be solved, which is not described herein again.
The embodiment of the invention provides a hardware SAT solver with multi-thread parallel execution, all data are stored in an on-chip memory of an FPGA, so that the time overhead caused by reading off-chip data is avoided, meanwhile, by utilizing a multi-thread strategy, different threads interact with the same address mapping table and clause mapping table, the resource overhead of the on-chip memory is greatly reduced, and the total turnover per second is increased in multiple due to the multi-thread strategy, so that the solving success rate is high.
Although the preferred embodiments of the present invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, and the scope of the invention should not be limited to the embodiments described above. It will be apparent to those skilled in the art that various modifications can be made without departing from the spirit of the invention, and these modifications should be construed as within the scope of the invention.
Claims (10)
1. A hardware SAT solver for multi-threaded parallel execution,
the method comprises the following steps: the system comprises a first register module, a first evaluation module group, a buffer module group, a counter module, a argument rollover module, a probability mapping table, a FIFO tree group, a second register module group, a second evaluation module and a third register module;
the first register module is used for storing a clause corresponding to the CNF formula argument initial assignment;
the first evaluation module group comprises a plurality of groups of parallel first evaluation modules and is used for storing the clauses sent by the first register module and the clauses after argument reversal in a multithread parallel manner;
the buffer module group comprises a plurality of groups of parallel buffer modules and is used for assigning values of temporarily turned characters in the multithread parallel buffer;
the counter module is used for calculating break-value values of all the inverted variables in the buffer module group and sequencing the break-values;
the probability mapping table is used for pre-storing break-value values corresponding to different turning probabilities;
the argument turning module is used for turning clause arguments according to the probability of the probability mapping table;
the FIFO tree group comprises a plurality of groups of parallel FIFO trees, each group of FIFO trees comprises a plurality of levels of FIFO, and the FIFO tree is used for storing clauses which cannot be satisfied after being overturned by the argument overturning module in the multithreading parallel buffer module group;
the second register module group comprises a plurality of groups of parallel second register modules and is used for receiving unsatisfiable clauses from the FIFO tree group in a multithreading parallel manner;
the second evaluation module is used for randomly reading a clause from the second register module group and evaluating whether the clause is satisfiable or unsatisfiable, if the clause is satisfiable, the second evaluation module continues to randomly read a clause from the second register module group and evaluates whether the clause is satisfiable or unsatisfiable; if the clause is unsatisfiable, sending the unsatisfiable clause to a third register module;
and the third register module is used for storing the clauses which are evaluated to be unsatisfiable by the second evaluation module, searching the clauses containing the negative characters of the characters in the clauses in the first register module and sending the clauses to the first evaluation module group.
2. The multi-threaded parallel execution hardware SAT solver of claim 1,
the first register module comprises an address mapping table and a clause mapping table, and data of clauses corresponding to the CNF formula argument initial assignment are stored in the address mapping table and the clause mapping table.
3. The multi-threaded parallel execution hardware SAT solver of claim 1,
and when unsatisfiable clauses are overturned by the argument overturning module in the FIFO tree group multithread parallel storage buffer module group, the unsatisfiable clauses are randomly written into the FIFO.
4. The multi-threaded parallel execution hardware SAT solver of claim 3,
after the unsatisfiable clauses are written into the FIFO randomly in the event of unsatisfiable clauses after being overturned by the argument overturning module in the FIFO tree group multithread parallel storage buffer module, the method also comprises the following steps:
and emptying the data in the buffer module group.
5. The multi-threaded parallel execution hardware SAT solver of claim 2,
the clause data sent by the first register module to the first evaluation module group further comprises a sign bit for indicating whether the first evaluation module group needs to evaluate satisfiability or non-satisfiability of the clause data.
6. A multi-threaded parallel execution hardware SAT solver as recited in claim 1,
the hardware SAT solver further comprising: a random number generation module;
the turning over the clause argument according to the probability of the probability mapping table specifically includes:
the counter module calculates break-value values after all the variables in the buffer module group are turned over, and sequences the break-value values;
comparing the break-value values after the variable ordering with the probability mapping table, if the break-value values of the variables exist in the probability mapping table, generating a random number by the random number generating module, and selecting the variables corresponding to the break-value values corresponding to the random number by the variable overturning module to overturn; and if the break-value of the argument does not exist in the probability mapping table, the argument overturning module selects the argument corresponding to the minimum break-value to overturn.
7. The multi-threaded parallel execution hardware SAT solver of claim 1,
the hardware SAT solver further comprises: a random address generation module;
the second evaluation module reads a clause from the address of the second register module group according to the random address generated by the random address generation module.
8. The multi-threaded parallel execution hardware SAT solver of claim 1,
the probability mapping table prestores a plurality of groups of break-value values with the highest occurrence probability.
9. The multi-threaded parallel execution hardware SAT solver of claim 8,
the probability mapping table pre-stores the corresponding 78 sets of break-value values with the highest probability of occurrence.
10. The multi-threaded parallel execution hardware SAT solver of claim 1,
the hardware SAT solver is realized on the basis of a Xilinx Virtex-6 FPGA chip.
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