CN111159088A - IIC bus communication method and system based on heterogeneous multi-core processor - Google Patents
IIC bus communication method and system based on heterogeneous multi-core processor Download PDFInfo
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- CN111159088A CN111159088A CN201911196799.5A CN201911196799A CN111159088A CN 111159088 A CN111159088 A CN 111159088A CN 201911196799 A CN201911196799 A CN 201911196799A CN 111159088 A CN111159088 A CN 111159088A
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- iic
- bus communication
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40006—Architecture of a communication node
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0016—Inter-integrated circuit (I2C)
Abstract
The invention relates to the technical field of equipment fault diagnosis, in particular to an IIC bus communication method and system based on a heterogeneous multi-core processor; the method comprises S1, performing hardware configuration; the method specifically comprises the steps of configuring the communication rate and the address length of IIC master equipment nodes, the number and the physical address of IIC slave equipment nodes, the receiving interrupt priority, an interrupt processing function and the initial address and the length of a shared memory; s2, starting an IIC bus communication flow; specifically, the method comprises the steps of sending data to an external IIC equipment node through main write operation; reading and processing the data returned by the external IIC equipment node; the system comprises an ARM and an FPGA; according to the embodiment of the invention, the data returned by the external IIC equipment node is stored in the shared memory, so that the data exchange between the ARM and the FPGA is realized, and the stability and the real-time performance of the state monitoring and fault diagnosis functions are improved.
Description
Technical Field
The invention relates to the technical field of equipment fault diagnosis, in particular to an IIC bus communication method and system based on a heterogeneous multi-core processor.
Background
With the improvement of the requirements on the testability and the maintainability of the equipment, the requirements on the condition monitoring and the fault diagnosis of the equipment are more and more urgent. The state monitoring and fault diagnosis function is mainly implemented by an IPMB (intelligent platform Management Bus) based on the IIC Bus, and a BMC (Baseboard Management Controller, BMC) of each functional module in the system exchanges data through the IPMB Bus. There are 2 modes of data flow on the bus: query response mode, event mode. In the query response mode, the master BMC sends a query instruction, and the slave BMC responds to the query instruction after receiving the instruction and returns data. In the event mode, the slave BMC sends event information, such as state information of voltage overrun, fan stalling and the like, to the master BMC, and the master BMC responds after receiving the time information.
At present, when the state monitoring and fault diagnosis function normally operates, a data sender is always used as an IIC bus communication master node, a data receiver is always used as an IIC bus communication slave node, and both a master BMC and a slave BMC need to frequently switch master nodes and slave nodes, so the success rate and the speed of master-slave switching directly influence the stability and the real-time performance of data exchange.
Disclosure of Invention
In order to overcome the defects of the prior art, embodiments of the present invention provide an IIC bus communication method and system based on a heterogeneous multi-core processor, so that on the premise of implementing 2 operating modes of an IPMB bus, frequent master-slave switching is avoided, and stability and real-time performance of state monitoring and fault diagnosis functions are improved.
On one hand, the embodiment of the invention provides an IIC bus communication method based on a heterogeneous multi-core processor, which comprises the following steps:
s1, configuring hardware parameters; the method specifically comprises the steps of configuring the communication speed and the address length of IIC master equipment nodes, the number and the physical address of IIC slave equipment nodes, the receiving interrupt priority, an interrupt processing function and the initial address and the length of a shared memory;
s2, starting an IIC bus communication flow; specifically, the method comprises the steps that the IIC master equipment node is controlled to send data to the external IIC equipment node through main write operation; processing the stored data returned by the external IIC equipment node; the sending data comprises a query instruction and event information.
On the other hand, the embodiment of the invention provides an IIC bus communication system based on a heterogeneous multi-core processor, which comprises an ARM and an FPGA; the ARM is provided with a user control unit, an ARM core, a shared memory and an IIC main equipment node, the FPGA is provided with a plurality of IIC slave equipment nodes, and the ARM and the FPGA are connected through an AXI _ HP interface; and the ARM and the FPGA exchange external IIC equipment nodes in the shared memory to return data.
The embodiment of the invention provides an IIC bus communication method and system based on a heterogeneous multi-core processor; data returned by the external IIC equipment node is stored in the shared memory, so that data exchange between the ARM and the FPGA is realized, frequent switching of a master node and a slave node under a query response mode and an event mode is avoided, and the stability and the real-time performance of the state monitoring and fault diagnosis functions are improved.
Drawings
In order to more clearly illustrate the technical solution of the present invention, the drawings needed to be used in the technical description of the present invention will be briefly introduced below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without inventive labor.
FIG. 1 is a schematic flowchart of an IIC bus communication method based on a heterogeneous multi-core processor according to an embodiment of the present invention;
FIG. 2 is a sub-flow diagram of an IIC bus communication method based on a heterogeneous multi-core processor according to an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of an IIC bus communication system based on a heterogeneous multi-core processor according to an embodiment of the present invention;
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
FIG. 1 is a schematic flowchart of an IIC bus communication method based on a heterogeneous multi-core processor according to an embodiment of the present invention; FIG. 2 is a sub-flow diagram of an IIC bus communication method based on a heterogeneous multi-core processor according to an embodiment of the present invention;
as shown in fig. 1 and 2, the method comprises the following steps:
s1, configuring hardware parameters; the method specifically comprises the steps of configuring the communication speed and the address length of IIC master equipment nodes, the number and the physical address of IIC slave equipment nodes, the receiving interrupt priority, an interrupt processing function and the initial address and the length of a shared memory;
s2, starting an IIC bus communication flow; specifically, the method comprises the steps that the IIC master equipment node is controlled to send data to the external IIC equipment node through main write operation; processing the stored data returned by the external IIC equipment node; the sending data comprises a query instruction and event information.
Further, the step S2 specifically includes:
s21, storing the return data of the external IIC equipment node in the shared memory;
s22, the IIC slave device node sends an interrupt signal to inform that the return data is ready;
s23, executing an interrupt processing function, and reading return data from the shared memory; the method specifically comprises the steps of checking and analyzing the returned data according to a message protocol and carrying out subsequent processing.
Specifically, the user control unit firstly configures hardware parameters; the IIC master device node starts an IIC bus communication process, performs master write operation on the IIC master device node, and sends data to an external IIC device node; the IIC slave equipment node copies the return data into the shared memory and sends an interrupt signal to the ARM core if receiving the return data; the user control unit executes an interrupt processing function, and the ARM can read data from the shared memory;
the embodiment of the invention provides an IIC bus communication method based on a heterogeneous multi-core processor; data returned by the external IIC equipment node is stored in the shared memory, so that data exchange between the ARM and the FPGA is realized, frequent switching of a master node and a slave node under a query response mode and an event mode is avoided, and the stability and the real-time performance of the state monitoring and fault diagnosis functions are improved.
Further, in the step S1, the number of IIC slave device nodes may be increased or decreased dynamically according to actual needs. The dynamic addition and deletion slave nodes can flexibly schedule resources according to actual use conditions, such as redundant FPGA resources are used for other purposes; for example, in a computer system supporting hot plug, a plurality of functional blades are configured in a chassis, and when a certain blade needs to be repaired on the premise of not shutting down the system, the blade needs to be unplugged first, and at this time, the user control unit deletes the corresponding slave node, and recycles the part of FPGA resources. And after the maintenance is finished, the system is inserted back into the case, and the user control unit increases the corresponding slave nodes again.
Based on the above embodiments, fig. 3 is a schematic structural diagram of an IIC bus communication system based on a heterogeneous multi-core processor according to an embodiment of the present invention; comprises an ARM and an FPGA; the ARM is provided with a user control unit, 2 ARM cores, a shared memory and an IIC master device node, the FPGA is provided with a plurality of IIC slave device nodes, and the ARM and the FPGA are connected through an AXI _ HP interface to realize the access of the ARM to data in the FPGA; and the ARM and the FPGA exchange external IIC equipment nodes in the shared memory to return data, and because the ARM can directly access the DDR of the shared memory, the ARM and the FPGA can communicate through the shared memory.
The embodiment of the invention provides an IIC bus communication system based on a heterogeneous multi-core processor to execute the method; data returned by the external IIC equipment node is stored in the shared memory, so that data exchange between the ARM and the FPGA is realized, frequent switching of a master node and a slave node under a query response mode and an event mode is avoided, and the stability and the real-time performance of the state monitoring and fault diagnosis functions are improved.
The above-described embodiments of the apparatus are merely illustrative, and the units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.
Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware. With this understanding in mind, the above-described technical solutions may be embodied in the form of a software product, which can be stored in a computer-readable storage medium such as ROM/RAM, magnetic disk, optical disk, etc., and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the methods described in the embodiments or some parts of the embodiments.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (6)
1. An IIC bus communication method based on a heterogeneous multi-core processor is characterized by comprising the following steps:
s1, configuring hardware parameters; the method specifically comprises the steps of configuring the communication speed and the address length of IIC master equipment nodes, the number and the physical address of IIC slave equipment nodes, the receiving interrupt priority, an interrupt processing function and the initial address and the length of a shared memory;
s2, starting an IIC bus communication flow; specifically, the method comprises the steps that the IIC main equipment node sends data to an external IIC equipment node; processing the stored data returned by the external IIC equipment node; the sending data comprises a query instruction and event information.
2. The IIC bus communication method based on the heterogeneous multi-core processor according to claim 1, wherein the step S2 specifically includes:
s21, storing the return data of the external IIC equipment node in the shared memory;
s22, the IIC slave device node sends an interrupt signal to inform that the return data is ready;
s23, executing an interrupt processing function, and reading return data from the shared memory; the method specifically comprises the steps of checking and analyzing the returned data according to a message protocol and carrying out subsequent processing.
3. The IIC bus communication method based on the heterogeneous multi-core processor of claim 1, wherein in the step S1, the number of IIC slave device nodes can be increased or decreased dynamically according to actual needs.
4. An IIC bus communication system based on a heterogeneous multi-core processor is characterized by comprising an ARM and an FPGA; the ARM is provided with a user control unit, an ARM core, a shared memory and an IIC master device node, the FPGA is provided with a plurality of IIC slave device nodes, and the ARM and the FPGA are connected through an AXI _ HP interface; and the ARM and the FPGA exchange external IIC equipment nodes in the shared memory to return data.
5. The IIC bus communication system based on the heterogeneous multi-core processor as claimed in claim 4, wherein the FPGA stores the return data of the external IIC device node in the shared memory; sending an interrupt signal to the ARM core to inform that the returned data is ready; the ARM core executes an interrupt processing function and reads return data from the shared memory; the method specifically comprises the steps of checking and analyzing the returned data according to a message protocol and carrying out subsequent processing.
6. The IIC bus communication system based on the heterogeneous multi-core processor as claimed in claim 4, wherein the number of IIC slave device nodes on the FPGA can be increased or deleted dynamically according to actual needs.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111817895A (en) * | 2020-07-14 | 2020-10-23 | 济南浪潮数据技术有限公司 | Master control node switching method, device, equipment and storage medium |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130318084A1 (en) * | 2012-05-22 | 2013-11-28 | Xockets IP, LLC | Processing structured and unstructured data using offload processors |
| CN104820657A (en) * | 2015-05-14 | 2015-08-05 | 西安电子科技大学 | Inter-core communication method and parallel programming model based on embedded heterogeneous multi-core processor |
| CN204965148U (en) * | 2015-07-22 | 2016-01-13 | 中国科学院上海技术物理研究所 | Distributing type sensor network system based on NFC technique |
| US20160161466A1 (en) * | 2013-08-30 | 2016-06-09 | Magnomics S.A. | Scalable and high throughput biosensing platform |
| CN106371357A (en) * | 2016-08-31 | 2017-02-01 | 中国船舶重工集团公司第七〇二研究所 | Multi-chip controller based on SoC-FPGA and large-power variable flow control device |
| CN107196695A (en) * | 2017-04-07 | 2017-09-22 | 西安电子科技大学 | Inter-satellite Links test system based on Zynq |
| CN107679009A (en) * | 2017-10-27 | 2018-02-09 | 中国航空无线电电子研究所 | Generalization hardware and software platform based on heterogeneous polynuclear framework |
| CN108231132A (en) * | 2017-12-28 | 2018-06-29 | 北京兆易创新科技股份有限公司 | A kind of nand flash memory verification device and verification system |
-
2019
- 2019-11-29 CN CN201911196799.5A patent/CN111159088A/en not_active Withdrawn
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130318084A1 (en) * | 2012-05-22 | 2013-11-28 | Xockets IP, LLC | Processing structured and unstructured data using offload processors |
| US20160161466A1 (en) * | 2013-08-30 | 2016-06-09 | Magnomics S.A. | Scalable and high throughput biosensing platform |
| CN104820657A (en) * | 2015-05-14 | 2015-08-05 | 西安电子科技大学 | Inter-core communication method and parallel programming model based on embedded heterogeneous multi-core processor |
| CN204965148U (en) * | 2015-07-22 | 2016-01-13 | 中国科学院上海技术物理研究所 | Distributing type sensor network system based on NFC technique |
| CN106371357A (en) * | 2016-08-31 | 2017-02-01 | 中国船舶重工集团公司第七〇二研究所 | Multi-chip controller based on SoC-FPGA and large-power variable flow control device |
| CN107196695A (en) * | 2017-04-07 | 2017-09-22 | 西安电子科技大学 | Inter-satellite Links test system based on Zynq |
| CN107679009A (en) * | 2017-10-27 | 2018-02-09 | 中国航空无线电电子研究所 | Generalization hardware and software platform based on heterogeneous polynuclear framework |
| CN108231132A (en) * | 2017-12-28 | 2018-06-29 | 北京兆易创新科技股份有限公司 | A kind of nand flash memory verification device and verification system |
Non-Patent Citations (2)
| Title |
|---|
| GRZEGORZ GRZĘDA等: ""Time interval measurement module implemented in SoC FPGA device"", 《INTL JOURNAL OF ELECTRONICS AND TELECOMMUNICATIONS》 * |
| 朱新召等: ""基于多核处理器的多层感知神经网络设计和实现"", 《微电子学与计算机》 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111817895A (en) * | 2020-07-14 | 2020-10-23 | 济南浪潮数据技术有限公司 | Master control node switching method, device, equipment and storage medium |
| CN111817895B (en) * | 2020-07-14 | 2023-04-07 | 济南浪潮数据技术有限公司 | Master control node switching method, device, equipment and storage medium |
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