CN111158451A - Electronic equipment and power supply method - Google Patents

Electronic equipment and power supply method Download PDF

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Publication number
CN111158451A
CN111158451A CN201911413854.1A CN201911413854A CN111158451A CN 111158451 A CN111158451 A CN 111158451A CN 201911413854 A CN201911413854 A CN 201911413854A CN 111158451 A CN111158451 A CN 111158451A
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power supply
signal
port
power
voltage domain
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朱建荣
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Lusheng Technology Co ltd
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Lusheng Technology Co ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/30—Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations
    • G06F1/305—Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations in the event of power-supply fluctuations

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Sources (AREA)

Abstract

The invention relates to an electronic device comprising: a processor having a first power port, a second power port, and a first signal port, the processor configured to transmit and receive signals through the first signal port; a memory having a third power port, a fourth power port, and a second signal port, the memory configured to receive and transmit signals through the second signal port; a first power supply configured to provide a first voltage domain, the first power supply being connected to the processor through a first power port and to the memory through a third power port; and a second power supply configured to provide a second voltage domain; the second power supply is connected with the processor through a second power supply port and is connected with the memory through a fourth power supply port.

Description

Electronic equipment and power supply method
Technical Field
The invention relates to an electronic device which can effectively reduce the jitter of signals, increase the margin of the signals, and has higher operation frequency and lower manufacturing cost.
Background
With the improvement of system performance of electronic devices, the bandwidth requirement of a memory (memory) is greater, and the frequency is higher when the bandwidth is larger. The higher the frequency, the smaller the cycle time of the signal, and the smaller the setup and hold times of the signal samples. In order to ensure the normal read-write communication, the requirements of the setup time and the hold time must be satisfied in the timing sequence.
Fig. 1 is a schematic diagram of a signal setup time and hold time. Referring to fig. 1, in an ideal case without signal jitter (jitter), the signal setup time is tDS0 and the hold time is tDH 0. When signal jitter is present, the signal setup time is tDS1 and the hold time is tDH 1. Both the signal settling time and the hold time with signal jitter become smaller compared to the ideal state without signal jitter.
Ideally, the edges (edge) of each address should not be perfectly aligned, and when the clock signal (CLK) goes late, the margin (margin) of the hold time of the control address signal (CA) that operates earlier becomes smaller, and when the clock signal goes early, the margin of the setup time of the address signal that operates later becomes smaller.
The jitter of the clock signal can be used to measure the degree of the jitter of the clock signal, and when the jitter of the clock signal increases, the margins before and after the control address signal are reduced. Also, as the jitter of the data strobe signal (DQS) increases, the margins before and after the data signal (DQ) become smaller.
Power supply ripple is an important factor causing signal jitter. Fig. 2 is a schematic diagram of an equivalent circuit of a driving circuit of an input-output port. Referring to fig. 2, a driving circuit of an input/output port (IO) may be equivalent to a metal-oxide semiconductor field effect transistor (MOSFET) and a capacitor. The signal delay is calculated as follows:
Delay＝C/k(Vgs-Vth) (1)
wherein Delay is a signal Delay, C is a capacitance (capacitance), k is a coefficient (coefficient), Vgs is a Gate-source voltage (Gate to source voltage), and Vth is a Gate-source threshold voltage (Gate to source threshold voltage).
Fig. 3 is a delay diagram of an input/output port. Referring to fig. 3, compared to the normal level V of the input/output portNOMWhen high level voltage V of portHThe higher the Delay (TD, Time Delay), the shorter (Faster) the low level voltage V at the portLThe lower the delay, the longer the delay (Slower). The larger the ripple of the power supply, the larger the jitter of the signal.
Fig. 4 is a schematic diagram of a conventional electronic apparatus. Referring to fig. 4, in the conventional electronic device 400, power is supplied in such a manner that all input/output ports (IO) of a Central Processing Unit (CPU)410 and a Memory (Memory)420 are in a VCCQ0 voltage domain. The VCCQ0 voltage domain is provided by the same power supply 430.
The power supply ripple mainly comprises two parts, namely ripple output by the power supply and ripple noise introduced by the wiring inductance (L) of a Printed Circuit Board (PCB). Therefore, the conventional power supply method for the electronic device 400 has the following problems:
first, the load current of the VCCQ0 voltage domain of the memory 420 is large, and the BUCK power supply needs to be used for supplying power, but the ripple of the BUCK power supply itself is large, so that the jitter of the signal is large, and the margin of the signal is small.
Secondly, according to the calculation formula of the power supply ripple:
VRip＝ ZPDN* ISw(2)
wherein, VRipFor power supply ripple, ZPDNDistribution of network impedance for power supply, ISwIs the load current.
Thus, at the power distribution network impedance ZPDN0Without change, the load current ISw0The larger the power supply ripple VRip0The larger the size, the larger the jitter of the signal and the smaller the margin of the signal.
Thirdly, due to the load current ISw0Larger, to achieve small supply ripple VRip0Then the power distribution network impedance ZPDN0It must be small. In order to achieve a smaller impedance ZPDN0The trace inductance of the PCB needs to be reduced, which requires the traces of the PCB to be short and wide, and the number of layers of the PCB may be increased, thereby increasing the design difficulty and manufacturing cost of the PCB.
In addition, to achieve a small power distribution network impedance ZPDN0It is also desirable to consider the addition of decoupling capacitors (decap) on the die, package and PCB to reduce the power distribution network impedance ZPDN0The design difficulty and the manufacturing cost of the electronic device are also increased.
In view of this, the prior art is subject to further improvement.
Disclosure of Invention
The invention aims to provide an electronic device which can effectively reduce the jitter of signals and increase the margin of the signals, and has higher operation frequency and lower manufacturing cost.
The present invention provides an electronic device for solving the above-mentioned problems, including: a processor having a first power port, a second power port, and a first signal port, the processor configured to send and receive signals through the first signal port; a memory having a third power port, a fourth power port, and a second signal port, the memory configured to receive and transmit the signal through the second signal port; a first power supply configured to provide a first voltage domain, the first power supply connected to the processor through the first power port and connected to the memory through the third power port; and a second power supply configured to provide a second voltage domain; the second power supply is connected to the processor through the second power supply port and to the memory through the fourth power supply port.
In an embodiment of the present invention, the signals include a data signal, a control address signal, a data strobe signal, and a clock signal; the first power supply is configured to provide the first voltage domain for the data signals and the control address signals through the first power port and the third power port; the second power supply is configured to provide the second voltage domain for the data strobe signal and the clock signal through the second power port and the fourth power port.
In an embodiment of the invention, the first power supply is a dc conversion power supply, and the second power supply is a low dropout regulator.
In an embodiment of the invention, the processor further has a fifth power port, the memory further has a sixth power port, the electronic device further includes a third power source, the third power source is connected to the processor through the fifth power port and is connected to the memory through the sixth power port, the signals include a data signal, a control address signal, a data strobe signal, and a clock signal; wherein the first power supply is configured to provide the first voltage domain for the data signal and the control address signal through the first power port and the third power port, the second power supply is configured to provide the second voltage domain for the data strobe signal through the second power port and the fourth power port, and the third power supply is configured to provide a third voltage domain for the clock signal through the fifth power port and the sixth power port.
In an embodiment of the invention, the jitter of the data strobe signal is adapted to control the margin of the data signal, and the jitter of the clock signal is adapted to control the margin of the control address signal.
Another aspect of the present invention provides a power supply method applied to an electronic device, the electronic device including a processor, a memory, a first power supply and a second power supply, the processor having a first power port, a second power port and a first signal port, the memory having a third power port, a fourth power port and a second signal port, the first power supply being connected to the processor through the first power port and to the memory through the third power port, the second power supply being connected to the processor through the second power port and to the memory through the fourth power port, the power supply method including: transmitting and receiving signals through the first signal port; receiving and transmitting the signal through the second signal port; providing a first voltage domain; and providing a second voltage domain.
In an embodiment of the present invention, the signals include a data signal, a control address signal, a data strobe signal, and a clock signal, and the power supply method further includes: providing the first voltage domain for the data signals and the control address signals; and providing the second voltage domain for the data strobe signal and the clock signal.
In an embodiment of the invention, the first voltage domain is provided by a dc conversion power supply, and the second voltage domain is provided by a low dropout regulator.
In an embodiment of the invention, the processor further has a fifth power port, the memory further has a sixth power port, the electronic device further includes a third power supply, the third power supply is connected to the processor through the fifth power port and is connected to the memory through the sixth power port, the signals include a data signal, a control address signal, a data strobe signal, and a clock signal, and the power supply method further includes: providing the first voltage domain for the data signals and the control address signals; providing the second voltage domain for the data strobe signal; and providing a third voltage domain for the clock signal.
In an embodiment of the invention, the jitter of the data strobe signal is adapted to control the margin of the data signal, and the jitter of the clock signal is adapted to control the margin of the control address signal.
Due to the adoption of the technical scheme, compared with the prior art, the invention has the following remarkable advantages:
the electronic equipment respectively uses the first power supply and the second power supply to supply power to the processor and the memory, wherein the first power supply provides a first voltage domain, and the second power supply provides a second voltage domain, so that the jitter of signals is effectively reduced, the signal margin is increased, and the electronic equipment has higher operating frequency and lower manufacturing cost.
Drawings
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below, wherein:
FIG. 1 is a schematic diagram of a signal setup time and hold time;
FIG. 2 is a schematic diagram of an equivalent circuit of a driving circuit of an input/output port;
FIG. 3 is a schematic delay diagram of an input/output port;
FIG. 4 is a schematic diagram of a prior art electronic device;
FIG. 5 is a schematic diagram of an electronic device in accordance with an embodiment of the invention;
fig. 6 is a flow chart of a power supply method according to an embodiment of the invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described herein, and thus the present invention is not limited to the specific embodiments disclosed below.
As used in this application and the appended claims, the terms "a," "an," "the," and/or "the" are not intended to be inclusive in the singular, but rather are intended to be inclusive in the plural unless the context clearly dictates otherwise. In general, the terms "comprises" and "comprising" merely indicate that steps and elements are included which are explicitly identified, that the steps and elements do not form an exclusive list, and that a method or apparatus may include other steps or elements.
In describing the embodiments of the present invention in detail, the cross-sectional views illustrating the structure of the device are not enlarged partially in a general scale for convenience of illustration, and the schematic drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary words "below" and "beneath" can encompass both an orientation of up and down. The device may have other orientations (rotated 90 degrees or at other orientations) and the spatial relationship descriptors used herein should be interpreted accordingly. Further, it will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
It will be understood that when an element is referred to as being "on," "connected to," "coupled to" or "contacting" another element, it can be directly on, connected or coupled to, or contacting the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly on," "directly connected to," "directly coupled to" or "directly contacting" another element, there are no intervening elements present. Similarly, when a first component is said to be "in electrical contact with" or "electrically coupled to" a second component, there is an electrical path between the first component and the second component that allows current to flow. The electrical path may include capacitors, coupled inductors, and/or other components that allow current to flow even without direct contact between the conductive components.
The following embodiments of the present invention provide an electronic device that can effectively reduce jitter of a signal, increase a margin of the signal, have a higher operating frequency, and lower manufacturing cost.
It is to be understood that the following description is merely exemplary, and that variations may be made by those skilled in the art without departing from the spirit of the invention.
Fig. 5 is a schematic diagram of an electronic device according to an embodiment of the invention. The electronic device 500 of the present invention is described below with reference to fig. 5.
Referring to fig. 5, the electronic device 500 includes a processor 510, a memory 520, a first power supply 530, and a second power supply 540.
The processor 510 has a first power port (not shown), a second power port (not shown), and a first signal port 511. The processor 510 is configured to transmit and receive signals through a first signal port 511. The memory 520 has a third power port (not shown), a fourth power port (not shown) and a second signal port 521. The memory 520 is configured to receive and transmit signals through the second signal port 521. The first power supply 530 is configured to provide a first voltage domain 501, the first power supply 530 being connected to the processor 510 through a first power port and to the memory 520 through a third power port. The second power supply 540 is configured to provide a second voltage domain 502; the second power supply 540 is connected to the processor 510 through a second power supply port and to the memory 520 through a fourth power supply port.
It is understood that the processor 510 is an execution unit in the electronic device 500, which is responsible for information processing and program operation. Illustratively, a processor may include an operator (arithmetic logic unit, ALU), a Cache memory (Cache), and a Bus (Bus) that enables data transfer and state control of the associations between them. Processors may employ various types of architectures. For example, the architecture of the real-time operating system architecture of the Multi-core processor platform may be a Symmetric Multiprocessing (SMP) architecture, an Asymmetric Multiprocessing (AMP) architecture, a hybrid multiprocessing (BMP) architecture, and the like. Preferably, in the following embodiments of the present invention, the processor 510 is a Central Processing Unit (CPU).
The memory 520 is a unit in the electronic device 500 that temporarily stores operation data in the processor 510 and data exchanged with an external memory. Illustratively, the storage may be internal storage (memory) or a combination of internal and external storage. The memory may be a semiconductor memory unit, such as a Random Access Memory (RAM), a Read Only Memory (ROM), and a CACHE memory (CACHE). The external memory includes, but is not limited to, hard disks, floppy disks, optical disks, U-disks, and the like. Preferably, in the following embodiments of the present invention, the storage 520 is a Memory (Memory).
Referring to fig. 5, in some embodiments, the first signal port 511 and the second signal port 521 may be input/output ports (IO) of the processor 510 and the memory 520, respectively.
In an embodiment of the invention, the first power source 530 may be a direct current (DC/DC) conversion power source, and the second power source 540 is a Low Dropout Regulator (LDO).
The dc conversion power supply may convert a high voltage dc power supply into a low voltage dc power supply or convert a low voltage dc power supply into a high voltage dc power supply. In some examples, the direct current conversion power supply may be a BUCK-type (BUCK) DC/DC power supply, i.e., a BUCK power supply. In other examples, the DC conversion power source may also be a BOOST (BOOST) DC/DC power source, i.e., a BOOST power source, but the application is not limited thereto.
Preferably, in the following embodiments of the present invention, the first power supply 530 is a BUCK power supply.
The low dropout linear regulator is a linear direct current regulator and can provide a stable direct current voltage power supply. Compared with a common linear direct current voltage regulator, the low dropout linear voltage regulator can work under the condition of smaller output and input voltage difference.
Referring to fig. 5, in an embodiment of the present invention, the signals include a data signal (DQ), a control address signal (CA), a data strobe Signal (DQs), and a clock signal (CLK). The first power supply 530 is configured to provide a first voltage domain (VCCQ0)501 for data signals (DQ) and control address signals (CA) through the first power port and the third power port. The second power supply 540 is configured to provide a second voltage domain (VCCQ1)502 for the data strobe signal (DQS) and the clock signal (CLK) through the second power port and the fourth power port.
It should be understood that the voltages of the second voltage domain (VCCQ1)502 and the second voltage domain (VCCQ1)502 may be the same or different, and the embodiment is not limited thereto.
In an embodiment of the present invention, the jitter of the data strobe signal (DQS) is adapted to control the margin of the data signal (DQ), and the jitter of the clock signal (CLK) is adapted to control the margin of the address signal (CA).
Referring to FIG. 5, the first voltageThe load current of the domain (VCCQ0)501 is ISw0Power supply ripple of VRip0. The load current of the second voltage domain (VCCQ1)502 is ISw1Power supply ripple of VRip1。
Since the magnitude of the load current is directly related to the magnitude of the signal. The electronic device 500 of the present invention independently powers the clock signal (CLK) and the data strobe signal (DQS) through the second voltage domain (VCCQ1)502 provided by the second power supply 540 such that the load current I of the second voltage domain (VCCQ1)502Sw1Is small and can be powered using a low dropout linear regulator.
The second power supply 540 using the low dropout linear regulator has a small power supply ripple. Also, the load current I due to the second voltage domain (VCCQ1)502Sw1The power ripple V of the second voltage domain (VCCQ1)502 is small as shown in equation (2)Rip1Is smaller.
Thus, the power supply ripple V of the second voltage domain (VCCQ1)502 is smallRip1So that jitter of the clock signal (CLK) and the data strobe signal (DQS) is small. And the margins of the data signal (DQ) and the control address signal (CA) are controlled by the jitter of the data strobe Signal (DQs) and the clock signal (CLK), respectively. Accordingly, the margins of the clock signal (CLK) and the data strobe signal (DQS) are large, thereby achieving stable operation of the electronic device 500 at higher frequencies.
On the other hand, the load current I due to the second voltage domain (VCCQ1)502Sw1Smaller, routing pair V of PCBRip1The influence of (c) is small. Compared with the conventional electronic device 400 shown in fig. 4, the electronic device 500 of the present invention reduces the requirement for PCB routing, and reduces the design difficulty and manufacturing cost of the electronic device 500.
It should be noted that in some embodiments of the present invention, the data strobe signal (DQS) and the clock signal (CLK) may also be separately powered by different voltage domains provided by different power supplies.
Illustratively, the processor 510 may further have a fifth power port (not shown), the memory 520 may further have a sixth power port (not shown), and the electronic device 500 may further include a third power source (not shown). The third power supply is connected to the processor 510 through a fifth power supply port and to the memory 520 through a sixth power supply port. The signals include a data signal (DQ), a control address signal (CA), a data strobe Signal (DQs), and a clock signal (CLK).
The first power supply 530 is configured to provide a first voltage domain (e.g., the first voltage domain 501 shown in fig. 5) for the data signal (DQ) and the control address signal (CA) through the first power supply port and the third power supply port, the second power supply 540 is configured to provide a second voltage domain (e.g., the second voltage domain 502 shown in fig. 5) for the data strobe Signal (DQs) through the second power supply port and the fourth power supply port, and the third power supply is configured to provide a third voltage domain (not shown) for the clock signal (CLK) through the fifth power supply port and the sixth power supply port.
By supplying power by dividing the data strobe signal (DQS) and the clock signal (CLK) into different voltage domains, the load current can be further reduced, jitter of the data strobe signal (DQS) and the clock signal (CLK) is reduced, and the margins of the data signal (DQ) and the control address signal (CA) are increased.
The above embodiments of the present invention provide an electronic device, which can effectively reduce jitter of a signal, increase a margin of the signal, and have a higher operating frequency and a lower manufacturing cost.
Another aspect of the present invention is to provide a power supply method, which can effectively reduce jitter of signals, increase signal margins, and enable electronic devices to have higher operating frequency and lower manufacturing cost.
It is understood that the power supply method can be implemented in, for example, the electronic device 500 shown in fig. 5 or a variation thereof, but the invention is not limited thereto.
Fig. 6 is a flow chart of a power supply method according to an embodiment of the invention. The method is described below with reference to fig. 1 to 6.
The power supply method is suitable for electronic equipment. Referring to fig. 5, the electronic device 500 includes a processor 510, a memory 520, a first power supply 530, and a second power supply 540.
The processor 510 has a first power port (not shown), a second power port (not shown), and a first signal port 511. The memory 520 has a third power port (not shown), a fourth power port (not shown) and a second signal port 521. The first power supply 530 is connected to the processor 510 through a first power supply port and to the memory 520 through a third power supply port. The second power supply 540 is connected to the processor 510 through a second power supply port and to the memory 520 through a fourth power supply port.
The power supply method comprises the following steps:
step 610, sending and receiving signals through a first signal port.
In some examples, the first signal port 511 may be an input output port (IO) of the processor 510. The processor 510 sends and receives signals through a first signal port 511.
Step 620, receiving and transmitting signals through the second signal port.
In some examples, the second signal port 521 may be an input output port (IO) of the memory 520. The memory 520 receives and transmits signals from the processor 510 through a second signal port 521.
Step 630, a first voltage domain is provided.
Referring to fig. 5, in an embodiment of the invention, the first voltage domain 501 may be provided by a first power supply 530. The first power supply 530 may be a direct current conversion power supply (DC/DC).
The dc conversion power supply may convert a high voltage dc power supply into a low voltage dc power supply or convert a low voltage dc power supply into a high voltage dc power supply. In some examples, the direct current conversion power supply may be a BUCK-type (BUCK) DC/DC power supply, i.e., a BUCK power supply. In other examples, the DC conversion power source may also be a BOOST (BOOST) DC/DC power source, i.e., a BOOST power source, but the application is not limited thereto.
Preferably, in the following embodiments of the present invention, the first power supply 530 is a BUCK power supply.
At step 640, a second voltage domain is provided.
Referring to fig. 5, in an embodiment of the invention, the second voltage domain 502 may be provided by a second power supply 540. The second power supply 540 may be a Low Dropout linear Regulator (LDO).
The low dropout linear regulator is a linear direct current regulator and can provide a stable direct current voltage power supply. Compared with a common linear direct current voltage regulator, the low dropout linear voltage regulator can work under the condition of smaller output and input voltage difference.
In an embodiment of the present invention, the signals include a data signal (DQ), a control address signal (CA), a data strobe Signal (DQs), and a clock signal (CLK). The power supply method further includes: a first voltage domain (VCCQ0)501 is provided for data signals (DQ) and control address signals (CA) and a second voltage domain (VCCQ1)502 is provided for data strobe Signals (DQs) and clock signals (CLK).
Illustratively, the first voltage domain (VCCQ0)501 may be provided by the first power source 530, and the second voltage domain (VCCQ1)502 may be provided by the second power source 540, but the present application is not limited thereto.
In an embodiment of the present invention, the jitter of the data strobe signal (DQS) is adapted to control the margin of the data signal (DQ), and the jitter of the clock signal (CLK) is adapted to control the margin of the address signal (CA).
The second power supply 540 using the low dropout linear regulator has a small power supply ripple. Also, the load current I due to the second voltage domain (VCCQ1)502Sw1The power ripple V of the second voltage domain (VCCQ1)502 is small as shown in equation (2)Rip1Is smaller.
Thus, the power supply ripple V of the second voltage domain (VCCQ1)502 is smallRip1Jitter of the clock signal (CLK) and the data strobe signal (DQS) is made small, and margins of the clock signal (CLK) and the data strobe signal (DQS) are made large, thereby achieving stable operation of the electronic device 500 at higher frequencies.
On the other hand, the load current I due to the second voltage domain (VCCQ1)502Sw1Smaller, routing pair V of PCBRip1The influence of (c) is small. Compared with the conventional electronic device 400 shown in fig. 4, the electronic device 500 of the present invention reduces the requirement for PCB routing, and reduces the design difficulty and manufacturing cost of the electronic device 500.
In an embodiment of the invention, the processor 510 may further have a fifth power port (not shown), the memory 520 may further have a sixth power port (not shown), and the electronic device 500 may further include a third power source (not shown). The third power supply is connected to the processor 510 through a fifth power supply port and to the memory 520 through a sixth power supply port. The signals include a data signal (DQ), a control address signal (CA), a data strobe Signal (DQs), and a clock signal (CLK). The power supply method further includes: a first voltage domain (e.g., the first voltage domain 501 shown in fig. 5) is provided for the data signal (DQ) and the control address signal (CA), a second voltage domain (e.g., the second voltage domain 502 shown in fig. 5) is provided for the data strobe Signal (DQs), and a third voltage domain (not shown) is provided for the clock signal (CLK).
For example, the first voltage domain may be provided by the first power source 530, the second voltage domain may be provided by the second power source 540, and the third voltage domain may be provided by a third power source (not shown), but the present application is not limited thereto.
By supplying power by dividing the data strobe signal (DQS) and the clock signal (CLK) into different voltage domains, the load current can be further reduced, jitter of the data strobe signal (DQS) and the clock signal (CLK) is reduced, and the margins of the data signal (DQ) and the control address signal (CA) are increased.
It should be noted that the above embodiments use the flowchart shown in fig. 6 to illustrate the steps/operations performed by the method according to the embodiments of the present application. It should be understood that the above steps/operations are not necessarily performed exactly in order, but various steps/operations may be changed in order or processed simultaneously. Meanwhile, other steps/operations may be added to or removed from these steps/operations.
The priority of the steps selected for determining the method can be adjusted accordingly by those skilled in the art according to actual needs, and the present invention is not limited thereto.
Other implementation details of the power supply method of the present embodiment may refer to the embodiments described in fig. 1 to 5, and are not further expanded herein.
The above embodiments of the present invention provide a power supply method, which can effectively reduce jitter of signals, increase signal margins, and enable electronic devices to have higher operating frequency and lower manufacturing cost.
It should be understood that the above-described embodiments are illustrative only. The embodiments described herein may be implemented in hardware, software, firmware, middleware, microcode, or any combination thereof. For a hardware implementation, the processing units may be implemented within one or more Application Specific Integrated Circuits (ASICs), Digital Signal Processors (DSPs), Digital Signal Processing Devices (DSPDs), Programmable Logic Devices (PLDs), Field Programmable Gate Arrays (FPGAs), processors, controllers, micro-controllers, microprocessors, and/or other electronic units designed to perform the functions described herein, or a combination thereof.
Having thus described the basic concept, it will be apparent to those skilled in the art that the foregoing disclosure is by way of example only, and is not intended to limit the present application. Various modifications, improvements and adaptations to the present application may occur to those skilled in the art, although not explicitly described herein. Such modifications, improvements and adaptations are proposed in the present application and thus fall within the spirit and scope of the exemplary embodiments of the present application.
Also, this application uses specific language to describe embodiments of the application. Reference throughout this specification to "one embodiment," "an embodiment," and/or "some embodiments" means that a particular feature, structure, or characteristic described in connection with at least one embodiment of the present application is included in at least one embodiment of the present application. Therefore, it is emphasized and should be appreciated that two or more references to "an embodiment" or "one embodiment" or "an alternative embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, some features, structures, or characteristics of one or more embodiments of the present application may be combined as appropriate.
Computer program code required for the operation of various portions of the present application may be written in any one or more programming languages, including an object oriented programming language such as Java, Scala, Smalltalk, Eiffel, JADE, Emerald, C + +, C #, VB.NET, Python, and the like, a conventional programming language such as C, Visual Basic, Fortran 2003, Perl, COBOL 2002, PHP, ABAP, a dynamic programming language such as Python, Ruby, and Groovy, or other programming languages, and the like. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any network format, such as a Local Area Network (LAN) or a Wide Area Network (WAN), or the connection may be made to an external computer (for example, through the Internet), or in a cloud computing environment, or as a service, such as a software as a service (SaaS).
Additionally, the order in which elements and sequences of the processes described herein are processed, the use of alphanumeric characters, or the use of other designations, is not intended to limit the order of the processes and methods described herein, unless explicitly claimed. While various presently contemplated embodiments of the invention have been discussed in the foregoing disclosure by way of example, it is to be understood that such detail is solely for that purpose and that the appended claims are not limited to the disclosed embodiments, but, on the contrary, are intended to cover all modifications and equivalent arrangements that are within the spirit and scope of the embodiments herein. For example, although the system components described above may be implemented by hardware devices, they may also be implemented by software-only solutions, such as installing the described system on an existing server or mobile device.
Similarly, it should be noted that in the preceding description of embodiments of the application, various features are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure aiding in the understanding of one or more of the embodiments. This method of disclosure, however, is not intended to require more features than are expressly recited in the claims. Indeed, the embodiments may be characterized as having less than all of the features of a single embodiment disclosed above.
Although the present invention has been described with reference to the present specific embodiments, it will be appreciated by those skilled in the art that the above embodiments are merely illustrative of the present invention, and various equivalent changes and substitutions may be made without departing from the spirit of the invention, and therefore, it is intended that all changes and modifications to the above embodiments within the spirit and scope of the present invention be covered by the appended claims.

Claims (10)

1. An electronic device, comprising:
a processor having a first power port, a second power port, and a first signal port, the processor configured to send and receive signals through the first signal port;
a memory having a third power port, a fourth power port, and a second signal port, the memory configured to receive and transmit the signal through the second signal port;
a first power supply configured to provide a first voltage domain, the first power supply connected to the processor through the first power port and connected to the memory through the third power port; and
a second power supply configured to provide a second voltage domain; the second power supply is connected to the processor through the second power supply port and to the memory through the fourth power supply port.
2. The electronic device of claim 1, wherein the signals include a data signal, a control address signal, a data strobe signal, and a clock signal; the first power supply is configured to provide the first voltage domain for the data signals and the control address signals through the first power port and the third power port; the second power supply is configured to provide the second voltage domain for the data strobe signal and the clock signal through the second power port and the fourth power port.
3. The electronic device of claim 1, wherein the first power supply is a dc-converted power supply and the second power supply is a low dropout linear regulator.
4. The electronic device of claim 1, wherein the processor further has a fifth power port, the memory further has a sixth power port, the electronic device further comprising a third power supply connected to the processor through the fifth power port and to the memory through the sixth power port, the signals including a data signal, a control address signal, a data strobe signal, and a clock signal;
wherein the first power supply is configured to provide the first voltage domain for the data signal and the control address signal through the first power port and the third power port, the second power supply is configured to provide the second voltage domain for the data strobe signal through the second power port and the fourth power port, and the third power supply is configured to provide a third voltage domain for the clock signal through the fifth power port and the sixth power port.
5. An electronic device as claimed in claim 2 or 4, wherein the jitter of the data strobe signal is adapted to control the margin of the data signal and the jitter of the clock signal is adapted to control the margin of the control address signal.
6. A power supply method applied to an electronic device, the electronic device including a processor, a memory, a first power supply and a second power supply, the processor having a first power port, a second power port and a first signal port, the memory having a third power port, a fourth power port and a second signal port, the first power supply being connected to the processor through the first power port and to the memory through the third power port, the second power supply being connected to the processor through the second power port and to the memory through the fourth power port, the power supply method comprising the steps of:
transmitting and receiving signals through the first signal port;
receiving and transmitting the signal through the second signal port;
providing a first voltage domain; and
a second voltage domain is provided.
7. The power supply method of claim 6, wherein the signals include a data signal, a control address signal, a data strobe signal, and a clock signal, the power supply method further comprising:
providing the first voltage domain for the data signals and the control address signals; and
the second voltage domain is provided for the data strobe signal and the clock signal.
8. The power supply method of claim 6 wherein the first voltage domain is provided by a DC-converted power supply and the second voltage domain is provided by a low dropout linear regulator.
9. The power supply method of claim 6 wherein the processor further has a fifth power port, the memory further has a sixth power port, the electronic device further comprises a third power supply connected to the processor through the fifth power port and to the memory through the sixth power port, the signals including a data signal, a control address signal, a data strobe signal, and a clock signal, the power supply method further comprising:
providing the first voltage domain for the data signals and the control address signals;
providing the second voltage domain for the data strobe signal; and
a third voltage domain is provided for the clock signal.
10. The power supply method according to claim 7 or 9, wherein the jitter of the data strobe signal is adapted to control the margin of the data signal, and the jitter of the clock signal is adapted to control the margin of the control address signal.
CN201911413854.1A 2019-12-31 2019-12-31 Electronic equipment and power supply method Pending CN111158451A (en)

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