CN111148285A

CN111148285A - Uplink data processing method and device, receiver and storage medium

Info

Publication number: CN111148285A
Application number: CN202010001532.2A
Authority: CN
Inventors: 陈见飞; 阮俊冰; 丁宝国
Original assignee: Comba Telecom Systems China Ltd
Current assignee: Comba Network Systems Co Ltd
Priority date: 2020-01-02
Filing date: 2020-01-02
Publication date: 2020-05-12
Anticipated expiration: 2040-01-02
Also published as: CN111148285B; WO2021136202A1

Abstract

The application provides an uplink data processing method, an uplink data processing device, a receiver and a storage medium, which are used for reducing the situation that decoding fails when the receiver receives uplink data. The method comprises the following steps: receiving uplink data in a first communication mode in a plurality of communication modes; caching the uplink data, and adjusting the time domain position of the uplink data in the first communication mode according to a pre-stored time delay value to obtain the adjusted uplink data; wherein the delay value is used to represent a processing delay of the receiver; and demodulating and decoding the adjusted uplink data.

Description

Uplink data processing method and device, receiver and storage medium

Technical Field

The present application relates to the field of communications technologies, and in particular, to an uplink data processing method, an uplink data processing apparatus, a receiver, and a storage medium.

Background

With the continuous development of communication technology, various communication modes are emerging, such as Narrow band internet of Things (NB-IoT) or Long Term Evolution (LTE).

Different communication modes require corresponding sites to be established, and the communication cost is high. At present, there are receivers capable of supporting multiple communication modes, but due to different communication parameters of different communication modes, such as different sampling rates, the receivers may fail to decode the uplink data of different communication modes when demodulating and decoding.

Disclosure of Invention

The embodiment of the application provides an uplink data processing method, an uplink data processing device, a receiver and a storage medium, which are used for reducing the situation that decoding fails when the receiver receives uplink data.

In a first aspect, a method for processing uplink data is provided, which is applied in a receiver, and includes:

receiving uplink data in a first communication mode in a plurality of communication modes;

caching the uplink data, and adjusting the time domain position of the uplink data according to a pre-stored time delay value to obtain the adjusted uplink data; wherein the delay value is used to represent a processing delay of the receiver;

and demodulating and decoding the adjusted uplink data.

In the embodiment of the application, the uplink data can be successfully demodulated and decoded by adjusting the time domain position of the received uplink data, so that the purpose of receiving the uplink data transmitted in different communication modes is achieved. Compared with the traditional mode that the receiver receives the uplink data of one communication mode, the method and the device have the advantages that the receiver receives the uplink data of different communication modes, the utilization rate of hardware equipment is improved, and the hardware cost is saved. In addition, operators do not need to establish different base stations aiming at different communication modes, and the cost of the operators is saved.

Optionally, after adjusting the time domain position of the uplink data in the first communication mode according to a pre-stored delay value, the method includes:

adjusting the length of the adjusted uplink data to be the data length corresponding to the preset transmission format corresponding to the second communication mode;

wherein the second communication mode belongs to one of the plurality of communication modes.

In the embodiment of the application, a data format of one of the multiple communication modes is adopted as a standard data format, and the receiver can adjust uplink data of other communication modes to the standard data format for transmission, so that the receiver can process, demodulate and decode the uplink data in the same mode, the processing process is simpler and faster, and the working efficiency of the receiver is improved.

Optionally, adjusting the time domain position of the uplink data according to the pre-stored time delay value and according to the pre-stored time delay value, and after obtaining the adjusted uplink data, the method includes:

according to a preset transmission format, filling a start bit in the adjusted uplink data;

determining a jitter offset of the start bit relative to a reference bit in the adjusted uplink data of the first subframe;

and adjusting the time domain position of the adjusted uplink data according to the jitter offset.

In the embodiment of the application, the start bit is filled in the uplink symbol, so that the jitter offset can be determined according to the offset of the start bit relative to the reference bit, the time domain position of the uplink data is adjusted according to the jitter offset, and the influence of jitter on the uplink data is reduced. For uplink data in different communication modes, the occupied bandwidth, sampling rate, or the amount of data contained in one symbol may be different, and therefore, the influence of jitter on the uplink data in different communication modes is also different. For example, the jitter of the uplink data in NB-IoT mode may cause a phase error, thereby affecting the demodulation performance of the receiver on the uplink data. Therefore, in the embodiment of the present application, by adjusting the jitter offset, the possibility of poor performance of demodulating the uplink data is further reduced, thereby reducing the occurrence of the situation that the receiver fails to decode the uplink data.

Optionally, determining a jitter offset of the start bit with respect to a reference bit in the adjusted uplink data of the first subframe includes:

determining the offset of the ith bit of the adjusted uplink data relative to the reference bit as a first offset; wherein i is a positive integer;

and if the first offset is within a first preset range and the ith bit is the start bit, determining the first offset as the jitter offset of the delay of the start bit relative to the reference bit.

In the embodiment of the application, the jitter offset is determined to be in the first preset range, so that the offset condition of the offset uplink data is determined to be the delay, the receiver can adjust the delay offset of the uplink data more specifically, and the accuracy of adjusting the jitter offset of the uplink data is improved. In addition, in the embodiment of the present application, the delay jitter offset of the uplink data is further adjusted, so that a situation that decoding fails due to poor uplink data demodulation performance caused by jitter can be avoided.

if the first offset is not in the first preset range, determining whether the ith bit is in a second preset range; wherein the starting value of the second preset range is greater than the end value of the first preset range;

and if the first offset is within a second preset range and the ith bit is the starting bit, determining the first offset as the jitter offset of the starting bit in advance relative to the reference starting bit.

In the embodiment of the application, the jitter offset is determined to be within the second preset range, and the offset of the offset uplink data is determined to be in advance, so that the receiver can adjust the uplink data more pertinently, and the accuracy of adjusting the offset of the uplink data can be improved. In addition, in the embodiment of the present application, the advance jitter offset of the uplink data is further adjusted, so that a situation that demodulation and decoding of the uplink data fail due to jitter can be avoided.

In a second aspect, a receiver is provided, including:

the radio frequency module is used for receiving uplink data in a first communication mode in multiple communication modes and sending the uplink data to the FPGA module;

the FPGA module is used for receiving the uplink data, caching the uplink data, adjusting the time domain position of the uplink data according to a prestored time delay value, and sending the adjusted uplink data to the DSP module; the time delay value is used for representing the processing time delay of the radio frequency module and the FPGA module;

and the DSP module is used for receiving the adjusted uplink data and demodulating and decoding the adjusted uplink data.

Optionally, the FPGA module is further configured to:

adjusting the length of the adjusted uplink data to be the data length corresponding to the preset transmission format corresponding to the second communication mode; wherein the second communication mode belongs to one of the plurality of communication modes.

Optionally, the FPGA module is further configured to fill a start bit in the adjusted uplink data according to a preset transmission format;

the DSP module is further configured to determine a jitter offset of the start bit with respect to a reference bit in the adjusted uplink data of the first subframe; and adjusting the time domain position of the adjusted uplink data according to the jitter offset.

Optionally, the DSP module is specifically configured to:

and if the first offset is within a first preset range and the ith bit is the starting bit, determining the first offset as the jitter offset of the delay of the starting bit relative to the reference starting bit.

Optionally, the DSP module is specifically configured to:

and if the ith bit is determined to be in a second preset range and the ith bit is the starting bit, determining the first offset as the jitter offset of the starting bit in advance relative to the reference starting bit.

In a third aspect, an uplink data processing apparatus is provided, including:

the receiving module is used for receiving uplink data in a first communication mode in multiple communication modes;

the processing module is used for caching the uplink data, adjusting the time domain position of the uplink data according to a pre-stored time delay value and obtaining the adjusted uplink data; wherein the delay value is used for representing the processing delay of the receiving module and the processing module;

and the demodulation module is used for demodulating and decoding the adjusted uplink data.

In a fourth aspect, there is provided a storage medium having stored thereon computer-executable instructions for causing a computer to perform the method of any of the first aspects.

Drawings

Fig. 1 is a schematic diagram illustrating a case where uplink data is divided into two symbols according to an embodiment of the present application;

fig. 2 is a schematic view of an application scenario of an uplink data processing method according to an embodiment of the present application;

fig. 3 is a schematic structural diagram of a receiver according to an embodiment of the present application;

fig. 4 is a flowchart of an uplink data processing method according to an embodiment of the present application;

fig. 5 is a schematic diagram of an uplink data processing method according to an embodiment of the present application;

fig. 6 is a schematic diagram of another uplink data processing method according to an embodiment of the present application;

fig. 7 is a schematic diagram of an uplink data transmission format in an LTE mode according to an embodiment of the present application;

fig. 8 is a schematic diagram of an NB-IoT mode uplink data transmission format according to an embodiment of the present disclosure;

fig. 9 is a schematic diagram of an adjusted NB-IoT mode uplink data transmission format according to an embodiment of the present disclosure;

FIG. 10 is a diagram illustrating a process for determining jitter offset according to an embodiment of the present application;

fig. 11 is a schematic structural diagram of a receiver according to an embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application.

Hereinafter, some terms in the embodiments of the present application are explained to facilitate understanding by those skilled in the art.

LTE: LTE is a wireless data communication technology standard, and there are two duplex modes, Time Division Duplex (TDD) and Frequency Division Duplex (FDD), mainly used for separating receiving and transmitting channels.

A wireless frame: TDD and FDD have respective frame structures, FDD employs a radio frame, the length of the radio frame is 10ms, each radio frame includes 10 subframes, each subframe includes 2 slots, and each slot includes 7 symbols, that is, one radio frame includes 20 slots and 140 symbols.

In addition, in the embodiments of the present application, "at least one" means one or more, "a plurality" means two or more. "and/or" describes the association relationship of the associated objects, meaning that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone, wherein A and B can be singular or plural. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. "at least one of the following" or similar expressions refer to any combination of these items, including any combination of the singular or plural items. For example, at least one (one) of a, b, or c, may represent: a, b, c, a-b, a-c, b-c, or a-b-c, wherein a, b, c may be single or multiple.

Generally, in an internet of things communication scenario, the internet of things device and other devices do not need to communicate via broadband, and can communicate via an NB-IoT communication mode. The NB-IoT technology has the advantages of strong link, high coverage, low cost, low power consumption, etc., however, the application of the NB-IoT technology needs to depend on network sites, and currently, the number of NB-IoT network sites established by operators is limited, and wide coverage is not available. Moreover, the hardware cost for establishing the NB-IoT sites is relatively high, so that the progress of each large operator in the network construction of the NB-IoT technology is relatively slow, and the application and development of the NB-IoT technology are hindered.

Therefore, at present, the same network device can be used to receive uplink data in multiple communication modes. If the existing network equipment is adopted to receive uplink data sent by different equipment in different communication modes, because the uplink data in different communication modes have different transmission formats, if the uplink data in different communication modes are all demodulated and decoded in the same processing mode, the situation of decoding failure may occur.

For example, the existing LTE technology is already mature, and there are many sites established by operators, so that the coverage is wide. If the hardware device of LTE directly receives the uplink data transmitted in NB-IoT mode, the receiver may fail to decode the uplink data when demodulating and decoding the uplink data.

Specifically, please refer to fig. 1, which is a schematic diagram illustrating a case where uplink data is divided into two symbols. Fig. 1 shows a case where uplink data is divided into two subframes, taking three subframes in a radio frame as an example. In the ideal uplink data, the starting position of the air interface data of the first symbol should be the same as the reference bit of the corresponding subframe. The reference bit is used to characterize the starting position of one subframe.

In the uplink data processed by the hardware, there is a certain time delay between the starting position of the air interface data of the first symbol and the reference bit of the corresponding subframe, as shown in fig. 1, that is, the starting position of the air interface data of the first symbol is not aligned with the reference bit of the corresponding subframe, so that the air interface data of the 14 th symbol in fig. 1 is divided into two subframes, and a decoding failure condition is easily generated in the subsequent demodulation and decoding process using the symbol as a unit.

Specifically, the baseband sampling rate of the LTE technology is different from that of the NB-IoT technology, which may cause uplink data to be split into two adjacent symbols of the radio frame or two symbols in different subframes of the radio frame when the uplink data in the NB-IoT mode is transmitted to the baseband chip, and so on. Therefore, when the receiver demodulates and decodes the uplink data, decoding failure occurs.

In view of this, the present application proposes an uplink data processing method, which is performed by a receiver, and the receiver can be applied in a network device.

The Network device may be a Base Transceiver Station (BTS) in GSM or CDMA, a Base Station (NodeB, NB) in a WCDMA system, an evolved node b (Evo1utiona1NodeB, eNB, or eNodeB) in an LTE system, a wireless controller in a cloud Radio Access Network (C1 output Radio Access Network, CRAN) scenario, or a relay Station, an Access point, a vehicle-mounted device, a wearable device, a Network device in a future 5G Network, a Network device in a future evolved PLMN Network, or the like, which is not limited in the embodiment of the present application.

Fig. 2 is a schematic view of an application scenario of an uplink data processing method according to an embodiment of the present application. The application scenario includes a network device 201 and a terminal device 203. The network device 201 includes a receiver 202, and the receiver 202 is configured to receive, process, and demodulate and decode uplink data sent by other devices. The terminal device 203 includes a first terminal device 203 and a second terminal device 203. The first terminal device 203 is a terminal device 203 that communicates in the first communication mode, for example, an intelligent door lock, an intelligent air conditioner, or an intelligent automobile. The second terminal device 203 is a terminal device 203, such as a mobile phone or a computer, which performs communication in the second communication mode. The first communication mode is, for example, an NB-IoT mode, and the second communication mode is, for example, an LTE or 5G mode.

Specifically, the network device 201 and the first terminal device 203 may communicate with each other in a first communication mode, and the network device and the second terminal device 203 may communicate with each other in a second communication mode.

Based on the application scenario of fig. 2, the structure of the receiver 202 in the embodiment of the present application is described below.

Referring to fig. 3, an example of a structure of a main block in the receiver 202 is shown. The receiver 202 includes a radio frequency module 301, a Field Programmable Gate Array (FPGA) module 302, and a DSP module 303. The radio frequency module 301 is connected with the FPGA module 302, and the FPGA module 302 is connected with the DSP module 303. The Radio frequency module 301 may be implemented by a Remote Radio Unit (RRU). The FPGA module 302 may include three parts, namely a Configurable Logic Block (CLB), an Input/Output Block (IOB), and an Interconnect (Interconnect), and is a programmable device. The DSP module 303 is a microprocessor with data processing capability and high operating speed, and can process a large number of digital signals quickly. The hardware modules in the receiver 202 for implementing the uplink data processing method provided in the present application should be noted that fig. 3 is an example of the hardware structure of the receiver 202, but the hardware structure of the receiver 202 is not limited in practice.

The following takes the application scenario of fig. 2 and the structure of the receiver 202 in fig. 3 as an example to describe the uplink data processing method involved in the embodiment of the present application.

Referring to fig. 4, a flowchart for receiving uplink data specifically includes the following steps:

s41: receiving uplink data in a first communication mode in a plurality of communication modes;

s42: caching uplink data, and adjusting the time domain position of the uplink data according to a pre-stored time delay value to obtain the adjusted uplink data;

s43: and demodulating and decoding the adjusted uplink data.

The general idea in the embodiments of the present application is described below:

the radio frequency module 301 receives uplink data sent from other devices, performs corresponding processing on the received uplink data, and sends the processed uplink data to the FPGA module 302. After receiving the uplink data from the radio frequency module 301, the FPGA module 302 buffers the uplink data, and adjusts the time domain position of the uplink data according to the delay value, where the time domain position of the uplink data may be understood as the time domain position where the uplink data is actually received. The FPGA module 302 sends the adjusted uplink data to the DSP module 303. After receiving the data from the FPGA module 302, the DSP module 303 demodulates and decodes the uplink data. Thus, reception, processing, and demodulation decoding of the uplink data transmitted from the other device by the receiver 202 are completed.

After the general idea of the embodiments of the present application is introduced, specific embodiments of each step will be described in detail below.

S41, receiving uplink data in a first communication mode of the plurality of communication modes.

Specifically, the radio frequency module 301 may receive uplink data in multiple communication modes of the receiver 202, where the multiple communication modes may be LTE, 5G, or NB-IoT communication modes. The following description will be given taking an example where the receiver 202 receives uplink data in a first communication mode, where the first communication mode represents any one of a plurality of communication modes, and the embodiment of the present application does not limit a specific type of the first communication mode. The radio frequency module 301 receives uplink data sent by other devices, such as the terminal device 203.

The receiver 202 processes the received uplink data through the radio frequency module 301, for example, performs analog-to-digital conversion processing and the like. The radio frequency module 301 sends the processed uplink data to the FPGA module 302.

After receiving the uplink data sent by the radio frequency module 301, the FPGA module 302 executes S42, buffers the uplink data, and adjusts the time domain position of the uplink data in the first communication mode according to the pre-stored time delay value, to obtain the adjusted uplink data.

As the radio frequency module 301 and the FPGA module 302 will cause a certain time delay to the uplink data in the process of processing the uplink data, the receiver 202 will have poor demodulation performance in the process of demodulating and decoding the uplink data, thereby causing a situation of decoding failure. Therefore, the FPGA module 302 may adjust the time domain position of the uplink data by buffering the uplink data. After receiving the uplink data from the radio frequency module 301, the FPGA module 302 buffers the uplink data in the FPGA module 302. After the FPGA module 302 buffers the uplink data, the FPGA module 302 may adjust a time domain position of the uplink data according to a pre-stored delay value. There are various methods for obtaining the pre-stored delay value, and the method for obtaining the pre-stored delay value by the FPGA module 302 will be described below.

One way to obtain a pre-stored delay value is to:

the FPGA module 302 may obtain the delay value according to the processing delay when the radio frequency module 301 and the FPGA module 302 process data.

Specifically, in the process that the radio frequency module 301 receives the uplink data and performs corresponding processing, and sends the processed uplink data to the FPGA module 302, and in the process that the FPGA module 302 receives and caches the uplink data, the processing process of the hardware module may cause a certain time delay in the transmission of the uplink data. Since the processes of processing different data of the radio frequency module 301 and the FPGA module 302 are substantially the same, the time delay of uplink data received each time is substantially the same. Therefore, the FPGA module 302 or the test device can determine the delay values of the radio frequency module 301 and the FPGA module 302 through a process of receiving the uplink data of the test. The FPGA module 302 or the testing device may store the pre-calculated delay value in the FPGA module 302, which is equivalent to the FPGA module 302 obtaining the pre-stored delay value.

After the FPGA module 302 obtains the pre-stored time delay value, the time domain position of the uplink data in the buffer memory may be adjusted according to the pre-stored time delay value. There are many methods for adjusting the time domain position of the buffered uplink data by the FPGA module 302, and two of the methods are described below as examples.

The first adjusting method comprises the following steps:

according to the pre-stored time delay value, the FPGA module 302 generates a digital sequence, and inserts the digital sequence into the uplink data to adjust the time domain position of the uplink data.

Specifically, the FPGA module 302 generates a digital sequence with a corresponding length according to a pre-stored delay value, and inserts the digital sequence into the start position/end position of the uplink data in the buffer, so as to offset the transmission delay of the uplink data. The number sequence may be a predetermined fixed number composition, such as all 0's or all 1's, etc., or may be a generated random number, without limitation.

In one possible embodiment, the FPGA module 302 determines the length of the digital sequence based on its own processing data rate and delay value.

Specifically, the length of the digital sequence is positively correlated with the absolute value of the delay value, that is, the larger the absolute value of the delay value is, the larger the delay value to be compensated is, so that the FPGA module 302 may multiply the processing rate of itself by the delay value to obtain the length of the digital sequence to be inserted.

It relates to how to determine the start or end position of the upstream data in which the digital sequence is inserted into the buffer.

Specifically, the FPGA module 302 may determine the delay state of the uplink data. The delay status is used to indicate whether the uplink data is delayed or advanced. If the uplink data is advanced, inserting the digital sequence into the initial position of the uplink data, and if the uplink data is delayed, inserting the digital sequence into the end position of the uplink data.

For example, please refer to fig. 5, which is a diagram illustrating adjusting a delay value of uplink data. If the predetermined number sequence is a number sequence of all 0 s, according to the pre-stored delay value, if the uplink data is delayed, the number sequence "0000" needs to be inserted at the end position of the uplink data "123456" to achieve the purpose of adjusting the uplink data and offsetting the transmission delay of the uplink data.

And a second adjusting method:

according to the pre-stored time delay value, the FPGA module 302 adjusts the start pointer for indicating the start position of the subframe to the actual start position of the uplink data in the buffer, so as to adjust the time domain position of the uplink data.

Specifically, according to the pre-stored delay value, the FPGA module 302 adjusts a start pointer for indicating the start position of the subframe to the actual start position of the uplink data, so as to adjust the time domain position of the uplink data, so as to eliminate the reception delay of the uplink data caused by the radio frequency module 301 and the FPGA module 302.

For example, please refer to fig. 6, which is a schematic diagram illustrating another method for adjusting uplink data. The FPGA module 302 is configured to indicate that a start pointer of a position where a subframe starts is not aligned with a position where the uplink data actually starts. The FPGA module 302 adjusts the start pointer to the position where the data of the uplink data "123456" starts to be "1" according to the pre-stored delay value, so as to achieve the purpose of adjusting the uplink data and eliminating the transmission delay of the uplink data.

In a possible embodiment, after adjusting the time domain position of the uplink data according to the pre-stored delay value, the FPGA module 302 may adjust the transmission format of the adjusted uplink data according to a preset transmission format. The transmission format may include, for example, a data length of one symbol in the uplink data, and/or a flag bit for characterizing the uplink data, for example, a start bit for characterizing a start position of the uplink data, and the like.

The following describes a process of the FPGA module 302 adjusting the transmission format of the uplink data.

As an embodiment, for different communication modes, the preset transmission format may be a transmission format corresponding to a current communication mode; alternatively, the preset transmission format may be a preset transmission format for different communication modes, and is not limited in particular.

Specifically, for different communication modes, the receiver 202 may receive, process, demodulate and decode the uplink data by using the transmission format corresponding to the current communication mode, and the receiver 202 may directly invoke the hardware device corresponding to the current communication mode to process the uplink data without performing additional adjustment on the uplink data;

alternatively, for different communication modes, the receiver 202 may receive, process, demodulate and decode the uplink data according to the same preset transmission format, where the preset transmission format may be a transmission format corresponding to any one of the multiple communication modes. The receiver 202 correspondingly adjusts the uplink data transmitted in multiple communication modes, so that the adjusted uplink data can satisfy a preset transmission format. The receiver 202 may also adjust other than the communication mode corresponding to the preset one transmission format, that is, only adjust the communication mode other than the communication mode.

Specifically, the FPGA module 302 adds a start bit to the uplink data to determine a start position of the effective data in the adjusted uplink data. And adding an end bit for the uplink data after the time domain position is adjusted, wherein the end bit is used for determining the end position of the effective data in the adjusted uplink data. Alternatively, other flag bits may be added, and are not particularly limited.

In one possible embodiment, after adding the start bit, the end bit, or other flag bit, the uplink data transmitted in the first communication mode may be supplemented with the data length according to a preset transmission format.

The following describes an example of the process of the FPGA module 302 adjusting the transmission format of the uplink data, where the first communication mode is an NB-IoT mode, and the transmission format of the uplink data transmitted in the second communication mode is a preset transmission format, and the second communication mode is an LTE mode.

First, a transmission format of uplink data transmitted in an LTE mode and a transmission format of uplink data transmitted in an NB-IoT mode are described.

Please refer to fig. 7, which is a schematic diagram of an uplink data transmission format in LTE mode. The transmission format of uplink data in FDD mode of LTE may be described by taking a radio frame as an example. One symbol of a radio frame includes a Cyclic Prefix (CP) and a packet. The CP of the first symbol in one subframe includes 160 air interface data, and the CPs of the remaining symbols include 144 air interface data. The data packet of each symbol in one subframe includes 2048 air interface data.

Please refer to fig. 8, which is a schematic diagram of an NB-IoT mode uplink data transmission format. The NB-IoT mode uplink data transmission format may be described by taking one radio frame as an example. One symbol of the radio frame includes a cyclic prefix CP and a data packet. The CP of the first symbol in one subframe includes 10 air interface data, and the CPs of the other symbols include 9 air interface data. The data packet of each symbol in one subframe includes 128 air interface data.

Second, a process of adjusting uplink data transmitted in the NB-IoT mode according to a transmission format of the uplink data transmitted in the LTE mode may be described as follows.

Please refer to fig. 9, which is a diagram illustrating an adjusted NB-IoT mode of uplink data transmission format. Taking the first symbol in the radio frame as an example, the uplink data transmission format in the LTE mode includes a CP with 160 air interface data and a data packet with 2048 air interface data. The FPGA module 302 may add flag bits to the NB-IoT mode upstream data, for example, add 1 start bit before the first bit of the NB-IoT mode upstream data and 1 end bit after the last bit of the NB-IoT mode upstream data. The NB-IoT mode uplink data to which the flag bit is added includes 1 start bit, 1 end bit, cyclic prefixes of 10 air interface data, and data packets of 128 air interface data. According to the transmission format of the uplink data in the LTE mode, 2068 pieces of air interface data are also needed to be supplemented to the uplink data in the NB-IoT mode. The supplementary air interface data may be pre-agreed data, such as all 0 s or all 1 s, or may be other data, such as random data, and the like, without limitation.

After the buffered uplink data in the first communication mode is adjusted according to the transmission format of the second communication mode, the FPGA module 302 sends the adjusted uplink data to the DSP module 303.

The FPGA module 302 adds a reference bit to the adjusted start position of the uplink data, and may generate a left-right offset due to jitter during the transmission of the uplink data. The jitter offset has little influence on the uplink data in the LTE transmission mode and can be ignored. For the NB-IoT mode uplink data, since the NB-IoT mode transmission occupies a small bandwidth and has a low sampling rate, and a symbol of a radio frame includes relatively less data, the NB-IoT mode transmission is susceptible to jitter offset during the uplink data transmission process, and the jitter offset may cause failure in decoding the uplink data by the subsequent DSP module 303.

In a possible embodiment, before the DSP module 303 performs S43 to demodulate and decode the adjusted uplink data, the DSP module 303 may further adjust the received adjusted uplink data to further reduce the decoding failure of the uplink data due to jitter.

Specifically, after the DSP module 303 receives the uplink data from the FPGA module 302, the jitter offset of the uplink data may be determined. The DSP module 303 further adjusts the uplink data according to the jitter offset.

The following describes a process of determining the jitter offset of the uplink data by the DSP module 303.

The DSP module 303 determines an offset of the start bit of the upstream data with respect to the reference bit as a jitter offset of the upstream data. The time domain position of the uplink data is adjusted according to the jitter offset, and the specific adjustment method may refer to the adjustment methods listed above, which are not described herein again.

Specifically, when receiving the uplink data, the DSP module 303 determines whether the subframe is a frame header of a radio frame after receiving the uplink data of the subframe, that is, determines whether the subframe is a first subframe of a radio frame. If the sub-frame is a frame header of a radio frame, the position of the start bit in the first symbol in the sub-frame is determined.

If the offset of the determined start bit relative to the reference bit is within a first preset range, the uplink data is shown to be delayed, and if the offset of the determined start bit relative to the reference bit is within a second preset range, the uplink data is shown to be advanced. The first preset range and the second preset range may be value ranges of two offsets preset according to an empirical value, or may be value ranges of the two offsets determined in other manners, which is not limited specifically. The first preset range and the second preset range may be two adjacent value ranges, or may be two non-adjacent value ranges, and are not limited specifically. The starting value of the second preset range is greater than the end value of the first preset range, that is, each value in the second preset range is greater than each value in the first preset range.

In a possible embodiment, in a first symbol of a first subframe of a radio frame, the DSP module 303 starts to determine from a first data over the air interface, and determines whether the data over the air interface is a start bit. The offset of the current air interface data relative to the reference bit is determined as a first offset, and if the air interface data is not the start bit, the second air interface data is determined until the DSP module 303 determines that the ith air interface data is the start bit before the end value of the second preset range. And determining a first offset of the ith air interface data relative to the reference bit as a jitter offset.

Or until the end value of the second preset range is reached, the DSP module 303 does not determine such an i value, which indicates that the position of the start bit in the symbol is not within the first preset range or the second preset range, the uplink data offset is too large, and is the unadjustable uplink data, and a corresponding prompt is given, where the prompting mode may be an audio prompt or a text prompt, and a specific prompting mode is not limited.

Specifically, if an i value is determined before the end value of the second preset range, the i value may be within the first preset range, and at this time, the first offset is a delay amount; alternatively, the first offset may be within a second preset range, where the first offset is an advance. The DSP module 303 may further determine the range within which the value of i lies.

The DSP module 303 determines whether the value of i is within a first predetermined range. If the value of i is within the first preset range, the DSP module 303 determines the first offset i as a jitter offset of the uplink data, which indicates that the uplink data is delayed.

If the value of i is not within the first predetermined range, the DSP module 303 determines if the value of i is within a second predetermined range. If the value of i is within the second preset range, the DSP module 303 determines the first offset i as the jitter offset of the uplink data, indicating that the uplink data is advanced.

Taking a first symbol in a radio frame of uplink data transmitted in an NB-IoT mode to include 138 air interface data, taking a first preset range as 1-64 and a second preset range as 65-130 as an example, a process of determining a jitter offset is described, please refer to fig. 10, which is a flowchart for determining a jitter offset, and the following describes, with reference to fig. 10, an example of a process for determining a jitter offset according to an embodiment of the present application:

s1001, determining uplink data of a first subframe in the uplink data.

The DSP module 303 determines the jitter offset of the uplink data according to the jitter offset of the uplink data of the first subframe.

And S1002, determining whether a first offset of the i-th bit air interface data relative to the reference bit is within a first preset range.

And i starts to take a value from 1, and judges whether the first offset of the 1 st air interface data relative to the reference bit is within a first preset range of 1-64. Wherein the first offset is the value 1 of i.

If the DSP module 303 determines that the first offset of the i-th bit over-the-air data with respect to the reference bit is within the first preset range, the DSP module 303 executes S1003 to determine whether the i-th bit over-the-air data is the start bit. The DSP module 303 determines whether the 1 st bit of air interface data is the start bit of the addition. If the 1 st bit of air interface data is the start bit, the DSP module 303 performs S1004 to determine the first offset as a jitter offset delayed with respect to the reference bit. If the 1 st bit air interface data is not the start bit, the DSP module 303 executes S1002 to determine whether the first offset of the 2 nd bit air interface data with respect to the reference bit is within the first preset range. The DSP module 303 increments i by 1 and re-executes S1002.

If the DSP module 303 determines that the first offset of the i-th bit air interface data with respect to the reference bit is not within the first preset range, the DSP module 303 executes S1005 to determine whether the first offset of the i-th bit air interface data with respect to the reference bit is within a second preset range. If the DSP module 303 determines that the first offset of the 66 th bit air interface data with respect to the reference bit is not within the first preset range 1-64, it determines whether the first offset of the 66 th bit air interface data with respect to the reference bit is within the second preset range 65-130.

If the DSP module 303 determines that the first offset of the i-th bit air interface data with respect to the reference bit is within the second preset range, the DSP module 303 executes S1006 to determine whether the i-th bit air interface data is the start bit. The DSP module 303 determines whether the 66 th air interface data is the start bit of the add.

If the 66 th bit of air interface data is the start bit, the DSP module 303 executes S1007 to determine the first offset as a jitter offset advanced with respect to the reference bit. If the 66 th bit of air interface data is not the start bit, the DSP module 303 executes S1005 to determine whether the first offset of the 67 th bit of air interface data with respect to the reference bit is within the second preset range. The DSP module 303 increments i by 1 and re-executes S1005.

If the DSP module 303 determines that the first offset of the i-th bit air interface data with respect to the reference bit is not within the second preset range, the DSP module 303 executes S1008 to determine that the jitter offset of the uplink data is 0. The DSP module 303 determines that the first offset of the 132 th bit air interface data with respect to the reference bit is not within the second preset range 65-130, and then the DSP module 303 determines that the jitter offset of the uplink data is 0.

After the DSP module 303 adjusts the uplink data, the DSP module 303 executes S43 to demodulate and decode the adjusted uplink data. The demodulation and decoding process of the DSP module 303 further includes Fast Fourier Transform (FFT), equalization processing, and the like, and is not limited specifically.

Based on the same inventive concept, embodiments of the present application provide a receiver, which can implement the functions corresponding to the uplink data processing methods discussed above. The receiver corresponds to a part of the network device discussed above, and with continued reference to fig. 3, the receiver includes a radio frequency module 301, an FPGA module 302, and a DSP module 303. Wherein:

the radio frequency module 301 is configured to receive uplink data in a first communication mode of multiple communication modes, and send the uplink data in the first communication mode to the field programmable gate array FPGA module 302;

the FPGA module 302 is configured to receive uplink data in the first communication mode, buffer the uplink data in the first communication mode, adjust a time domain position of the uplink data in the first communication mode according to a pre-stored delay value, and send the adjusted uplink data to the digital signal processing DSP module 303; the time delay value is used for representing the processing time delay of the radio frequency module 301 and the FPGA module 302;

the DSP module 303 is configured to receive the adjusted uplink data, and demodulate and decode the adjusted uplink data.

In one possible embodiment, the FPGA module 302 is further configured to:

adjusting the length of the adjusted uplink data to be the data length corresponding to the preset transmission format corresponding to the second communication mode; wherein the second communication mode belongs to one of a plurality of communication modes.

In a possible embodiment, the FPGA module 302 is further configured to fill a start bit in the adjusted uplink data according to a preset transmission format;

the DSP module 303 is further configured to: determining the jitter offset of the initial bit relative to the reference bit in the adjusted uplink data of the first subframe;

In a possible embodiment, the DSP module 303 is specifically configured to:

if the first offset is within a first preset range and the ith bit is the start bit, determining the first offset as the jitter offset of the delay of the start bit relative to the reference start bit.

In a possible embodiment, the DSP module 303 is specifically configured to:

if the first offset is not in the first preset range, determining whether the ith bit is in a second preset range; wherein the starting value of the second preset range is larger than the end value of the first preset range;

if the first offset is within a second preset range and the ith bit is the start bit, determining the first offset as the jitter offset of the start bit advanced relative to the reference start bit.

Based on the same inventive concept, the present application further provides a receiver, which is equivalent to the receiver discussed above, please refer to fig. 11, and the receiver includes a receiving module 1101, a processing module 1102, and a demodulating module 1103, where:

a receiving module 1101, configured to receive uplink data in a first communication mode of multiple communication modes;

the processing module 1102 is configured to cache uplink data, and adjust a time domain position of the uplink data according to a pre-stored delay value, to obtain adjusted uplink data; wherein the delay value is used to represent the processing delay of the receiver 202;

a demodulation module 1103, configured to demodulate and decode the adjusted uplink data.

In a possible embodiment, the processing module 1102 is further configured to:

according to a preset transmission format, filling initial bits in the adjusted uplink data;

determining the jitter offset of the initial bit relative to the reference bit in the adjusted uplink data of the first subframe;

In a possible embodiment, the processing module 1102 is specifically configured to:

As an example, the processing module 1102 in fig. 11 may implement the functions of the FPGA module 302 and the DSP module 303 in fig. 3 discussed earlier. The transceiver module 1101 in fig. 11 may implement the functions of the rf module 301 in fig. 3.

Based on the same inventive concept, embodiments of the present application further provide a storage medium storing computer instructions, which, when executed on a computer, cause the computer to perform the uplink data processing method discussed above.

In some possible embodiments, the aspects of the upstream data processing method provided by the present application may also be implemented in the form of a program product, which includes program code for causing an apparatus to perform the steps of the upstream data processing method according to various exemplary embodiments of the present application described above in this specification, when the program product is run on the apparatus.

As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

While the preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all alterations and modifications as fall within the scope of the application.

It will be apparent to those skilled in the art that various changes and modifications may be made in the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. Thus, if such modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to encompass such modifications and variations.

Claims

1. An uplink data processing method applied to a receiver, the method comprising:

and demodulating and decoding the adjusted uplink data.

2. The method as claimed in claim 1, wherein after adjusting the time domain position of the uplink data according to the pre-stored delay value, the method comprises:

3. The method according to claim 1, after adjusting the time domain position of the uplink data according to a pre-stored delay value to obtain the adjusted uplink data, comprising:

4. The method as claimed in claim 3, wherein determining the jitter offset of the start bit with respect to the reference bit in the adjusted uplink data of the first subframe comprises:

5. The method as claimed in claim 3 or 4, wherein determining the jitter offset of the start bit with respect to the reference bit in the adjusted uplink data of the first subframe comprises:

and if the first offset is within a second preset range and the ith bit is the starting bit, determining the first offset as the jitter offset of the starting bit relative to the reference bit in advance.

6. A receiver, comprising:

7. The receiver of claim 6, wherein the FPGA module is further configured to:

8. The receiver of claim 6,

the FPGA module is further used for filling a start bit in the adjusted uplink data according to a preset transmission format;

9. The receiver of claim 8, wherein the DSP module is specifically configured to:

and if the first offset is within a first preset range and the ith bit is the starting bit, determining the first offset as the jitter offset of the delay of the starting mark bit relative to the reference bit.

10. The receiver according to claim 8 or 9, wherein the DSP module is specifically configured to:

and if the ith bit is determined to be in a second preset range and the ith bit is the starting bit, determining the first offset as the jitter offset of the starting bit in advance relative to the reference bit.

11. An upstream data processing apparatus, comprising:

the processing module is used for caching the uplink data, adjusting the time domain position of the uplink data according to a pre-stored time delay value and obtaining the adjusted uplink data; wherein the delay value is used to represent a processing delay of the receiver;

12. A computer-readable storage medium having stored thereon computer instructions which, when executed on a computer, cause the computer to perform the method of any one of claims 1-5.