CN111147776A - Pixel unit circuit detection device and method - Google Patents
Pixel unit circuit detection device and method Download PDFInfo
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- CN111147776A CN111147776A CN202010008111.2A CN202010008111A CN111147776A CN 111147776 A CN111147776 A CN 111147776A CN 202010008111 A CN202010008111 A CN 202010008111A CN 111147776 A CN111147776 A CN 111147776A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N17/00—Diagnosis, testing or measuring for television systems or their details
- H04N17/002—Diagnosis, testing or measuring for television systems or their details for television cameras
Abstract
The application provides a pixel unit circuit detection device and a method, which relate to the field of sensors, and the pixel unit circuit detection device comprises: the device comprises a variable voltage input end, a photodiode, an input end switch, a first modulation switch and a second modulation switch; one end of the input end switch is connected with the variable voltage input end, the other end of the input end switch is respectively connected with one end of the first modulation switch, one end of the second modulation switch and the output end of the photodiode, the input end of the photodiode is grounded, and the signal input of the input end switch, the first modulation switch and the second modulation switch is controlled by the same clock control circuit; the other end of the first modulation switch is connected to the first output end through a first reset circuit, and the other end of the second modulation switch is connected to the second output end through a second reset circuit. The input signal is ensured to be synchronous with the signal corresponding to one modulation switch, and the accuracy and the reliability of measurement are improved.
Description
Technical Field
The present disclosure relates to the field of sensors, and more particularly, to a pixel unit circuit detection apparatus and method.
Background
A Complementary Metal-Oxide-Semiconductor (CMOS) image sensor is a sensor in the field of image processing, and can be applied to terminal devices such as computers, vehicles and mobile phones, and also can be applied to professional photographic devices or devices that need to process images.
The existing CMOS image sensor measures the modulation and demodulation contrast by using a laser to perform a light injection test, that is, by injecting external laser into the CMOS image sensor, wherein the modulation and demodulation contrast is a result of comparing electrons collected by a first tap end with electrons collected by a second tap end within the same period of time.
However, in the existing mode of light injection, because the laser is not directly connected with the processing chip of the CMOS image sensor, it is difficult to control the input signal to be synchronous with the signal of one of the Tap ends, and in the using process, the waveform of the control signal of the laser is difficult to be completely consistent with the signal of any one of the Tap ends, thereby causing the inaccurate measurement result.
Disclosure of Invention
The present disclosure is directed to a pixel unit circuit detecting device and method for controlling an input signal to be synchronous with a signal of one of tap terminals, so as to improve measurement accuracy and reliability.
In order to achieve the purpose, the technical scheme adopted by the application is as follows:
in a first aspect, the present application provides a pixel unit circuit detection device, including:
the device comprises a variable voltage input end, a photodiode, an input end switch, a first modulation switch and a second modulation switch;
one end of the input end switch is connected with the variable voltage input end, the other end of the input end switch is respectively connected with one end of the first modulation switch, one end of the second modulation switch and the output end of the photodiode, the input end of the photodiode is grounded, and the signal input of the input end switch, the first modulation switch and the second modulation switch is controlled by the same clock control circuit;
the other end of the first modulation switch is connected to the first output end through a first reset circuit, and the other end of the second modulation switch is connected to the second output end through a second reset circuit.
Optionally, after the photodiode is reset, the amount of electrons is 0, gates of the input switch, the first modulation switch and the second modulation switch are all biased to a low-level off state, and the variable voltage input terminal is in a low-level state;
after the input end switch and the first modulation switch are simultaneously turned on, electrons are input into the photodiode through the variable voltage input end, and when a grid signal of the first modulation switch is at a high level and a grid signal of the second modulation switch is at a low level, the first modulation switch collects the electrons.
Optionally, when the gate signal of the second modulation switch is at a high level and the gate signal of the first modulation switch is at a low level, the second modulation switch collects electrons.
Optionally, the first reset circuit comprises: the power supply comprises a first capacitor, a first reset switch, a first source electrode following MOS tube and a first power interface; the other end of the first modulation switch and one end of the first capacitor are connected with one end of the first reset switch; the other end of the first reset switch and one end of the first source-follower MOS transistor, which is not a gate, are connected to the first power interface, the gate terminal of the first source-follower MOS transistor is connected to one end of the first reset switch, the other end of the first modulation switch, and one end of the first capacitor, respectively, and the other end of the first source-follower MOS transistor, which is not a gate, is connected to a first output terminal;
the second reset circuit includes: the second capacitor, the second reset switch, the second source electrode following MOS tube and the second power interface; the other two ends of the second modulation switch and one end of the second capacitor are connected with one end of the second reset switch; the other end of the second reset switch and one end of the second source electrode following MOS tube non-grid electrode are connected with the second power supply interface, the grid electrode end of the second source electrode following MOS tube is respectively connected with one end of the second reset switch, the other end of the second modulation switch and one end of the second capacitor, and the other end of the second source electrode following MOS tube non-grid electrode is used for being connected with a second output end.
In a second aspect, the present application also provides a pixel unit circuit detection method, which is applied to the pixel unit circuit detection apparatus provided in the first aspect, and the method includes:
receiving switch control signals of a clock control circuit to the input end switch, the first modulation switch and the second modulation switch;
controlling the states of the input end switch, the first modulation switch and the second modulation switch according to the switch control signal, so that electrons are input into the photodiode from the variable voltage input end;
and respectively acquiring output data of the first output end and the second output end based on the electrons collected by the photodiode.
Optionally, after the photodiode is reset, the amount of electrons is 0, gates of the input switch, the first modulation switch and the second modulation switch are all biased to a low-level off state, and the variable voltage input terminal is in a low-level state;
the controlling the states of the input switch, the first modulation switch and the second modulation switch according to the switch control signal to enable electrons to be input into the photodiode through the variable voltage input end comprises:
after the photodiode is reset, the input end switch and the first modulation switch are controlled to be simultaneously turned on according to the switch control signal, electrons are input into the photodiode through the variable voltage input end, and when a grid signal of the first modulation switch is at a high level and a grid signal of the second modulation switch is at a low level, the first modulation switch collects the electrons.
Optionally, when the gate signal of the second modulation switch is at a high level and the gate signal of the first modulation switch is at a low level, the second modulation switch collects electrons.
Optionally, the first reset circuit comprises: the power supply comprises a first capacitor, a first reset switch, a first source electrode following MOS tube and a first power interface; the other end of the first modulation switch and one end of the first capacitor are connected with one end of the first reset switch; the other end of the first reset switch and one end of the first source-follower MOS transistor, which is not a gate, are connected to the first power interface, the gate terminal of the first source-follower MOS transistor is connected to one end of the first reset switch, the other end of the first modulation switch, and one end of the first capacitor, respectively, and the other end of the first source-follower MOS transistor, which is not a gate, is connected to a first output terminal;
the second reset circuit includes: the second capacitor, the second reset switch, the second source electrode following MOS tube and the second power interface; the other two ends of the second modulation switch and one end of the second capacitor are connected with one end of the second reset switch; the other end of the second reset switch and one end of the second source electrode following MOS tube non-grid electrode are connected with the second power supply interface, the grid electrode end of the second source electrode following MOS tube is respectively connected with one end of the second reset switch, the other end of the second modulation switch and one end of the second capacitor, and the other end of the second source electrode following MOS tube non-grid electrode is used for being connected with a second output end.
Optionally, before receiving the switch control signals of the clock control circuit to the input switch, the first modulation switch, and the second modulation switch, the method further includes:
and biasing the first power interface, the second power interface and the variable voltage input end to high level, and biasing the input end switch, the first modulation switch and the second modulation switch to high level until the electrons in the photodiode are discharged to complete resetting.
Optionally, the method further comprises:
a first selection switch and a second selection switch;
the other end of the first source electrode following MOS tube non-grid electrode is connected with one end of the first selection switch, and the other end of the first selection switch is connected with the first output end;
the other end of the second source electrode following MOS tube non-grid electrode is connected with one end of the second selection switch, and the other end of the second selection switch is connected with the first output end.
Compared with the prior art, the method has the following beneficial effects:
the pixel unit circuit detection device provided in the embodiment of the present application includes: the device comprises a variable voltage input end, a photodiode, an input end switch, a first modulation switch and a second modulation switch; one end of the input end switch is connected with the variable voltage input end, the other end of the input end switch is respectively connected with one end of the first modulation switch, one end of the second modulation switch and the output end of the photodiode, the input end of the photodiode is grounded, the input end switch, the first modulation switch and the second modulation switch are controlled by the same clock control circuit, the other end of the first modulation switch is connected to the first output end through the first reset circuit, and the other end of the second modulation switch is connected to the second output end through the second reset circuit. The charge is injected by setting the variable voltage input end, and the signal input of the input end switch, the first modulation switch and the second modulation switch is controlled by the same clock control circuit, so that the synchronization of the input signal and the signal corresponding to one modulation switch is ensured, and the accuracy and the reliability of measurement are improved.
Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the application. The objectives and other advantages of the application may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
In order to more clearly explain the technical solutions of the present application, the drawings needed for the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and that those skilled in the art can also derive other related drawings from these drawings without inventive effort.
Fig. 1 is a schematic structural diagram of a pixel unit circuit detection device according to an embodiment of the present disclosure;
FIG. 2 is a schematic structural diagram of a pixel unit circuit detection device according to another embodiment of the present disclosure;
FIG. 3 is a schematic structural diagram of a pixel unit circuit detection device according to another embodiment of the present disclosure;
FIG. 4 is a timing diagram illustrating a control of a pixel unit circuit detecting device according to an embodiment of the present disclosure;
fig. 5 is a schematic flow chart of a pixel unit circuit detection method according to an embodiment of the present disclosure.
Detailed Description
The technical solutions in the present application will be clearly and completely described below with reference to the drawings attached to the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
The embodiment of the application aims at the problems that in the prior art, a laser emission waveform is matched with a tap end signal in an external laser injection mode, and then a modulation and demodulation contrast ratio is obtained by utilizing a difference value of two tap ends, but in practice, a measuring result is inaccurate due to the fact that a laser emitter and a tap end signal are not 100% matched. The pixel unit circuit detection device may be integrated in an image sensor, a laser radar, and the like, and is not particularly limited herein.
Fig. 1 is a schematic structural diagram of a pixel unit circuit detection device according to an embodiment of the present application, and as shown in fig. 1, the pixel unit circuit detection device includes: a variable voltage input terminal vdd 01, a photodiode 02, an input terminal switch 03, a first modulation switch 04, and a second modulation switch 05.
One end of the input terminal switch 03 is connected to the variable voltage input terminal vdd 01, and the other end of the input terminal switch 03 is connected to one end of the first modulation switch 04, one end of the second modulation switch 05, and the output terminal of the photodiode 02.
The input of the photodiode 02 is connected to ground.
The signal inputs of the input end switch 03, the first modulation switch 04 and the second modulation switch 05 are controlled by the same clock control circuit. The clock control circuit may be an external circuit, or may be integrated in the pixel unit circuit detection device, which is not limited in this application.
The clock control circuit controls at least one of the first modulation switch 04 and the second modulation switch 05 to be synchronized with the signal of the input terminal switch 03.
The other end of the first modulation switch 04 is connected to the first output terminal VOUT1 through the first reset circuit 06, and the other end of the second modulation switch 05 is connected to the second output terminal VOUT2 through the second reset circuit 07.
In the process of demodulating the contrast, the pixel unit circuit detection apparatus compares the electrons collected by the first modulation switch 04 (i.e., tap1) and the second modulation switch 05 (i.e., tap2) in the same time period, and may specifically perform a comparison operation with other physical parameters such as charge or voltage of the physical quantity related to the accumulation of electrons, so as to obtain the modem contrast as a result.
In a specific implementation process, the variable voltage input terminal vdd 01 may store certain electrons, and after the input terminal switch 03 is turned on, the electrons may be injected into the photodiode 02. After the first modulation switch 04 is turned on, the first modulation switch 04 collects electrons; after the second modulation switch 05 is turned on, the second modulation switch 05 collects electrons. And finally, acquiring the voltage V1 of the first output end and the voltage V2 of the second output end, and calculating and acquiring the modulation and demodulation contrast according to V1 and V2.
The pixel unit circuit detection device provided in the embodiment of the present application includes: the device comprises a variable voltage input end, a photodiode, an input end switch, a first modulation switch and a second modulation switch; one end of the input end switch is connected with the variable voltage input end, the other end of the input end switch is respectively connected with one end of the first modulation switch, one end of the second modulation switch and the output end of the photodiode, and the input end of the photodiode is grounded, wherein the signal input of the variable voltage input end, the first modulation switch and the second modulation switch is controlled by the same clock control circuit, the other end of the first modulation switch is connected to the first output end through the first reset circuit, and the other end of the second modulation switch is connected to the second output end through the second reset circuit. The charge is injected by setting the variable voltage input end, and the signal input of the input end switch, the first modulation switch and the second modulation switch is controlled by the same clock control circuit, so that the synchronization of an input signal and a signal corresponding to one modulation switch is ensured, the accuracy and the reliability of measurement are improved, the clock circuit is integrated in the whole detection circuit, the high efficiency of the circuit on time control is ensured, and the reliability of signal control is ensured by the unified control of the other clock circuit.
Alternatively, the photodiode 02 has an electron amount of 0 after reset, the gates of the input terminal switch 03, the first modulation switch 04, and the second modulation switch 05 are all biased to a low-level off state, and the variable voltage input terminal vdd 01 is also in a low-level state.
In this embodiment, taking clock synchronization between the input switch 03 and the first modulation switch 04 as an example:
when the input switch 03 and the first modulation switch 04 are controlled to be turned on simultaneously according to the same clock control circuit, electrons are input to the photodiode 02 from the variable voltage input vdd 01. And when the grid signal of the first modulation switch 04 is at a high level and the grid signal of the second modulation switch 05 is at a low level, the first modulation switch 04 collects electrons.
Accordingly, when the gate signal of the second modulation switch 05 is at a high level and the gate signal of the first modulation switch 04 is at a low level, the second modulation switch 05 collects electrons.
It should be noted that, the switches in the embodiments of the present application, such as the input switch, the first modulation switch, the second modulation switch, and the like, may be implemented by MOS transistors, but are not limited thereto. The control signal of the clock control circuit can be input by the grid electrode of the MOS tube.
Fig. 2 is a schematic structural diagram of a pixel unit circuit detection device according to another embodiment of the present application, and as shown in fig. 2, on the basis of fig. 1, in the above device, the first reset circuit 06 includes: the first capacitor 601, the first reset switch 602, the first source follower MOS 603, and the first power interface VDD1, and the design of the reset switch enables the whole circuit to achieve the effect of real-time recovery.
The other end of the first modulation switch 04 and one end of the first capacitor 601 are connected with one end of the first reset switch 602; the other end of the first reset switch 602 and one end of the non-gate of the first source follower MOS transistor 603 are connected to the first power interface VDD1, the gate end of the first source follower MOS transistor 603 is connected to one end of the first reset switch 602, the other end of the first modulation switch 04, and one end of the first capacitor 601, respectively, and the other end of the non-gate of the first source follower MOS transistor 603 is used for connecting to the first output terminal.
Similarly, the second reset circuit 07 includes: a second capacitor 701, a second reset switch 702, a second source follower MOS transistor 703, and a second power interface VDD 2.
The other end of the second modulation switch 05 and one end of the second capacitor 701 are connected with one end of the second reset switch 702; the other end of the second reset switch 702 and one end of the non-gate of the second source follower MOS transistor 703 are connected to the second power interface VDD2, the gate end of the second source follower MOS transistor 703 is connected to one end of the second reset switch 702, the other end of the second modulation switch 05 and one end of the second capacitor 701, respectively, and the other end of the non-gate of the second source follower MOS transistor 703 is used for connecting to the second output terminal.
The action time of the reset circuit can be preset to be matched with the clock circuit to carry out, after the calculation of the pixel modulation and demodulation contrast is completed, the circuit can repeatedly carry out different contrast calculations for many times, the accuracy of the whole sensor is ensured, and the reset circuit can also be matched with other signals such as input grid signals of an MOS (metal oxide semiconductor) tube.
Fig. 3 is a schematic structural diagram of a pixel unit circuit detection device according to another embodiment of the present disclosure, and as shown in fig. 3, the device further includes: a first selection switch 301 and a second selection switch 302.
Further, the other end of the non-gate of the first source follower MOS 603 may be connected to the first output terminal VOUT1 by providing a first selection switch 301 (for example, a MOS transistor); the other non-gate end of the second source follower MOS transistor 703 is connected to the second output terminal VOUT2 through a second selection switch 302 (e.g., a MOS transistor), which is not limited in this regard.
Fig. 4 is a control timing chart of the pixel unit circuit detecting device according to an embodiment of the present application, and the charge injection process is explained in detail based on the above embodiment, as shown in the timing chart of fig. 4.
The a to D stages, which belong to the reset stage, first perform a reset operation on the photodiode 02. Specifically, in the reset stage VDD1, VDD2, VDD 01 are all biased at a high level, the clock control circuit controls the gates of the input switch 03, the first modulation switch 04, and the second modulation switch 05 to be in a high-level on state, and in this process, electrons in the photodiode 02 are evacuated to be completely depleted, so that preparation is made for subsequent charge integration.
After the phase D is finished, that is, after the reset operation is finished, the gates of the input switch 03, the first modulation switch 04, and the second modulation switch 05 are biased to the low-level off state, and vdd 01 is also turned to the low level.
Further, in the process of injecting the charge, the clock control circuit controls the input switch 03 and the first modulation switch 04, and electrons flow into the photodiode 02 from the vdd 01 terminal.
After the reset is finished, the photodiode 02 fully depletes the clamp voltage Vpin, assuming that Vpin is about 1V, the voltage at the input switch 03 side is vdd, the voltage at one side is Vpin, and Vpin is greater than vdd, when the input switch 03 is turned on, electrons flow into the photodiode 02 from the vdd 01 end, thereby achieving the effect of charge injection to the PD photodiode. In addition, when the control input switch 03 and the first modulation switch 04 are turned on simultaneously, the gate voltage of the first modulation switch 04 is higher and the gate voltage of the second modulation switch 05 is lower, and electrons are collected by the first modulation switch 04. Similarly, when the gate voltage of the first modulation switch 04 is low and the gate voltage of the second modulation switch 05 is high, electrons are collected by the second modulation switch 05.
As shown in fig. 4, the gate control voltages of the first modulation switch 04 and the second modulation switch 05 are opposite and can be repeated for multiple times, so that multiple sets of output signals of the first output terminal and the second output terminal can be obtained.
Alternatively, the algorithm for calculating the modulation and demodulation contrast according to the sets of output signals V1, V2 at the first output end and the second output end may be:
modulation-demodulation contrast
Fig. 5 is a schematic flow chart of a pixel unit circuit detection method according to an embodiment of the present application, where the method is applied to the foregoing apparatus, and as shown in fig. 5, the method includes:
s501, receiving switch control signals of the clock control circuit to the input end switch, the first modulation switch and the second modulation switch.
The switch control signal is used for controlling the on or off of the input end switch, the first modulation switch and the second modulation switch.
And S502, respectively controlling the states of the input end switch, the first modulation switch and the second modulation switch according to the switch control signal, so that electrons are input into the photodiode from the variable voltage input end.
S503, acquiring output data of the first output end and the second output end respectively based on the electrons collected by the photodiode.
In the pixel unit circuit detection method provided in the embodiment of the present application, signal inputs of the variable voltage input terminal, the first modulation switch, and the second modulation switch are controlled by the same clock control circuit, and receive switch control signals of the clock control circuit to the input terminal switch, the first modulation switch, and the second modulation switch, and respectively control states of the input terminal switch, the first modulation switch, and the second modulation switch according to the switch control signals, so that electrons are input to the photodiode from the variable voltage input terminal, and further, based on the electrons collected by the photodiode, output data of the first output terminal and the second output terminal are respectively obtained, thereby ensuring that an input signal is synchronized with a signal corresponding to one of the modulation switches, and improving accuracy and reliability of measurement.
Further, the photodiode has an electron amount of 0 after reset, gates of the input switch, the first modulation switch and the second modulation switch are all biased to a low-level off state, and the variable voltage input terminal is in a low-level state.
Accordingly, the controlling the states of the input switch, the first modulation switch and the second modulation switch according to the switch control signal to input electrons from the variable voltage input terminal to the photodiode may include: after the photodiode is reset, the input end switch and the first modulation switch are controlled to be simultaneously turned on according to the switch control signal, electrons are input into the photodiode through the variable voltage input end, and when a grid signal of the first modulation switch is at a high level and a grid signal of the second modulation switch is at a low level, the first modulation switch collects the electrons.
In addition, when the grid signal of the second modulation switch is at a high level and the grid signal of the first modulation switch is at a low level, the second modulation switch collects electrons.
In an optional embodiment, referring to the first reset circuit and the second reset circuit shown in fig. 2, before receiving the switch control signals of the input switch, the first modulation switch, and the second modulation switch, the clock control circuit further includes:
and biasing the first power interface, the second power interface and the variable voltage input end to high level, and biasing the input end switch, the first modulation switch and the second modulation switch to high level until the electrons in the photodiode are discharged to complete resetting.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (10)
1. A pixel cell circuit testing apparatus, comprising:
the device comprises a variable voltage input end, a photodiode, an input end switch, a first modulation switch and a second modulation switch;
one end of the input end switch is connected with the variable voltage input end, the other end of the input end switch is respectively connected with one end of the first modulation switch, one end of the second modulation switch and the output end of the photodiode, the input end of the photodiode is grounded, and the signal input of the input end switch, the first modulation switch and the second modulation switch is controlled by the same clock control circuit;
the other end of the first modulation switch is connected to the first output end through a first reset circuit, and the other end of the second modulation switch is connected to the second output end through a second reset circuit.
2. The pixel cell circuit detecting device according to claim 1, wherein the photodiode has an electron amount of 0 after reset, gates of the input switch, the first modulation switch, and the second modulation switch are all biased to a low-level off state, and the variable voltage input terminal is in a low-level state;
after the input end switch and the first modulation switch are simultaneously turned on, electrons are input into the photodiode through the variable voltage input end, and when a grid signal of the first modulation switch is at a high level and a grid signal of the second modulation switch is at a low level, the first modulation switch collects the electrons.
3. The pixel cell circuit detecting device according to claim 1, wherein the second modulation switch collects electrons when the gate signal of the second modulation switch is at a high level and the gate signal of the first modulation switch is at a low level.
4. The pixel cell circuit detecting device according to claim 2, wherein the first reset circuit comprises: the power supply comprises a first capacitor, a first reset switch, a first source electrode following MOS tube and a first power interface; the other end of the first modulation switch and one end of the first capacitor are connected with one end of the first reset switch; the other end of the first reset switch and one end of the first source-follower MOS transistor, which is not a gate, are connected to the first power interface, the gate terminal of the first source-follower MOS transistor is connected to one end of the first reset switch, the other end of the first modulation switch, and one end of the first capacitor, respectively, and the other end of the first source-follower MOS transistor, which is not a gate, is connected to a first output terminal;
the second reset circuit includes: the second capacitor, the second reset switch, the second source electrode following MOS tube and the second power interface; the other end of the second modulation switch and one end of the second capacitor are connected with one end of the second reset switch; the other end of the second reset switch and one end of the second source electrode following MOS tube non-grid electrode are connected with the second power supply interface, the grid electrode end of the second source electrode following MOS tube is respectively connected with one end of the second reset switch, the other end of the second modulation switch and one end of the second capacitor, and the other end of the second source electrode following MOS tube non-grid electrode is used for being connected with a second output end.
5. A pixel cell circuit inspection method applied to the pixel cell circuit inspection apparatus according to any one of claims 1 to 4, the method comprising:
receiving switch control signals of a clock control circuit to the input end switch, the first modulation switch and the second modulation switch;
controlling the states of the input end switch, the first modulation switch and the second modulation switch according to the switch control signal, so that electrons are input into the photodiode from the variable voltage input end;
and respectively acquiring output data of the first output end and the second output end based on the electrons collected by the photodiode.
6. The method of claim 5, wherein the photodiode has an electron amount of 0 after reset, the gates of the input switch, the first modulation switch, and the second modulation switch are all biased to a low off state, and the variable voltage input is in a low state;
the controlling the states of the input switch, the first modulation switch and the second modulation switch according to the switch control signal to enable electrons to be input into the photodiode through the variable voltage input end comprises:
after the photodiode is reset, the input end switch and the first modulation switch are controlled to be simultaneously turned on according to the switch control signal, electrons are input into the photodiode through the variable voltage input end, and when a grid signal of the first modulation switch is at a high level and a grid signal of the second modulation switch is at a low level, the first modulation switch collects the electrons.
7. The method of claim 5, wherein the second modulation switch collects electrons when the gate signal of the second modulation switch is high and the gate signal of the first modulation switch is low.
8. The method of claim 6, wherein the first reset circuit comprises: the power supply comprises a first capacitor, a first reset switch, a first source electrode following MOS tube and a first power interface; the other end of the first modulation switch and one end of the first capacitor are connected with one end of the first reset switch; the other end of the first reset switch and one end of the first source-follower MOS transistor, which is not a gate, are connected to the first power interface, the gate terminal of the first source-follower MOS transistor is connected to one end of the first reset switch, the other end of the first modulation switch, and one end of the first capacitor, respectively, and the other end of the first source-follower MOS transistor, which is not a gate, is connected to a first output terminal;
the second reset circuit includes: the second capacitor, the second reset switch, the second source electrode following MOS tube and the second power interface; the other two ends of the second modulation switch and one end of the second capacitor are connected with one end of the second reset switch; the other end of the second reset switch and one end of the second source electrode following MOS tube non-grid electrode are connected with the second power supply interface, the grid electrode end of the second source electrode following MOS tube is respectively connected with one end of the second reset switch, the other end of the second modulation switch and one end of the second capacitor, and the other end of the second source electrode following MOS tube non-grid electrode is used for being connected with a second output end.
9. The method of claim 8, wherein the receiving the clock control signals of the input switch, the first modulation switch, and the second modulation switch preceded by the clock control circuit, further comprising:
and biasing the first power interface, the second power interface and the variable voltage input end to high level, and biasing the input end switch, the first modulation switch and the second modulation switch to high level until the electrons in the photodiode are discharged to complete resetting.
10. The method of claim 7, wherein the apparatus further comprises:
a first selection switch and a second selection switch;
the other end of the first source electrode following MOS tube non-grid electrode is connected with one end of the first selection switch, and the other end of the first selection switch is connected with the first output end;
the other end of the second source electrode following MOS tube non-grid electrode is connected with one end of the second selection switch, and the other end of the second selection switch is connected with the first output end.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010008111.2A CN111147776B (en) | 2020-01-02 | 2020-01-02 | Pixel unit circuit detection device and method |
Applications Claiming Priority (1)
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