CN111147175A - Time-triggered Ethernet data frame capturing and storing device and method - Google Patents
Time-triggered Ethernet data frame capturing and storing device and method Download PDFInfo
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- CN111147175A CN111147175A CN201911190445.XA CN201911190445A CN111147175A CN 111147175 A CN111147175 A CN 111147175A CN 201911190445 A CN201911190445 A CN 201911190445A CN 111147175 A CN111147175 A CN 111147175A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0641—Change of the master or reference, e.g. take-over or failure of the master
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0658—Clock or time synchronisation among packet nodes
Abstract
In order to solve the technical problem that the existing capturing method cannot meet the debugging and verification requirements of the functions of synchronization, communication and the like of the time-triggered Ethernet with the speed of 1Gbps and 10Gbps, the invention provides a device and a method for capturing and storing a time-triggered Ethernet data frame. The invention solves the problems of filtering and capturing based on the error type, protocol type, virtual link or destination MAC address of the data frame, realizes the real-time filtering and capturing of the data frame, and meets the debugging and verifying requirements of the functions of synchronization, communication and the like of the time-triggered Ethernet with the speed of 1Gbps and 10 Gbps; the data frame descriptors and the data frame contents are independently stored, so that a standard libpcap file is conveniently formed, the data analysis process is simplified by using the standard libpcap library for analysis, the interruption based on the data buffer length or the buffer quantity is supported, and the method has the advantages of flexible filtering control, simple data analysis, extremely less processor time occupation in the data transmission process and the like.
Description
Technical Field
The invention belongs to the technical field of network communication, and relates to a time-triggered Ethernet data frame capturing and storing device and method.
Background
In the ethernet conforming to the IEEE802.3 standard, a network device uses an event-triggered transmission mechanism, and the network device can access the network at any point in time, using a first-come-first-serve principle. Communication between network devices over a shared medium necessarily results in some messages being transmitted with indeterminate jitter and cumulative delay. On the basis of standard Ethernet, ARINC company provides an AFDX (avionics full Duplex switched Ethernet) network of ARINC664 Part7 standard, and Virtual Links (VL), Bandwidth Allocation Gaps (BAG), jitter management and other mechanisms are added in a data link layer, so that the conflict in the message transmission process is effectively reduced, the message has real-time performance and certainty, and the requirements of reliability and certainty of avionics system information transmission are met.
The SAE organization has promulgated the AS6802 time-triggered ethernet (TTE) network standard, compatible with standard ethernet and AFDX networks, using coordinated and uniform network time among network devices to reduce transmission delay and jitter, thereby meeting the application needs of different real-time and security levels in a single network. The AS6802 standard supports Time-Triggered messages (Time-Triggered messages, abbreviated AS TT messages), Rate-limited messages (Rate-dependent messages, abbreviated AS RC messages) and Best-Effort messages (Best-Effort messages, abbreviated AS BE messages) of a Time-Triggered mechanism, and Protocol Control frames (Protocol Control frames, abbreviated AS PCF messages) for uniform Time.
Currently, simulation equipment and test equipment are mostly adopted for debugging and verifying the time-triggered Ethernet, and dedicated time-triggered Ethernet data capture equipment is not available for the time. When data needs to be captured, common Ethernet equipment is used for being matched with capture software, a kernel-level packet filter is used for assisting, and filtering display is carried out in the software after all capture storage, so that the two modes occupy a large amount of processor resources, can not capture some error data, are difficult to capture specified data according to a capture table, and can not meet the debugging and verification requirements of functions of synchronization, communication and the like of the time-triggered Ethernet with the speed of 1Gbps and 10 Gbps.
Disclosure of Invention
In order to solve the technical problem that the existing capturing method cannot meet the debugging and verification requirements of the functions of synchronization, communication and the like of the time-triggered Ethernet with the speed of 1Gbps and 10Gbps, the invention provides a device and a method for capturing and storing a time-triggered Ethernet data frame.
The technical scheme of the invention is as follows:
the time triggered Ethernet data frame capturing and storing device is characterized by comprising:
n data receiving channels, wherein N is more than or equal to 1; the system also comprises a real-time clock unit, a data management unit, a data cache unit, a capture management unit, a PCIE controller and a PCI interface unit;
each data receiving channel comprises a TTE interface unit, an MAC receiving unit, a filtering control unit, a descriptor queue unit and a data frame queue unit;
the MAC receiving unit reads the data frame from the TTE interface unit, sends a signal to the real-time clock unit when the 1 st bit arrives, checks the data frame in the reading process, extracts data frame information including a state mark, a type mark and the actual length of the data frame, and calculates the length of a buffer area occupied by the data frame;
the filtering control unit selectively passes the data frames according to the data frame information provided by the MAC receiving unit and the filtering control information provided by the capturing management unit, and the passed data frames are capturing frames; the filtering control information comprises a frame type enable;
the descriptor queue unit stores descriptors of data frames released by the filtering control unit, wherein the descriptors comprise a second value S and a nanosecond value NS provided by the real-time clock unit, and a state mark, the actual length of the data frames and the length of a buffer area occupied by the data frames provided by the MAC receiving unit;
the data frame queue unit stores the data frames released by the filtering control unit;
a real-time clock unit maintains a time record, which comprises a second value S and a nanosecond value NS;
the data management unit reads data from the data frame queue unit and the descriptor queue unit of the N-path data receiving channels according to a set format, reads cache data from the data cache unit according to a request of the upper computer, and sends the cache data to the upper computer through the PCIE controller and the PCIE interface;
the data caching unit acquires data from the data management unit and performs caching storage;
the data frame and descriptor information thereof provided by the data management unit are collected by the management unit, and an interrupt signal is sent to the upper computer through the PCIE controller and the PCIE interface; the capture management unit is also used for acquiring the filtering control information from an upper computer and sending a transmission data preparation signal to the data management unit;
the PCIE controller and the PCI interface unit provide data interaction between the data management unit and the upper computer and between the capture management unit and the upper computer.
Further, if the data frame type is an IN frame, the data frame information extracted by the MAC receiving unit further includes the number of members; if the data frame type is TT frame or RC frame, the data frame information extracted by the MAC receiving unit also comprises a virtual link identifier field of the data frame; if the data frame type is a BE frame, the data frame information extracted by the MAC receiving unit further includes a destination MAC address field of the data frame.
The invention also provides a method for realizing the capture and storage of the time-triggered Ethernet data frame based on the time-triggered Ethernet data frame capture and storage device, which is characterized in that:
the capture management unit acquires the filtering control information sent by the upper computer through the PCIE controller and the PCI interface unit, and the filtering control information comprises
The overlength error frame reception enable signal overlap _ en,
the non-aligned error frame reception enable signal unalign _ en,
the check error frame reception enable signal checkerr en,
the type length field error frame reception enable signal lener _ en,
reception control enable signals CS _ en, CA _ en, IN _ en, TT _ en, RC _ en, and BE of frame types CS, CA, IN, TT _ en,
the IN frame membership threshold control enable signal IN _ thrld _ en,
the IN frame membership threshold IN _ thrld,
TT, RC and BE frame capture tables enable TT tab en, RC tab en and BE tab en,
TT, RC, and BE frame capture tables TT _ tab, RC _ tab, and BE _ tab,
a destination MAC address constant field RC _ dstmac _ const of the RC frame,
the maximum capture length max _ cap _ len for a single data frame,
the buffered frame number threshold controls the interrupt enable signal cap num int en,
the buffered frame number threshold cap num thrld,
the buffer frame length threshold controls the interrupt enable signal cap _ len _ int _ en,
a buffer frame length threshold value cap _ len _ thrld;
the capture management unit counts the data frames and descriptor information thereof provided by the data management unit in real time, including
Total number of captured frames total _ cap _ num,
the total length of space occupied by the capture frame total _ cap _ len,
the actual total length of the capture frame total _ frame _ len,
the total number of currently buffered frames cur _ cap _ num,
the total length cur _ cap _ len of the occupied space of the current buffering frame;
when the threshold value of the number of buffered frames controls the interrupt enable signal cap _ num _ int _ en to be in an enable state and the total number of currently buffered frames cur _ cap _ num is greater than or equal to the threshold value of the number of buffered frames cap _ num _ thrld,
or
When the buffer frame length threshold controls the interrupt enable signal cap _ len _ int _ en to be in an enable state and the total length cur _ cap _ len of the occupied space of the current buffer frame is greater than or equal to the buffer frame length threshold cap _ len _ thrld,
the capture management unit sends a data transmission preparation signal to the data management unit and simultaneously sends an interrupt signal to the upper computer;
when the upper computer actively reads the total length cur _ cap _ len of the occupied space of the current buffer frame, the capture management unit only sends a transmission data preparation signal to the data management unit;
the MAC receiving unit receives a data frame from the TTE interface and sends a signal to the real-time clock unit when a 1 st bit arrives;
the MAC receiving unit checks whether the data frame has errors or not in the receiving process, and extracts a state mark Fstatus of the data frame, wherein the state mark Fstatus comprises 3 bits; the data frame state corresponding to the data frame state mark Fstatus comprises data correctness, an overlength frame error, a non-aligned frame error, a frame check error and a type length field error;
the MAC receiving unit checks the relevant field of the data frame, determines the type of the data frame,
if the determined data frame type is an IN frame, recording the number of bits 1 IN the membership field of the data frame, namely the membership Fmn;
if the determined data frame type is a TT frame or an RC frame, recording a virtual link identifier field Fvlid of the data frame;
if the determined data frame type is a BE frame, recording a destination MAC address field Fdmac of the data frame;
the MAC receiving unit also records the length of a received data frame, wherein redundant bits of the non-aligned error frame are calculated according to 1 byte;
after the MAC receiving unit receives the data frame, calculating the length CapLen of the data frame occupied buffer area released by the filtering control unit:
len ═ min { fire, max _ cap _ len }, max _ cap _ len is the maximum capture length of a single data frame, i.e., the maximum number of bytes of data frames retained by the filter control unit;
when receiving the signal sent by the MAC receiving unit, the real-time clock unit provides clock information of the arrival time of the data frame, including a second value Fs and a nanosecond value Fns;
the filtering control unit judges and processes each received frame as follows:
when the data frame state is an overlength frame error, a non-aligned frame error, a frame check error or a type length field error, judging whether a corresponding overlength error frame receiving enabling signal overrule _ en, a non-aligned error frame receiving enabling signal unalign _ en, a check error frame receiving enabling signal checkerr _ en or a type length field error frame receiving enabling signal lener _ en is enabled, if so, accepting the data frame, otherwise, discarding the data frame;
when the data frame state is data correct and the frame type is CS or CA, judging whether a corresponding CS frame receiving control enabling signal CS _ en or CA frame receiving control enabling signal CA _ en is enabled, if so, receiving the data frame, otherwise, discarding the data frame;
when the data frame status is data correct and the frame type is IN,
receiving a data frame if the IN frame reception control enable signal IN _ en is IN an enable state but the IN frame member threshold control enable signal IN _ thrld _ en is disabled;
if the IN frame receiving control enabling signal IN _ en and the IN frame member threshold control enabling signal IN _ thrld _ en are both IN an enabling state, and the member number Fmn is not less than the IN frame member threshold IN _ thrld, receiving the data frame, otherwise, discarding the data frame;
when the data frame status is data correct and the frame type is TT,
if the TT frame reception control enable signal TT _ en is in an enable state, but the TT frame capture table enable signal TT _ tab _ en is in a disable state, receiving a data frame;
if the TT frame receiving control enabling signal TT _ en and the TT frame capturing table enabling signal TT _ tab _ en are both in an enabling state, and the virtual link identifier field Fvlid of the data frame belongs to the TT frame capturing table TT _ tab, receiving the data frame, otherwise, discarding the data frame;
when the data frame state is data correct and the frame type is RC, the processing method of the data frame is the same as the TT frame;
when the data frame status is data correct and the frame type is BE,
if the BE frame reception control enable signal BE _ en is in an enable state, but the BE frame capture table enable signal BE _ tab _ en is disabled, receiving the data frame;
if the BE frame reception control enabling BE _ en and the BE frame capture table enabling signal BE _ tab _ en are both in an enabling state, and the destination MAC address field Fdmac of the data frame belongs to the BE frame capture table BE _ tab, receiving the data frame, otherwise, discarding the data frame;
the descriptor queue unit collects a second value Fs and a nanosecond value Fns provided by the real-time clock unit, a state mark Fstatus of a data frame provided by the MAC receiving unit, a data frame length Flen and a data frame occupied buffer area length CapLen to form a 16-byte data frame descriptor; the 16-byte data frame descriptors are, from low address to high address, as follows: the second value Fs occupies 4 bytes, the nanosecond value Fns/8 occupies the middle-high 29 bits in 4 bytes, the state mark Fstatus of the data frame occupies the middle-low 3 bits in 4 bytes, the length of the data frame Flen occupies 4 bytes, and the length of the data frame CapLen occupies 4 bytes;
the descriptor queue generated by the descriptor queue unit corresponds to the data frame queue output by the filtering control unit, and each data frame in the data frame queue corresponds to a descriptor;
the data management unit manages the data cache unit, organizes the storage space of the data cache unit into a circular queue, and provides a read pointer pr and a write pointer pw;
the data management unit polls the data frame queue and descriptor queue of the N data receiving channels,
if the data frame queue and/or descriptor queue of a certain data receiving channel is not empty, the data management unit respectively takes out the descriptor and the data frame from the descriptor queue and the data frame queue of the data receiving channel, stores the descriptor and the data frame to the position of a write pointer pw of the data buffer unit according to the sequence of the descriptor before and the data frame after, and then updates the write pointer pw by the data management unit;
when the data management unit receives a transmission data preparation signal sent by the capture management unit, the value of the read ending pointer cpw is set as the value of the current write pointer pw, and the data to be transmitted is determined to be the data from the read pointer pr to cpw-1;
when the host computer receives the interrupt signal sent by the capturing management unit, the data to be transmitted is moved from the data cache unit to the memory of the host computer;
the upper computer can also actively read the total length cur _ cap _ len of the occupied space of the current buffer frame and start the data transfer from the data buffer unit to the memory of the upper computer; when data is moved, the length of the descriptor is fixed by 16 bytes, and the length of the data frame is determined by the length CapLen field of the buffer area occupied by the data frame in the descriptor; after the data transfer is completed, the data management unit updates the read pointer pr.
Further, when the upper computer stores the captured data frame and the descriptor thereof, firstly, a storage space is allocated, wherein the storage space comprises 24 bytes which are pre-reserved and used for storing the global header of the libpcap file, and the type of the libpcap file is nanosecond resolution; the data frames and descriptors read from the data cache unit are then stored behind the libpcap file global header, such that the global header, descriptors, data frames are organized into a standard libpcap file format.
Further, in the receiving process, the MAC receiving unit checks the relevant field of the data frame, and determines the type of the data frame, which is specifically as follows:
the destination MAC address constant field is 0 xabadbabbe, the MAC type field is 0x891d, the PCF type field is 0x4, and is marked as CS frame;
the destination MAC address constant field is 0 xabadbabbe, the MAC type field is 0x891d, the PCF type field is 0x8, and is marked as a CA frame;
the destination MAC address constant field is 0 xabadbabbe, the MAC type field is 0x891d, the PCF type field is 0x2, and is marked as an IN frame;
the destination MAC address constant field is 0 xabadbabbe, the MAC type field is 0x88d7, and the field is marked as TT frame;
the destination MAC address constant field is RC _ dstmac _ const, the MAC type field is 0x0800, and the destination MAC address constant field is recorded as an RC frame;
frames with MAC type field not 0x891d, 0x88d7, or 0x0800, or MAC type field 0x0800 and destination MAC address constant field not rc _ dstmac _ const, are denoted as BE frames.
The invention has the beneficial effects that:
1. the invention solves the problems of filtering and capturing based on the error type and protocol type of the data frame, virtual link or target MAC address, and organization, storage and analysis of the data frame, can realize real-time filtering and capturing of the data frame, and meets the debugging and verification requirements of the functions of synchronization, communication and the like of the time-triggered Ethernet with the speed of 1Gbps and 10 Gbps.
2. The invention adopts the independent storage of the data frame descriptor and the data frame content, is convenient for forming a standard libpcap file in the memory of the host, utilizes the analysis of a standard libpcap library, simplifies the data analysis process, operates the filtration and the capture based on the error type, the protocol type, the virtual link or the destination MAC address of the data frame, supports the interruption based on the data buffering length or the buffering quantity, and has the advantages of flexible filtration control, simple data analysis, little occupation of processor time in the data transmission process and the like.
Drawings
Fig. 1 is a schematic block diagram of a time triggered ethernet data frame capture and storage device of the present invention.
Detailed Description
The invention is further described below with reference to the accompanying drawings.
As shown in fig. 1, the time-triggered ethernet data frame capturing and storing apparatus of the present invention includes a real-time clock unit, a data management unit, a data cache unit, a capturing management unit, a PCIE controller, a PCI interface unit, and N data receiving channels, where N is greater than or equal to 1; each data receiving channel comprises a TTE interface unit, an MAC receiving unit, a filtering control unit, a descriptor queue unit and a data frame queue unit. The present invention will be described in detail below with reference to the respective parts.
First, capture management unit
The capture management unit obtains, through the PCIE controller and the PCI interface unit, filter control information sent by the upper computer, including an over-length error frame reception enable signal over _ en, a non-aligned error frame reception enable signal unaligned _ en, a check error frame reception enable signal checkerr _ en, a type length field error frame reception enable signal lener _ en, reception control enable CS _ en, CA _ en, TT _ en, RC _ en, and BE _ en of types CS (cold start frame), CA (cold start acknowledge frame), IN (integrated frame), TT (time triggered data frame), RC (rate limited data frame), and BE (best effort data frame), an IN frame member threshold control enable IN _ trld _ en, an IN frame threshold IN _ trld, TT, RC, and BE frame capture table enable TT _ tab _ en, RC _ tab _ en, and BE _ tab _ en, and a capture table, TT _ tab _ en, and BE _ tab _ frame capture table, RC _ tab and be _ tab, destination MAC address constant field RC _ dstmac _ const of RC frame, maximum capture length max _ cap _ len of single data frame, buffer frame number threshold control interrupt enable cap _ num _ int _ en, buffer frame number threshold cap _ num _ thrld, buffer frame length threshold control interrupt enable cap _ len _ int _ en and buffer frame length threshold cap _ len _ thrld.
The capture management unit counts the data frames and the descriptor information thereof provided by the data management unit in real time, and the data frames and the descriptor information thereof comprise total capture frame total number total _ cap _ num, total capture frame occupied space total number total _ cap _ len, actual capture frame total length total _ frame _ len, total current buffer frame number cur _ cap _ num and total current buffer frame occupied space total length cur _ cap _ len.
Wherein:
capturing the total frame number total _ cap _ num accumulated data frame number read from the data frame queue by the data management unit;
capturing the total length total _ cap _ len of the occupied space of the frame, accumulating the number of bytes of the storage space occupied by the data frame and the descriptor read from the data frame queue and the descriptor queue by the data management unit;
capturing a descriptor Flen read by a frame actual total length total _ frame _ len accumulated data management unit from a descriptor queue;
the total number cur _ cap _ num of the current buffer frames accumulates the number of data frames currently stored in the data buffer unit;
the total length cur _ cap _ len of the occupied space of the current buffer frame accumulates the number of bytes of the occupied space of the descriptor and the data frame currently stored in the data buffer unit.
The capture management unit updates the total capture frame number total _ cap _ num, the total capture frame occupied space total _ cap _ len, the capture frame actual total length total _ frame _ len, the current buffer frame total number cur _ cap _ num and the current buffer frame occupied space total length cur _ cap _ len after the data management unit reads the data frame and the descriptor queue,
when the threshold value of the number of buffered frames controls the interrupt enable signal cap _ num _ int _ en to be in an enable state and the total number of currently buffered frames cur _ cap _ num is greater than or equal to the threshold value of the number of buffered frames cap _ num _ thrld,
or
When the buffer frame length threshold controls the interrupt enable signal cap _ len _ int _ en to be in an enable state and the total length cur _ cap _ len of the occupied space of the current buffer frame is greater than or equal to the buffer frame length threshold cap _ len _ thrld,
the capture management unit sends a data transmission preparation signal to the data management unit and simultaneously sends an interrupt signal to the upper computer; by default, the buffer frame number threshold controls the interrupt enable cap _ num _ int _ en, and the buffer frame length threshold cap _ len _ thrld is 1048576 (i.e., 1 MB).
When the upper computer actively reads the total length cur _ cap _ len of the occupied space of the current buffer frame, the capture management unit only sends a transmission data preparation signal to the data management unit.
Second, MAC receiving unit
The MAC receiving unit receives data from the TTE interface and sends a signal to the real-time clock unit when a 1 st bit arrives;
the MAC receiving unit checks whether the data frame has errors in the receiving process, and provides a status flag Fstatus of the data frame, wherein the status flag Fstatus of the data frame comprises 3 bits, and the MAC receiving unit comprises: 0x0 indicates data correct, 0x4 indicates an extra-long frame error, 0x5 indicates a non-aligned frame error, 0x6 indicates a frame check error, 0x7 indicates a type length field error, and the rest remains.
In the receiving process, the MAC receiving unit checks the relevant field of the data frame to determine the type of the data frame:
the destination MAC address constant field is 0 xabadbabbe, the MAC type field is 0x891d, and the PCF type field is 0x4, and is denoted as CS (cold start frame);
the destination MAC address constant field is 0 xabadbabbe, the MAC type field is 0x891d, and the PCF type field is 0x8, and is denoted as CA (cold start acknowledgement frame);
the destination MAC address constant field is 0 xabadbabbe, the MAC type field is 0x891d, and the PCF type field is 0x2, and is denoted as IN (integrated frame);
the destination MAC address constant field is 0 xabadbabbe, the MAC type field is 0x88d7, and is denoted as TT (time triggered data frame);
the destination MAC address constant field is RC _ dstmac _ const, the MAC type field is 0x0800, and is noted as RC (rate limiting data frame);
a frame whose MAC type field is not 0x891d, 0x88d7, or 0x0800, or whose MAC type field is 0x0800 and whose destination MAC address constant field is not rc _ dstmac _ const is denoted as BE (best effort data frame).
IN the receiving process, if the data frame type is an IN frame, the MAC receiving unit records the number of bits 1 IN the membership field of the data frame, namely the membership Fmn;
in the receiving process, if the data frame type is TT frame or RC frame, the MAC receiving unit records the virtual link identifier field Fvlid of the data frame;
and in the receiving process, if the data frame type is a BE frame, the MAC receiving unit records a destination MAC address field Fdmac of the data frame.
The MAC receiving unit also records the received data frame length, Flen, where the excess bits of the non-aligned error frame are calculated in 1 byte.
After the MAC receiving unit receives the data frame, the MAC receiving unit calculates the length CapLen of the buffer occupied by the data frame released by the filtering control unit,
len min Flen max _ cap _ len, max _ cap _ len being the maximum capture length of a single data frame, i.e. the maximum number of bytes of the data frame retained by the filter control unit.
Three, real time clock unit
When receiving the signal sent by the MAC receiving unit, the real-time clock unit provides clock information of the arrival time of the data frame, including a second value Fs and a nanosecond value Fns.
Fourth, filter the control unit
The filtering control unit judges and processes each received frame as follows:
when the status flag Fstatus of the data frame is 0x4, indicating that an ultra-long frame error occurs in the data frame, determining whether an ultra-long error frame reception enable signal over enable _ en is in an enable state, if so, accepting the data frame, otherwise, discarding the data frame;
when the status flag Fstatus of the data frame is 0x5, indicating that a non-aligned frame error occurs in the data frame, determining whether a non-aligned error frame reception enable signal unalign _ en is in an enable state, if so, accepting the data frame, otherwise, discarding the data frame;
when the status flag Fstatus of the data frame is 0x6, indicating that a frame check error occurs in the data frame, determining whether a check error frame reception enable signal checkerr _ en is in an enable state, if so, accepting the data frame, otherwise, discarding the data frame;
when the status flag Fstatus of the data frame is 0x7, indicating that the data frame has a type length field error, determining whether the length _ en is in an enabled state, if so, accepting the data frame, otherwise, discarding the data frame;
when the status flag Fstatus of the data frame is 0x0 (indicating that the data is correct) and the frame type is CS, determining whether the CS frame reception control enable signal CS _ en is in an enable state, if so, receiving the data frame, otherwise, discarding the data frame;
when the status flag Fstatus of the data frame is 0x0 (indicating that the data is correct) and the frame type is CA, determining whether a CA frame reception control enable signal CA _ en is enabled, if so, receiving the data frame, otherwise, discarding the data frame;
when the status flag Fstatus of the data frame is 0x0 (indicating that the data is correct) and the frame type is IN, if the IN frame reception control enable signal IN _ en is IN an enabled state and the IN frame member threshold control enable signal IN _ thrld _ en is IN a disabled state, the data frame is received; if the IN frame receiving control enabling signal IN _ en is IN an enabling state, the IN frame member threshold value control enabling signal IN _ thrld _ en is IN an enabling state, the number Fmn of the members is not less than the IN frame member threshold value IN _ thrld, receiving the data frame, otherwise, discarding the data frame;
when the status flag Fstatus of the data frame is 0x0 (indicating that the data is correct) and the frame type is TT, if the TT frame reception control enable signal TT _ en is in an enabled state and the TT frame capture table enable signal TT _ tab _ en is in a disabled state, the data frame is received; and if the TT frame receiving control enabling signal TT _ en is in an enabling state, the TT frame capturing table enabling signal TT _ tab _ en is in an enabling state, the virtual link identifier field Fvlid of the data frame belongs to the TT frame capturing table TT _ tab, receiving the data frame, and otherwise, discarding the data frame.
When the status flag Fstatus of the data frame is 0x0 (indicating that the data is correct) and the frame type is RC, if the RC frame reception control enable signal RC _ en is in an enable state and the RC frame capture table enable signal RC _ tab _ en is in a disable state, the data frame is received; and if the RC frame receiving control enabling signal RC _ en is in an enabling state, the RC frame capturing table enabling signal RC _ tab _ en is in an enabling state, the virtual link identifier field Fvlid of the data frame belongs to the RC frame capturing table RC _ tab, receiving the data frame, and otherwise, discarding the data frame.
When the status flag Fstatus of the data frame is 0x0 (indicating that the data is correct) and the frame type is BE, if the BE frame reception control enable signal BE _ en is in an enable state and the BE frame capture table enable signal BE _ tab _ en is in a disable state, the data frame is received; and if the BE frame reception control enabling signal BE _ en is in an enabling state, the BE frame capture table enabling signal BE _ tab _ en is in an enabling state, the destination MAC address field Fdmac of the data frame belongs to the BE frame capture table BE _ tab, receiving the data frame, and otherwise, discarding the data frame.
Fifthly, descriptor queue unit
The descriptor queue collects Fs and Fns provided by a real-time clock unit, a state mark Fstatus and a data frame length Flen of a data frame provided by an MAC receiving unit, and a data frame occupied buffer area length CapLen, and forms a 16-byte data frame descriptor, wherein the 16-byte data frame descriptor sequentially comprises the following components from a low address to a high address: the second value Fs occupies 4 bytes, the nanosecond value Fns/8 occupies the middle-high 29 bits in 4 bytes, the state flag Fstatus of the data frame occupies the middle-low 3 bits in 4 bytes, the length of the data frame Flen occupies 4 bytes, and the length of the data frame CapLen occupies 4 bytes.
The descriptor queue generated by the descriptor queue unit corresponds to the data frame queue output by the filtering control unit, and one data frame corresponds to one descriptor.
Sixthly, a data management unit
The data management unit manages the data buffer unit, organizes the storage space of the data buffer into a circular queue, and provides a read pointer pr and a write pointer pw.
The data management unit polls the data frame queue and descriptor queue of the N data receiving channels,
if the data frame queue and/or the descriptor queue of a certain data receiving channel are/is not empty (both are certainly not empty at the same time), the data management unit respectively takes out the descriptor and the data frame from the descriptor queue and the data frame queue of the data receiving channel, stores the descriptor and the data frame to the position of a write pointer pw of the data buffer unit according to the sequence of the descriptor before and the data frame after, and then updates the write pointer pw by the data management unit, wherein the updated write pointer pw is an initial write pointer + the written data length;
when the data management unit receives the transmission data preparation signal sent by the capture management unit, the value of the read end pointer cpw is set as the value of the current write pointer pw, and the data from the read pointers pr to cpw-1 is determined as the data to be transmitted.
Seven, upper computer
When the host computer receives the interrupt signal sent by the capturing management unit, the data to be transmitted are transferred from the data cache unit to the memory of the host computer; the host computer can also actively read the total length cur _ cap _ len of the occupied space of the current buffer frame, and starts the data transfer from the data buffer unit to the memory of the host computer.
When data is moved, the length of the descriptor is fixed by 16 bytes, and the length of the data frame is determined by the length CapLen field of the buffer area occupied by the data frame in the descriptor; after the data transfer is completed, the data management unit updates the read pointer pr.
When the upper computer stores the captured data frame and the descriptor thereof, the distributed space comprises a pre-reserved 24-byte libpcap file global header, and the type of the libpcap file is nanosecond resolution. The global header, the descriptor and the data frame are stored in a standard libpcap file format and can be directly stored as a libpcap file or analyzed by calling a standard libpcap library.
Claims (5)
1. The time triggered Ethernet data frame capturing and storing device is characterized by comprising:
n data receiving channels, wherein N is more than or equal to 1; the system also comprises a real-time clock unit, a data management unit, a data cache unit, a capture management unit, a PCIE controller and a PCI interface unit;
each data receiving channel comprises a TTE interface unit, an MAC receiving unit, a filtering control unit, a descriptor queue unit and a data frame queue unit;
the MAC receiving unit reads the data frame from the TTE interface unit, sends a signal to the real-time clock unit when the 1 st bit arrives, checks the data frame in the reading process, extracts data frame information including a state mark, a type mark and the actual length of the data frame, and calculates the length of a buffer area occupied by the data frame;
the filtering control unit selectively passes the data frames according to the data frame information provided by the MAC receiving unit and the filtering control information provided by the capturing management unit, and the passed data frames are capturing frames; the filtering control information comprises a frame type enable;
the descriptor queue unit stores descriptors of data frames released by the filtering control unit, wherein the descriptors comprise a second value S and a nanosecond value NS provided by the real-time clock unit, and a state mark, the actual length of the data frames and the length of a buffer area occupied by the data frames provided by the MAC receiving unit;
the data frame queue unit stores the data frames released by the filtering control unit;
a real-time clock unit maintains a time record, which comprises a second value S and a nanosecond value NS;
the data management unit reads data from the data frame queue unit and the descriptor queue unit of the N-path data receiving channels according to a set format, reads cache data from the data cache unit according to a request of the upper computer, and sends the cache data to the upper computer through the PCIE controller and the PCIE interface;
the data caching unit acquires data from the data management unit and performs caching storage;
the data frame and descriptor information thereof provided by the data management unit are collected by the management unit, and an interrupt signal is sent to the upper computer through the PCIE controller and the PCIE interface; the capture management unit is also used for acquiring the filtering control information from an upper computer and sending a transmission data preparation signal to the data management unit;
the PCIE controller and the PCI interface unit provide data interaction between the data management unit and the upper computer and between the capture management unit and the upper computer.
2. The time-triggered ethernet data frame capture, storage device of claim 1, characterized in that:
if the data frame type is an IN frame, the data frame information extracted by the MAC receiving unit also comprises the number of members;
if the data frame type is TT frame or RC frame, the data frame information extracted by the MAC receiving unit also comprises a virtual link identifier field of the data frame;
if the data frame type is a BE frame, the data frame information extracted by the MAC receiving unit further includes a destination MAC address field of the data frame.
3. The method for capturing and storing the time-triggered ethernet data frame according to claim 1 or 2, wherein the method comprises the following steps:
the capture management unit acquires the filtering control information sent by the upper computer through the PCIE controller and the PCI interface unit, and the filtering control information comprises
The overlength error frame reception enable signal overlap _ en,
the non-aligned error frame reception enable signal unalign _ en,
the check error frame reception enable signal checkerr en,
the type length field error frame reception enable signal lener _ en,
reception control enable signals CS _ en, CA _ en, IN _ en, TT _ en, RC _ en, and BE of frame types CS, CA, IN, TT _ en,
the IN frame membership threshold control enable signal IN _ thrld _ en,
the IN frame membership threshold IN _ thrld,
TT, RC and BE frame capture tables enable TT tab en, RC tab en and BE tab en,
TT, RC, and BE frame capture tables TT _ tab, RC _ tab, and BE _ tab,
a destination MAC address constant field RC _ dstmac _ const of the RC frame,
the maximum capture length max _ cap _ len for a single data frame,
the buffered frame number threshold controls the interrupt enable signal cap num int en,
the buffered frame number threshold cap num thrld,
the buffer frame length threshold controls the interrupt enable signal cap _ len _ int _ en,
a buffer frame length threshold value cap _ len _ thrld;
the capture management unit counts the data frames and descriptor information thereof provided by the data management unit in real time, including
Total number of captured frames total _ cap _ num,
the total length of space occupied by the capture frame total _ cap _ len,
the actual total length of the capture frame total _ frame _ len,
the total number of currently buffered frames cur _ cap _ num,
the total length cur _ cap _ len of the occupied space of the current buffering frame;
after the data management unit reads the data frames and the descriptor queue, the capture management unit updates the total number of capture frames, total _ cap _ num, the total length of occupied space of the capture frames, total _ cap _ len, the actual total length of the capture frames, total _ frame _ len, the total number of current buffer frames, cur _ cap _ num and the total length of occupied space of the current buffer frames, cur _ cap _ len;
when the threshold value of the number of buffered frames controls the interrupt enable signal cap _ num _ int _ en to be in an enable state and the total number of currently buffered frames cur _ cap _ num is greater than or equal to the threshold value of the number of buffered frames cap _ num _ thrld,
or
When the buffer frame length threshold controls the interrupt enable signal cap _ len _ int _ en to be in an enable state and the total length cur _ cap _ len of the occupied space of the current buffer frame is greater than or equal to the buffer frame length threshold cap _ len _ thrld,
the capture management unit sends a data transmission preparation signal to the data management unit and simultaneously sends an interrupt signal to the upper computer;
when the upper computer actively reads the total length cur _ cap _ len of the occupied space of the current buffer frame, the capture management unit only sends a transmission data preparation signal to the data management unit;
the MAC receiving unit receives a data frame from the TTE interface and sends a signal to the real-time clock unit when a 1 st bit arrives;
the MAC receiving unit checks whether the data frame has errors or not in the receiving process, and extracts a state mark Fstatus of the data frame, wherein the state mark Fstatus comprises 3 bits; the data frame state corresponding to the data frame state mark Fstatus comprises data correctness, an overlength frame error, a non-aligned frame error, a frame check error and a type length field error;
the MAC receiving unit checks the relevant field of the data frame, determines the type of the data frame,
if the determined data frame type is an IN frame, recording the number of bits 1 IN the membership field of the data frame, namely the membership Fmn;
if the determined data frame type is a TT frame or an RC frame, recording a virtual link identifier field Fvlid of the data frame;
if the determined data frame type is a BE frame, recording a destination MAC address field Fdmac of the data frame;
the MAC receiving unit also records the length of a received data frame, wherein redundant bits of the non-aligned error frame are calculated according to 1 byte;
after the MAC receiving unit receives the data frame, the MAC receiving unit calculates the buffer length CapLen occupied by the data frame released by the filtering control unit:
where len ═ min { fire, max _ cap _ len }, and max _ cap _ len is the maximum capture length of a single data frame, i.e., the maximum number of bytes of data frames retained by the filter control unit;
when receiving the signal sent by the MAC receiving unit, the real-time clock unit provides clock information of the arrival time of the data frame, including a second value Fs and a nanosecond value Fns;
the filtering control unit judges and processes each received frame as follows:
when the data frame state is an overlength frame error, a non-aligned frame error, a frame check error or a type length field error, judging whether a corresponding overlength error frame receiving enabling signal overrule _ en, a non-aligned error frame receiving enabling signal unalign _ en, a check error frame receiving enabling signal checkerr _ en or a type length field error frame receiving enabling signal lener _ en is enabled, if so, accepting the data frame, otherwise, discarding the data frame;
when the data frame state is data correct and the frame type is CS or CA, judging whether a corresponding CS frame receiving control enabling signal CS _ en or CA frame receiving control enabling signal CA _ en is enabled, if so, receiving the data frame, otherwise, discarding the data frame;
when the data frame status is data correct and the frame type is IN,
receiving a data frame if the IN frame reception control enable signal IN _ en is IN an enable state but the IN frame member threshold control enable signal IN _ thrld _ en is disabled;
if the IN frame receiving control enabling signal IN _ en and the IN frame member threshold control enabling signal IN _ thrld _ en are both IN an enabling state, and the member number Fmn is not less than the IN frame member threshold IN _ thrld, receiving the data frame, otherwise, discarding the data frame;
when the data frame status is data correct and the frame type is TT,
if the TT frame reception control enable signal TT _ en is in an enable state, but the TT frame capture table enable signal TT _ tab _ en is in a disable state, receiving a data frame;
if the TT frame receiving control enabling signal TT _ en and the TT frame capturing table enabling signal TT _ tab _ en are both in an enabling state, and the virtual link identifier field Fvlid of the data frame belongs to the TT frame capturing table TT _ tab, receiving the data frame, otherwise, discarding the data frame;
when the data frame state is data correct and the frame type is RC, the processing method of the data frame is the same as the TT frame;
when the data frame status is data correct and the frame type is BE,
if the BE frame reception control enable signal BE _ en is in an enable state, but the BE frame capture table enable signal BE _ tab _ en is disabled, receiving the data frame;
if the BE frame reception control enabling BE _ en and the BE frame capture table enabling signal BE _ tab _ en are both in an enabling state, and the destination MAC address field Fdmac of the data frame belongs to the BE frame capture table BE _ tab, receiving the data frame, otherwise, discarding the data frame;
the descriptor queue unit collects a second value Fs and a nanosecond value Fns provided by the real-time clock unit, a state mark Fstatus and a data frame length Flen of a data frame provided by the MAC receiving unit, and a data frame occupying buffer region length CapLen to form a 16-byte data frame descriptor; the 16-byte data frame descriptor sequentially occupies 4 bytes for a second value Fs from a low address to a high address, a nanosecond value Fns/8 occupies 29 higher bits in the 4 bytes, a state flag Fstatus of a data frame occupies 3 lower bits in the 4 bytes, the length of a data frame Flen occupies 4 bytes, and the length of a data frame occupied buffer CapLen occupies 4 bytes;
the descriptor queue generated by the descriptor queue unit corresponds to the data frame queue output by the filtering control unit, and each data frame in the data frame queue corresponds to a descriptor;
the data management unit manages the data cache unit, organizes the storage space of the data cache unit into a circular queue, and provides a read pointer pr and a write pointer pw;
polling a data frame queue and a descriptor queue of N data receiving channels by a data management unit, if the data frame queue and/or the descriptor queue of a certain data receiving channel is not empty, respectively taking out a descriptor and a data frame from the descriptor queue and the data frame queue of the data receiving channel by the data management unit, storing the descriptor and the data frame to the position of a write pointer pw of a data caching unit according to the sequence of the descriptor before and the data frame after, and then updating the write pointer pw by the data management unit;
when the data management unit receives the data transmission preparation signal, setting the value of the read ending pointer cpw as the value of the current write pointer pw, and determining the data to be transmitted as the data from the read pointer pr to cpw-1;
when the host computer receives the interrupt signal sent by the capturing management unit, the data to be transmitted is transferred from the data cache unit to the memory of the host computer;
the upper computer can also actively read the total length cur _ cap _ len of the occupied space of the current buffer frame and start the data transfer from the data buffer unit to the memory of the upper computer; when data is moved, the length of the descriptor is fixed by 16 bytes, and the length of the data frame is determined by the length CapLen field of the buffer area occupied by the data frame in the descriptor; after the data transfer is completed, the data management unit updates pr.
4. The method of claim 3, wherein the capturing and storing method comprises:
when the upper computer stores the captured data frame and its descriptor,
firstly, allocating a storage space, wherein the storage space comprises 24 bytes which are pre-reserved and is used for storing a global header of a libpcap file, and the type of the libpcap file is nanosecond resolution;
the data frames and descriptors read from the data cache unit are then stored behind the libpcap file global header, such that the global header, descriptors, data frames are organized into a standard libpcap file format.
5. The method of claim 3, wherein the capturing and storing method comprises:
in the receiving process, the MAC receiving unit checks the relevant field of the data frame and determines the type of the data frame, which is specifically as follows:
the destination MAC address constant field is 0 xabadbabbe, the MAC type field is 0x891d, the PCF type field is 0x4, and is marked as CS frame;
the destination MAC address constant field is 0 xabadbabbe, the MAC type field is 0x891d, the PCF type field is 0x8, and is marked as a CA frame;
the destination MAC address constant field is 0 xabadbabbe, the MAC type field is 0x891d, the PCF type field is 0x2, and is marked as an IN frame;
the destination MAC address constant field is 0 xabadbabbe, the MAC type field is 0x88d7, and the field is marked as TT frame;
the destination MAC address constant field is RC _ dstmac _ const, the MAC type field is 0x0800, and the destination MAC address constant field is recorded as an RC frame;
frames with MAC type field not 0x891d, 0x88d7, or 0x0800, or MAC type field 0x0800 and destination MAC address constant field not rc _ dstmac _ const, are denoted as BE frames.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113645299A (en) * | 2021-08-10 | 2021-11-12 | 中煤科工集团重庆研究院有限公司 | Mining mass data rapid buffering method |
| CN113866502A (en) * | 2021-12-02 | 2021-12-31 | 深圳市鼎阳科技股份有限公司 | Spectrum analyzer and data scanning and processing method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2566105A1 (en) * | 2011-09-02 | 2013-03-06 | Honeywell International Inc. | Time triggered ethernet system testing means and method |
| CN103368721A (en) * | 2013-07-23 | 2013-10-23 | 电子科技大学 | Computing method for transparent clock in time-triggered Ethernet |
| EP2705619A1 (en) * | 2011-05-06 | 2014-03-12 | FTS Computertechnik GmbH | Network and method for implementing a high-availability grand master clock |
| CN104717104A (en) * | 2013-12-17 | 2015-06-17 | 中国航空工业集团公司第六三一研究所 | Monitoring method based on time triggering Ethernet |
-
2019
- 2019-11-28 CN CN201911190445.XA patent/CN111147175B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2705619A1 (en) * | 2011-05-06 | 2014-03-12 | FTS Computertechnik GmbH | Network and method for implementing a high-availability grand master clock |
| EP2566105A1 (en) * | 2011-09-02 | 2013-03-06 | Honeywell International Inc. | Time triggered ethernet system testing means and method |
| CN103368721A (en) * | 2013-07-23 | 2013-10-23 | 电子科技大学 | Computing method for transparent clock in time-triggered Ethernet |
| CN104717104A (en) * | 2013-12-17 | 2015-06-17 | 中国航空工业集团公司第六三一研究所 | Monitoring method based on time triggering Ethernet |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113645299A (en) * | 2021-08-10 | 2021-11-12 | 中煤科工集团重庆研究院有限公司 | Mining mass data rapid buffering method |
| CN113645299B (en) * | 2021-08-10 | 2024-05-03 | 中煤科工集团重庆研究院有限公司 | Mining mass data rapid buffering method |
| CN113866502A (en) * | 2021-12-02 | 2021-12-31 | 深圳市鼎阳科技股份有限公司 | Spectrum analyzer and data scanning and processing method thereof |
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