CN111147063A - Anti-irradiation circuit aiming at 28nm three-path fully-isolated triple-modular redundancy - Google Patents
Anti-irradiation circuit aiming at 28nm three-path fully-isolated triple-modular redundancy Download PDFInfo
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Abstract
The embodiment of the invention provides a 28nm three-way fully-isolated triple-modular redundancy anti-irradiation circuit, relates to the technical field of anti-irradiation circuits, and can realize single-particle upset, single-particle multi-bit upset reinforcement and minimum area loss. The circuit comprises: the circuit comprises an intrinsic circuit, a delay circuit 1 and a delay circuit 2, wherein the intrinsic circuit comprises combinational logic, one end of the combinational logic inputs data, the other end of the combinational logic is connected with one end of a register 1, the other end of the register 1 is connected with one end of a big data decision device, and the other end of the big data decision device outputs data; the delay path 1 includes: one end of the deglitch1, one end of the deglitch1 is connected with the other end of the combinational logic, the other end of the deglitch1 is connected with one end of the register 2, and the other end of the register 2 is connected with one end of the big data judger; the delay path 2 includes: and one end of the deglitch2 is connected with the other end of the combinational logic, the other end of the deglitch2 is connected with the register 3, and the other end of the register 3 is connected with one end of the big data decider.
Description
Technical Field
The invention relates to the technical field of anti-irradiation circuits, in particular to a 28nm three-path fully-isolated triple-modular redundancy anti-irradiation circuit.
Background
Generally, methods for designing SEU (single event upset) reinforcement for integrated circuits can be divided into two categories: one is a method of establishing a DICE (dual-interlocked cell) library, and the other is a TMR (triple-modular redundancy).
TMR mainly adopts software method to change the input net list into three parts, thereby achieving the purpose of radiation resistance. However, on a 28nm process node, we need to consider not only SEU but also MBU (single event multi-bit upset), and according to the experience of sensitive node pairs of MBU on silicon, 2um isolation is needed when layout design of layout is performed, however, the area increase of 2um isolation is too large for 28 nm.
In a conventional triple-modular redundancy scheme, referring to fig. 1, 3 circuits of a register and combinational logic are duplicated, and a big data decision unit (for short, the circuit is a three-input single-output unit, output Z, and Z outputs high level when any two of three inputs of a, B, Z.A, B, and C are high, otherwise Z outputs low level, and a module function is Z ═ AB + AC + BC) is added between every two circuits.
When the particle inversion occurs in the combinational logic of the first part, the register of the first part adopts wrong data to one end of a voter (big data judger), and the register of the second part and the third part can still adopt correct data, so that the big data judger outputs a correct value; when the particle inversion occurs in the combinational logic of the second part, the register of the second part adopts wrong data to one end of a voter (big data judger), and the register of the third part of the first part can still adopt correct data, so that the big data judger outputs a correct value; when the particle inversion occurs in the combinational logic of the third part, the register of the third part adopts wrong data and transmits the wrong data to one end of a voter (big data judger), the register of the first part and the second part can still adopt correct data, and therefore the big data judger outputs a correct value;
therefore, three identical circuits are used, the inputs are identical, three outputs are connected to the data decider, when any one circuit in the three circuits is subjected to particle bombardment to generate errors, the outputs of the other two circuits can still keep correct, and the output result passing through the data decider (if 2 inputs are identical, the output is the value) is kept unchanged.
The triple modular redundancy technology in the prior art is that all sensitive nodes are physically isolated by 2um, and no functional unit is arranged between the 2um, so that the triple modular redundancy technology can be accepted for 180nm and 300nm, but wastes area for 28nm, and is not preferable.
How to improve the traditional triple-modular redundancy circuit structure to increase the area a little, realize the perfect combination of single event upset, single event multi-bit upset reinforcement and minimum area loss is the problem to be solved at present.
Disclosure of Invention
In order to solve the technical problem, the invention provides a 28nm three-way fully-isolated triple-modular redundancy anti-irradiation circuit, which realizes single-particle overturning, single-particle multi-bit overturning reinforcement and minimum area loss.
A three-way fully isolated trimodal redundant anti-radiation circuit for 28nm, comprising: the circuit comprises an intrinsic circuit, a delay circuit 1 and a delay circuit 2, wherein the intrinsic circuit comprises combinational logic, one end of the combinational logic inputs data, the other end of the combinational logic is connected with one end of a register 1, the other end of the register 1 is connected with one end of a big data decision device, and the other end of the big data decision device outputs data;
the delay circuit 1 includes: a deglitch1, one end of the deglitch1 is connected with the other end of the combinational logic, the other end of the deglitch1 is connected with one end of a register 2, and the other end of the register 2 is connected with one end of the big data judger;
the delay path 2 includes: a deglitch2, wherein one end of the deglitch2 is connected with the other end of the combinational logic, the other end of the deglitch2 is connected with a register 3, and the other end of the register 3 is connected with one end of the big data decider.
The register 1, the register 2 and the register 3 are registers with the same model and specification.
Preferably, the deglitch1 and the deglitch2 are identical.
Wherein register 1, register 2 and register 3 adopt the data value from the combinational logic and then transfer to the big data decider.
Has the advantages that: according to the 28nm three-path fully-isolated triple-modular redundancy anti-radiation circuit provided by the embodiment of the invention, when particles are turned over on the intrinsic circuit, the register 1 on the intrinsic circuit acquires wrong data and transmits the wrong data to one end of a voter (big data judger), the error can be filtered out due to the fact that the delay circuit 1 and the delay circuit 2 are provided with a deglitch (the delay circuit is essential), and the register 2 and the register 3 on the two paths can acquire correct values, so that the voter (big data judger) outputs correct values; when the data input end of the register 2 of the delay circuit 1 is turned over by particles, the register acquires wrong data and transmits the wrong data to one end of a voter (big data decision device), and the register 1 and the register 3 on the two circuits of the eigencircuit and the delay circuit 2 can acquire correct values, so the voter (big data decision device) outputs correct values; when the data input end of the register 3 of the delay circuit 2 is turned over by particles, the register acquires wrong data and transmits the wrong data to one end of a voter (big data decision device), and the register 1 and the register 2 on the intrinsic circuit and the delay circuit 1 can acquire correct values, so that the voter (big data decision device) outputs correct values; therefore, the circuit structure is one part of combinational logic, three parts of flip-flops are provided, deglitch (a delay circuit which is 1ns in nature and is used for filtering burrs) at the data end is added in front of the flip-flops, and a majority decision device is inserted behind the three parts of flip-flops. Therefore, circuit errors cannot be caused by the overturning of any node, and the three-way full isolation can be realized during the realization, so that the sensitive node pair cannot be overturned at the same time, and the immunity of single event upset is theoretically achieved. For large fan-out and clock trees, three paths of fully isolated triples are also made in the implementation process, and deglitch is additionally arranged on a source head. Because the intrinsic circuit, the delay circuit 1 and the delay circuit 2 have natural isolation function at the position of the layout, the isolation requirement of 2um is well realized, meanwhile, because the other 2 circuits do not copy the combinational logic except the intrinsic circuit, the delay circuit 1 and the delay circuit 2 do not need the area as large as the intrinsic circuit, when the actual realization is carried out, the area of the delay circuit 1 and the delay circuit 2 is smaller than the intrinsic circuit, the arrangement of DFF and the like of the delay circuit 1 and the delay circuit 2 is related, and after the physical position information of the corresponding register in the intrinsic circuit is extracted through software, the corresponding processing is carried out to obtain the position information of the physical position information.
Drawings
FIG. 1 is a schematic diagram of a triple modular redundancy circuit in the prior art;
FIG. 2 is a diagram of a three-way fully-isolated triple-modular redundancy radiation-resistant circuit for 28nm according to an embodiment of the present invention;
fig. 3 is a block diagram of a board according to an embodiment of the present invention.
In the figure: 1-combinational logic of input terminal, 2, 3-degluetch circuit, 4, 5, 6-register, and 7-big data decider.
Detailed Description
The following detailed description of embodiments of the invention refers to the accompanying drawings. Referring to fig. 2, an embodiment of the present invention provides a triple-mode redundant radiation-resistant circuit for 28nm three-way full isolation, including: the circuit comprises an intrinsic circuit, a delay circuit 1 and a delay circuit 2, wherein the intrinsic circuit comprises combinational logic, one end of the combinational logic inputs data, the other end of the combinational logic is connected with one end of a register 1, the other end of the register 1 is connected with one end of a big data decision device, and the other end of the big data decision device outputs data;
the delay circuit 1 includes: a deglitch1, one end of the deglitch1 is connected with the other end of the combinational logic, the other end of the deglitch1 is connected with one end of a register 2, and the other end of the register 2 is connected with one end of the big data judger;
the delay path 2 includes: a deglitch2, wherein one end of the deglitch2 is connected with the other end of the combinational logic, the other end of the deglitch2 is connected with a register 3, and the other end of the register 3 is connected with one end of the big data decider.
Wherein, 1 represents the combinational logic of the input end, and the output of the combinational logic enters the registers 1, 2 and 3 through the intrinsic path, the delay path 1 and the delay path 2; 2, 3 represents a deglitch circuit, which is built by a time delay device, is time delay essentially and has the function of filtering, and can successfully filter single-event upset pulses because the single-event upset pulses are smaller; 4. 5, 6 are registers for taking the values from the combinational logic and then transferring them to the majority decider; and 7 is a big data decider.
The register 1, the register 2 and the register 3 are registers with the same model and specification, and the deglitch1 and the deglitch2 are the same. The register 1, register 2 and register 3 take the data value from the combinational logic and then pass to the big data arbiter.
When the particle inversion occurs on the intrinsic path, the register 1 on the intrinsic path acquires wrong data and transmits the wrong data to one end of the voter (big data decision device), the error can be filtered out because the delay path 1 and the delay path 2 have a deglitch (essentially a delay circuit), and the registers 2 and 3 on the two paths can acquire correct values, so the voter (big data decision device) outputs correct values;
when the data input end of the register 2 of the delay circuit 1 is turned over by particles, the register acquires wrong data and transmits the wrong data to one end of a voter (big data decision device), and the register 1 and the register 3 on the two circuits of the eigencircuit and the delay circuit 2 can acquire correct values, so the voter (big data decision device) outputs correct values;
when the data input end of the register 3 of the delay circuit 2 is turned over by particles, the register acquires wrong data and transmits the wrong data to one end of a voter (big data decision device), and the register 1 and the register 2 on the intrinsic circuit and the delay circuit 1 can acquire correct values, so that the voter (big data decision device) outputs correct values;
therefore, the circuit structure is one part of combinational logic, three parts of flip-flops are provided, deglitch (a delay circuit which is 1ns in nature and is used for filtering burrs) at the data end is added in front of the flip-flops, and a majority decision device is inserted behind the three parts of flip-flops. Therefore, circuit errors cannot be caused by the overturning of any node, and the three-way full isolation can be realized during the realization, so that the sensitive node pair cannot be overturned at the same time, and the immunity of single event upset is theoretically achieved. For large fan-out and clock trees, three paths of fully isolated triples are also made in the implementation process, and deglitch is additionally arranged on a source head. The scheme is realized together with layout, and the effect is good.
Deglitch mainly functions to filter out errors due to particle bombardment. The three-way full-isolation triple-modular redundancy reinforcing scheme is different from the traditional layout implementation, the layout implementation method is shown below, the isolation of the sensitive node pair which is far beyond 2um in physics is guaranteed, and the area cannot be increased aiming at the isolation problem.
Referring to fig. 3, the layout is divided into 3 blocks, the middle B includes (1, 4,7 in fig. 2), the upper a includes (2, 5 in fig. 2), the lower C includes (3, 6 in fig. 2), because the intrinsic circuit, the delay circuit 1, the delay circuit 2 have natural isolation function in the position of the layout, the isolation requirement of 2um is well realized, meanwhile, because besides the intrinsic, the other 2 paths do not copy the combinational logic, so that the delay circuit 1 and the delay circuit 2 do not need the area as large as the intrinsic, in the practical realization, the area of the delay circuit 1 and the delay circuit 2 is smaller than the intrinsic, regarding the placement of DFF, etc. of the delay circuit 1 and the delay circuit 2, after extracting the physical position information of the corresponding register in the intrinsic through software, the corresponding processing is performed to obtain the position information of the physical position information.
The invention does not adopt the traditional method of combining logical triplets, but filters the single event upset by deglitch (intrinsic delay circuit); and the layout is placed in blocks, so that physical full isolation is realized. Points to be protected: the method does not adopt the traditional three parts of combinational logic, only adopts one part of combinational logic, and is added with deglitch (intrinsic delay circuit) and a majority decision device to filter single event upset, and the layout adopts block arrangement to realize physical full isolation.
It will be evident to those skilled in the art that the embodiments of the present invention are not limited to the details of the foregoing illustrative embodiments, and that the embodiments of the present invention are capable of being embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the embodiments being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned. Furthermore, it is obvious that the word "comprising" does not exclude other elements or steps, and the singular does not exclude the plural. Several units, modules or means recited in the system, apparatus or terminal claims may also be implemented by one and the same unit, module or means in software or hardware. The terms first, second, etc. are used to denote names, but not any particular order.
Finally, it should be noted that the above embodiments are only used for illustrating the technical solutions of the embodiments of the present invention and not for limiting, and although the embodiments of the present invention are described in detail with reference to the above preferred embodiments, it should be understood by those skilled in the art that modifications or equivalent substitutions can be made on the technical solutions of the embodiments of the present invention without departing from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims (4)
1. A three-way fully isolated triple-modular redundant anti-radiation circuit for 28nm is characterized in that: the method comprises the following steps: the circuit comprises an intrinsic circuit, a delay circuit 1 and a delay circuit 2, wherein the intrinsic circuit comprises combinational logic, one end of the combinational logic inputs data, the other end of the combinational logic is connected with one end of a register 1, the other end of the register 1 is connected with one end of a big data decision device, and the other end of the big data decision device outputs data;
the delay circuit 1 includes: a deglitch1, one end of the deglitch1 is connected with the other end of the combinational logic, the other end of the deglitch1 is connected with one end of a register 2, and the other end of the register 2 is connected with one end of the big data judger;
the delay path 2 includes: a deglitch2, wherein one end of the deglitch2 is connected with the other end of the combinational logic, the other end of the deglitch2 is connected with a register 3, and the other end of the register 3 is connected with one end of the big data decider.
2. The three-way fully isolated triple-modular redundant radiation-resistant circuit for 28nm of claim 1, wherein: the register 1, the register 2 and the register 3 are registers with the same model and specification.
3. The three-way fully isolated triple-modular redundant radiation-resistant circuit for 28nm of claim 1, wherein: the deglitch1 and deglitch2 are identical.
4. The three-way fully isolated triple-modular redundant radiation-resistant circuit for 28nm of any of claims 1-3, wherein: the register 1, register 2 and register 3 take the data value from the combinational logic and then pass to the big data arbiter.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111914504A (en) * | 2020-07-17 | 2020-11-10 | 中科亿海微电子科技（苏州）有限公司 | Triple-modular redundancy method and device of application circuit |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070262787A1 (en) * | 2006-05-10 | 2007-11-15 | Lucent Technologies Inc. | Soft error tolerant flip flops |
| US8384418B1 (en) * | 2009-09-08 | 2013-02-26 | Xilinx, Inc. | Mitigating the effect of single event transients on input/output pins of an integrated circuit device |
| CN103578567A (en) * | 2013-11-18 | 2014-02-12 | 中国电子科技集团公司第五十八研究所 | Triplication redundancy-based anti-radiation self-refreshing register |
-
2019
- 2019-12-06 CN CN201911239238.9A patent/CN111147063A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070262787A1 (en) * | 2006-05-10 | 2007-11-15 | Lucent Technologies Inc. | Soft error tolerant flip flops |
| US8384418B1 (en) * | 2009-09-08 | 2013-02-26 | Xilinx, Inc. | Mitigating the effect of single event transients on input/output pins of an integrated circuit device |
| CN103578567A (en) * | 2013-11-18 | 2014-02-12 | 中国电子科技集团公司第五十八研究所 | Triplication redundancy-based anti-radiation self-refreshing register |
Non-Patent Citations (1)
| Title |
|---|
| 谭宜涛，等: ""基于关键路径的三模冗余表决器插入算法"" * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111914504A (en) * | 2020-07-17 | 2020-11-10 | 中科亿海微电子科技（苏州）有限公司 | Triple-modular redundancy method and device of application circuit |
| CN111914504B (en) * | 2020-07-17 | 2024-03-15 | 中科亿海微电子科技（苏州）有限公司 | Triple-modular redundancy method and device for application circuit |
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