CN111147060B - Control circuit and semiconductor structure comprising same - Google Patents
Control circuit and semiconductor structure comprising same Download PDFInfo
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- CN111147060B CN111147060B CN201910467133.2A CN201910467133A CN111147060B CN 111147060 B CN111147060 B CN 111147060B CN 201910467133 A CN201910467133 A CN 201910467133A CN 111147060 B CN111147060 B CN 111147060B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 238000004146 energy storage Methods 0.000 claims description 14
- 238000002955 isolation Methods 0.000 claims description 13
- 238000010586 diagram Methods 0.000 description 8
- 230000005669 field effect Effects 0.000 description 6
- 230000015556 catabolic process Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/689—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors with galvanic isolation between the control circuit and the output circuit
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
- H03K17/082—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit
- H03K17/0822—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit in field-effect transistor switches
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention provides a control circuit and a semiconductor structure comprising the same, wherein the control circuit is used for providing an output voltage to a load and comprises a depletion MOSFET, an enhancement MOSFET and a current-voltage converter. The drain of the depletion MOSFET receives an input voltage, and the gate receives a first control voltage. The drain of the enhancement MOSFET receives an input voltage and its source is coupled to a load. The current-voltage converter generates a second control voltage to the gate of the enhancement MOSFET according to the current flowing through the depletion MOSFET. The enhancement MOSFET generates an output voltage for loading according to the second control voltage, and the enhancement MOSFET and the depletion MOSFET are integrated on the same substrate.
Description
Technical Field
The present invention relates to a control circuit, and more particularly, to a control circuit for supplying power to a load, wherein the control circuit may include a semiconductor structure of a depletion type MOSFET and an enhancement type MOSFET.
Background
The transistors are largely divided into bipolar junction transistors (bipolar junction transistor; BJT; FET) and field effect transistors (field effect transistor; FET). The field effect transistor is further classified into a metal oxide semiconductor field effect transistor (metal oxide semiconductor FET; MOSFET) and a Junction Field Effect Transistor (JFET). However, the gate of the junction field effect transistor is prone to leakage current, which results in power loss.
Disclosure of Invention
The invention provides a control circuit for providing an output voltage to a load, and comprises a depletion MOSFET, an enhancement MOSFET and a current-voltage converter. The drain of the depletion MOSFET receives an input voltage, and the gate receives a first control voltage. The drain of the enhancement MOSFET receives an input voltage and its source is coupled to a load. The current-voltage converter generates a second control voltage to the gate of the enhancement MOSFET according to the current flowing through the depletion MOSFET. The enhancement MOSFET generates an output voltage for loading according to the second control voltage, and the enhancement MOSFET and the depletion MOSFET are integrated on the same substrate.
The invention provides a semiconductor structure contained in a control circuit, comprising: a substrate having a first conductivity type; a first well region having the first conductivity type and formed in the substrate; a first doped region having a second conductivity type and formed in the first well region; a second well region having the second conductivity type and formed in the substrate; a second doped region having the second conductivity type and formed in the second well region; and a first gate structure formed on the substrate and overlapping the first and second well regions; wherein the first doped region is used as a source electrode of an enhanced MOSFET, the second doped region is used as a drain electrode of the enhanced MOSFET, and the first gate structure is used as a gate electrode of the enhanced MOSFET.
Drawings
FIG. 1 is a schematic diagram of an operating system of the present invention;
FIG. 2 is a schematic diagram of a control circuit according to one embodiment of the present invention;
FIG. 3 is a schematic diagram of another embodiment of the control circuit of the present invention;
FIG. 4 is a schematic diagram of another embodiment of the control circuit of the present invention;
FIG. 5 is a top view of semiconductor structures of depletion type MOSFETs and enhancement type MOSFETs of the present invention;
fig. 6 is a cross-sectional view of the semiconductor structure of fig. 5 along the portion of dashed line A-A ".
Description of the reference numerals
100: an operating system;
110: a control circuit;
120: a load;
vin: an input voltage;
vout: outputting a voltage;
RV: a reference voltage;
210. 310, 410: a control circuit;
211. 311, 411, DT: depletion type MOSFET;
212. 312, 412, ET: an enhancement MOSFET;
213. 313, 413: a current-voltage converter;
214: an energy storage element;
215: a diode;
216. 315, 419: a grounding end;
CV1, CV2: controlling the voltage;
314. 417, 418: a resistor;
414: a voltage regulator;
415: a comparison circuit;
416: a resistor string;
DV: partial pressure;
500: a substrate;
511-513, 511A, 511B: a well region;
521-525, 521A, 521B, 526A, 526B: a doped region;
531. 532: a gate structure;
541 to 546: an isolation structure;
d1: direction.
Detailed Description
The present invention will be described in more detail with reference to the drawings, wherein the invention is not limited to the embodiments. The present description provides various examples to illustrate the features of various embodiments of the present invention. The arrangement of the elements in the embodiments is illustrative and not intended to limit the invention. In addition, repetition of reference numerals in the embodiments does not imply a correlation between the various embodiments for simplicity of illustration.
FIG. 1 is a schematic diagram of an operating system of the present invention. As shown, the operating system 100 includes a control circuit 110 and a load 120. The control circuit 110 is used for supplying power to the load 120. In the present embodiment, the control circuit 110 receives an input voltage Vin and provides an output voltage Vout to the load 120. In one possible embodiment, the control circuit 110 includes a start-up circuit (start-up circuit) for providing an initial voltage when the power supply is just started.
The load 120 operates according to the output voltage Vout. In one possible embodiment, the output voltage Vout is the supply voltage for the load 120. The present invention is not limited to the circuit architecture of load 120. In one possible embodiment, the load 120 is a direct current-direct current converter (DC-DC converter) for converting the level of the output voltage Vout.
In other embodiments, the load 120 generates a reference voltage RV. The control circuit 110 knows the voltage required by the load 120 according to the reference voltage RV. In one possible embodiment, the control circuit 110 adjusts the output voltage Vout according to the reference voltage RV. For example, when the output voltage Vout is smaller than the reference voltage RV, the control circuit 110 increases the output voltage Vout. When the output voltage Vout is greater than the reference voltage RV, the control circuit 110 decreases the output voltage Vout. When the output voltage Vout is equal to the reference voltage RV, the control circuit 110 maintains the output voltage Vout. By the feedback signal (i.e. the reference voltage RV) provided by the load 120, the control circuit 110 appropriately adjusts the output voltage Vout to provide a stable supply voltage, so that the load 120 operates stably.
Fig. 2 is a schematic diagram of a control circuit according to an embodiment of the present invention. As shown, the control circuit 210 includes a depletion-mode MOSFET (depletion-mode MOSFET) 211, an enhancement-mode MOSFET (enhancement-mode MOSFET) 212, and a current-to-voltage converter (I-V converter) 213.
The drain of the depletion MOSFET211 receives the input voltage Vin, the gate receives a control voltage CV1, and the source is coupled to the current-to-voltage converter 213. In this embodiment, depletion MOSFET211 is an always on (always on) transistor. When the voltage difference between the gate and the source of the depletion MOSFET211 is greater than the threshold voltage (threshold voltage) of the depletion MOSFET211, the depletion MOSFET211 is turned on. Accordingly, the current-to-voltage converter 213 generates a control voltage CV2 according to the current flowing through the depletion MOSFET 211. However, when the voltage difference between the gate and the source of the depletion MOSFET211 is smaller than the threshold voltage of the depletion MOSFET211, the depletion MOSFET211 is not turned on. When the depletion type MOSFET211 is not turned on, no current flows through the depletion type MOSFET211, so that no power loss is caused. In one possible embodiment, the control voltage CV1 is provided by an external device (e.g., the load 120). In this example, the external device uses the control voltage CV1 to turn on or off the depletion MOSFET211 for adjusting the output voltage Vout.
The enhancement MOSFET212 has a drain receiving the input voltage Vin, a gate receiving the control voltage CV2, a source providing the output voltage Vout, and a base coupled to a ground 216. In the present embodiment, the enhancement MOSFET212 generates the output voltage Vout according to the control voltage CV2. The present invention is not limited to the type of enhancement MOSFET 212. In one possible embodiment, the enhancement MOSFET212 is an N-type transistor. In this example, when the control voltage CV2 is high, the enhancement MOSFET212 is turned on. At this time, the enhancement MOSFET212 generates the output voltage Vout from the input voltage Vin. In one possible embodiment, the output voltage Vout may decrease when the control voltage CV2 is insufficient to fully turn on the enhancement MOSFET 212. When the control voltage CV2 fully turns on the enhancement MOSFET212, the output voltage Vout increases. Therefore, by controlling the voltage CV2, a stable output voltage Vout can be obtained. In this embodiment, the enhancement MOSFET212 is a high voltage device with a channel size larger than that of the depletion MOSFET 211.
The current-to-voltage converter 213 generates a control voltage CV2 to the gate of the enhancement MOSFET212 according to the current flowing through the depletion MOSFET 211. The present invention is not limited to the circuit architecture of the current-to-voltage converter 213. Any circuit structure capable of converting current into voltage can be used as the current-voltage converter 213. In the present embodiment, the current-voltage converter 213 includes an energy storage element 214 and a diode 215.
One end of the energy storage element 214 is coupled to the source of the depletion MOSFET211 and the gate of the enhancement MOSFET 212. The other end of the energy storage element 214 is coupled to the ground 216. The energy storage element 214 is charged according to the current flowing through the depletion type MOSFET 211. In this example, the voltage stored in the energy storage element 214 is used as the control voltage CV2. Therefore, even if the depletion MOSFET211 is not turned on, the enhancement MOSFET212 can generate the output voltage Vout according to the control voltage CV2. The present invention is not limited in the type of energy storage element 214. In one possible embodiment, the energy storage element 214 is a capacitor.
The diode 215 is connected in parallel with the energy storage element 214. In this embodiment, the cathode (cathode) of the diode 215 is coupled to the source of the depletion MOSFET211 and the gate of the enhancement MOSFET212, and the anode (anode) is coupled to the ground 216. In one possible embodiment, the ground 216 is configured to receive a ground voltage (ground). In the present embodiment, when the energy storage element 214 stores a sufficient voltage, the enhancement MOSFET212 is turned on to generate the output voltage Vout.
By storing charge in the energy storage element 214, the depletion type MOSFET211 does not need to be continuously turned on, so that power consumption can be reduced. When the depletion MOSFET211 is not turned on, no current flows through the depletion MOSFET211, so that occurrence of leakage current can be avoided. Furthermore, since the switching speed of the depletion type MOSFET211 is high, it is ensured that the energy storage element 214 stores enough charges and the enhancement type MOSFET212 generates the output voltage Vout.
Fig. 3 is a schematic diagram of another embodiment of the control circuit of the present invention. Fig. 3 is similar to fig. 2, except that the current to voltage converter 313 of fig. 3 includes a resistor 314. One end of resistor 314 is coupled to the source of depletion MOSFET 311 and the gate of enhancement MOSFET 312. The other end of resistor 314 is coupled to a ground terminal 315. In this embodiment, the resistor 314 provides a control voltage CV2 according to the current flowing through the depletion MOSFET 311. In this example, the voltage difference across resistor 314 is taken as control voltage CV2.
The enhancement MOSFET 312 generates an output voltage Vout based on the control voltage CV2 and the input voltage Vin. Since the operation principle of the enhancement MOSFET 312 is the same as that of the enhancement MOSFET212 of fig. 2, a detailed description thereof will be omitted. In addition, the operation principle of the depletion MOSFET 311 in fig. 3 is similar to that of the depletion MOSFET211 in fig. 2, and thus will not be described again.
Fig. 4 is a schematic diagram of another embodiment of the control circuit of the present invention. In this example, the control circuit 410 includes a depletion MOSFET 411, an enhancement MOSFET 412, a current-to-voltage converter 413, and a voltage regulator 414. Since the operation of the depletion MOSFET 411 and the enhancement MOSFET 412 is similar to that of the depletion MOSFET211 and the enhancement MOSFET212 of fig. 2, a detailed description thereof will be omitted.
The current-voltage converter 413 generates a control voltage CV2 according to a current flowing through the depletion MOSFET 411. The present invention is not limited to the circuit architecture of the current-to-voltage converter 413. In one possible embodiment, the current-to-voltage converter 413 is similar in circuit architecture to the current-to-voltage converter 213 of fig. 2 or the current-to-voltage converter 313 of fig. 3.
The voltage regulator 415 generates a control voltage CV1 according to the output voltage Vout. In the present embodiment, the voltage regulator 415 includes a comparison circuit 415 and a resistor string 416. The resistor string 416 generates a voltage division DV according to the output voltage Vout. Resistor string 416 includes resistors 417 and 418. One terminal of resistor 417 is coupled to the source of enhancement MOSFET 412. One end of resistor 417 outputs a voltage division DV and is coupled to one end of resistor 418. The other end of resistor 418 is coupled to a ground 419. The comparison circuit 415 compares the divided voltage DV with the reference voltage RV to determine whether the output voltage Vout reaches a target voltage. The comparison circuit 415 generates a control voltage CV1 according to the comparison result of the voltage division DV and the reference voltage RV, so as to adjust the output voltage Vout.
In other embodiments, the comparison circuit 415 directly compares the output voltage Vout with the reference voltage RV. In this example, resistor string 416 may be omitted and comparison circuit 415 is directly coupled to the source of enhancement MOSFET 412. When the output voltage Vout is equal to the reference voltage RV, it indicates that the output voltage Vout has reached the target value. Therefore, the comparison circuit 415 does not turn on the depletion MOSFET 411 by the control voltage CV1. When the output voltage Vout is smaller than the reference voltage RV, the comparison circuit 415 controls the depletion MOSFET 411 by controlling the voltage CV1 to increase the current flowing through the depletion MOSFET 411. In one possible embodiment, the reference voltage RV is provided by an external device (e.g., load 120). In this case, the reference voltage RV may be stored in the external device in advance.
In one possible embodiment, the depletion type MOSFET and the enhancement type MOSFET are integrated on the same substrate to reduce the device occupation space. Fig. 5 is a top view of one possible semiconductor structure of the depletion mode MOSFET and enhancement mode MOSFET of the present invention. In this embodiment, the depletion type MOSFET and enhancement type MOSFET are integrated on the same substrate (substrate) 500.
As shown, a well 511 is formed in the substrate 500. In the present embodiment, the well 511 has a U-shaped structure with an opening facing the direction D1. Doped regions 521 and 522 are formed in the well region 511. In one possible embodiment, the conductivity type of doped region 521 is different from the conductivity type of doped region 522. A gate structure 531 is formed over the substrate 500 and overlaps a portion of the well region 511. In one possible embodiment, the gate structure 531 serves as the gate of the enhancement MOSFET. A well 512 is formed in the substrate 500. Doped region 523 is formed within well 512. In one possible embodiment, the conductivity type of doped region 523 is the same as the conductivity type of doped region 522. A gate structure 532 is formed over the substrate 500 and overlaps the doped regions 525 and 524. In one possible embodiment, the gate structure 532 serves as the gate of a depletion MOSFET.
Fig. 6 is a cross-sectional view of the semiconductor structure of fig. 5 along the portion of dashed line A-A ". The well regions 511A and 511B are disposed in the substrate 500. In one possible embodiment, the substrate 500 has a first conductivity type. In the present embodiment, the well regions 511A and 511B are portions of the well region 511 of FIG. 5. Thus, the well regions 511A and 511B are electrically connected to each other. In one possible embodiment, the well regions 511A and 511B have a first conductivity type. In this example, the doping concentration of the well regions 511A and 511B is higher than that of the substrate 500.
The well 512 is disposed in the substrate 500 and is located between the wells 511A and 511B. In this embodiment, the well 512 has a second conductivity type. The second conductivity type is different from the first conductivity type. For example, the first conductivity type is P-type and the second conductivity type is N-type. In other embodiments, the first conductivity type is N-type and the second conductivity type is P-type.
The doped region 521A is disposed in the well region 511A. In this embodiment, the doped region 521A has a first conductivity type and serves as a base (bulk) of the enhancement MOSFET ET. In one possible embodiment, the doping concentration of the doped region 521A is higher than the doping concentration of the well region 511A. The doped region 522 has the second conductivity type and is formed in the well region 511A. The doping concentration of the doped region 522 is higher than the doping concentration of the well region 512. In this embodiment, doped region 522 serves as the source of the enhancement MOSFET ET. The gate structure 531 is disposed over the substrate 500 and overlaps the partial well regions 511A and 512. In this embodiment, the gate structure 531 serves as the gate of the enhancement MOSFET ET. The doped region 523 has a second conductivity type and is formed in the well 512. The doping concentration of the doped region 523 is higher than the doping concentration of the well 512. In this embodiment, the doped region 523 serves as the drain of the enhancement MOSFET ET.
In addition, the doped region 523 also serves as the drain of the depletion MOSFET DT. As shown, the gate structure 532 is disposed over the substrate 500 and overlaps the partial well regions 512 and 511B. In this embodiment, the gate structure 532 serves as the gate of the depletion MOSFET DT. Doped regions 525 are formed in the substrate 500 and the well region 511. As shown, the doped region 525 has a first portion in the substrate 500 and a second portion in the well 511B. In this embodiment, the doped region 525 has the second conductivity type as a channel of the depletion type MOSFET DT. The doped region 524 is disposed in the well 511B. In this embodiment, the doped region 524 has the second conductivity type and serves as the source of the depletion MOSFET DT. The doped region 521B is disposed in the well 511B. In this embodiment, the doped region 521B has the first conductivity type as the base of the depletion MOSFET DT. Doped regions 521B and 521A are part of doped region 521 of fig. 5.
Since the depletion MOSFET and the enhancement MOSFET share the same doped region (i.e., 523), the number of traces can be reduced. Furthermore, since the depletion type MOSFET is similar to the enhancement type MOSFET, the process complexity is not increased since the depletion type MOSFET has one more doped region (i.e., 525).
In other embodiments, well region 512 further includes a well region 513. Well 513 has a second conductivity type. In this example, the well 512 is a deep well (deep well). In one possible embodiment, the doping concentration of doped region 523 is higher than the doping concentration of well 513. Well 513 has a higher doping concentration than well 512.
In some embodiments, FIG. 6 further shows isolation structures 541-546. The isolation structures 541-546 may be shallow trench isolation (Shallow Trench Isolation; STI) structures or region oxide (Local Oxidation of Silicon; LOCOS) structures. In other embodiments, the well region 512 further includes doped regions 526A and 526B. The doped region 526A is located under the isolation structure 543 and has a first conductivity type for controlling the breakdown voltage of the enhancement MOSFET ET. The doped region 526B is located under the isolation structure 544 and has a first conductivity type for controlling the breakdown voltage of the depletion MOSFET DT. In one possible embodiment, doped region 526A is part of a ring structure (not shown) and doped region 526B is another part of the ring structure. In other words, doped regions 526A and 526B are electrically connected to each other. In the present embodiment, the isolation structure 543 isolates the gate structure 531 from the doped region 523, and the isolation structure 544 isolates the gate structure 532 from the doped region 523. In other embodiments, at least one of doped regions 526A and 526B extends into well region 513.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Furthermore, unless explicitly indicated otherwise, the definition of a word in a general dictionary should be construed as meaning in its articles of related art and should not be interpreted as an ideal state or an excessively formal state.
Although the invention has been described with reference to preferred embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention. For example, the system, apparatus or method of embodiments of the present invention may be implemented in hardware, software or a combination of hardware and software. The scope of the invention is therefore defined by the appended claims.
Claims (10)
1. A control circuit for providing an output voltage to a load, the control circuit comprising:
a depletion MOSFET having a drain receiving an input voltage and a gate receiving a first control voltage;
an enhancement MOSFET having a drain receiving the input voltage and a source coupled to the load; and
a current-to-voltage converter for generating a second control voltage to the gate of the enhancement MOSFET according to the current flowing through the depletion MOSFET;
wherein the enhancement MOSFET generates the output voltage to the load according to the second control voltage;
wherein the gate of the enhancement MOSFET overlaps the gate of the depletion MOSFET by a first well region, and the first well region has a first doped region that serves as the drain of the enhancement MOSFET and the drain of the depletion MOSFET.
2. The control circuit of claim 1, wherein the current-to-voltage converter comprises:
an energy storage element coupled to the source of the depletion MOSFET and the gate of the enhancement MOSFET and charged according to the current flowing through the depletion MOSFET for providing the second control voltage; and
and the diode is connected with the energy storage element in parallel.
3. The control circuit of claim 1, wherein the current-to-voltage converter is a resistor that provides the second control voltage based on current flowing through the depletion mode MOSFET.
4. The control circuit of claim 1, further comprising:
and a voltage regulator for generating the first control voltage according to the output voltage.
5. The control circuit of claim 4, wherein the voltage regulator comprises:
a resistor string for processing the output voltage to generate a divided voltage; and
and a comparison circuit for comparing the divided voltage with a reference voltage to generate the first control voltage.
6. The control circuit of claim 5, wherein the reference voltage is provided by the load.
7. A semiconductor structure included in the control circuit of claim 1, comprising:
a substrate having a first conductivity type;
a second well region having the first conductivity type and formed in the substrate;
a second doped region having a second conductivity type and formed in the second well region;
a first grid structure formed on the substrate and overlapping the first well region and the second well region;
a third well region having the first conductivity type and formed in the substrate;
a third doped region having the second conductivity type and formed in the third well region; and
a second gate structure formed on the substrate and overlapping the second well region and the third well region;
wherein the second doped region acts as the source of an enhancement MOSFET and the first gate structure acts as the gate of the enhancement MOSFET;
wherein the third doped region serves as the source of the depletion MOSFET and the second gate structure serves as the gate of the depletion MOSFET;
wherein the first well region has the second conductivity type and is formed in the substrate, and the first doped region has the second conductivity type.
8. The semiconductor structure of claim 7, further comprising:
a fourth doped region of the second conductivity type, the fourth doped region having a first portion formed in the substrate and a second portion formed in the third well region;
wherein the fourth doped region serves as a channel for the depletion mode MOSFET.
9. The semiconductor structure of claim 8, further comprising:
a fourth well region having the second conductivity type and formed in the first well region, wherein the first doped region is located in the fourth well region;
a first isolation structure for separating the second gate structure and the first doped region;
a second isolation structure for separating the first gate structure and the first doped region;
a fifth doped region having the first conductivity type and formed under the first isolation structure; and
and a sixth doped region having the first conductivity type and formed under the second isolation structure.
10. The semiconductor structure of claim 7, wherein the first conductivity type is P-type and the second conductivity type is N-type.
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| Application Number | Priority Date | Filing Date | Title |
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| TW107139318 | 2018-11-06 | ||
| TW107139318A TWI688192B (en) | 2018-11-06 | 2018-11-06 | Control circuit and semiconductor structure thereof |
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| CN111147060A CN111147060A (en) | 2020-05-12 |
| CN111147060B true CN111147060B (en) | 2023-08-08 |
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| CN201910467133.2A Active CN111147060B (en) | 2018-11-06 | 2019-05-31 | Control circuit and semiconductor structure comprising same |
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| TW (1) | TWI688192B (en) |
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| CN103928464B (en) * | 2014-04-18 | 2015-08-12 | 杭州士兰微电子股份有限公司 | Multiple device and Switching Power Supply |
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2018
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2019
- 2019-05-31 CN CN201910467133.2A patent/CN111147060B/en active Active
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| EP0405407A2 (en) * | 1989-06-29 | 1991-01-02 | Siemens Aktiengesellschaft | Circuit arrangement for controlling a MOSFET with a load connected to its source |
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Also Published As
| Publication number | Publication date |
|---|---|
| TW202019067A (en) | 2020-05-16 |
| TWI688192B (en) | 2020-03-11 |
| CN111147060A (en) | 2020-05-12 |
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