CN111146089B - Fin-shaped structure, semiconductor device and preparation method of semiconductor device - Google Patents
Fin-shaped structure, semiconductor device and preparation method of semiconductor device Download PDFInfo
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- CN111146089B CN111146089B CN201911274412.3A CN201911274412A CN111146089B CN 111146089 B CN111146089 B CN 111146089B CN 201911274412 A CN201911274412 A CN 201911274412A CN 111146089 B CN111146089 B CN 111146089B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
The invention provides a preparation method of a fin-shaped structure, which comprises the following steps: providing a substrate, and sequentially forming a first dielectric layer and a first sacrificial layer on the substrate; forming a plurality of discrete first sacrificial fins based on the first sacrificial layer; forming a second sacrificial layer, wherein the second sacrificial layer covers the top layer and the side wall of the first sacrificial fin and the top layer of the first dielectric layer; removing the second sacrificial layer on the top layer of the first sacrificial fin and the top layer of the first dielectric layer, and forming a second sacrificial fin on the side wall of the first sacrificial fin; forming a second dielectric layer, and flattening to expose the tops of the first sacrificial fin and the second sacrificial fin; removing the first sacrificial fin; forming a third dielectric layer and flattening to expose the top layer of the second sacrificial fin; removing the second sacrificial fin and the first dielectric layer below the second sacrificial fin to form a groove; epitaxially grown and planarized from the bottom of the recess upward to form a fin structure. The invention also provides a fin-shaped structure, a preparation method of a semiconductor device based on the fin-shaped structure and the semiconductor device.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a fin-shaped structure, a semiconductor device and a preparation method thereof.
Background
In three-dimensional semiconductor devices, especially Fin field effect transistors (finfets), fin structures (Fin structures) are usually required to be formed as channel regions of the devices, and at present, the Fin structures are manufactured by photolithography, plasma etching of bulk silicon or two-time patterning or three-time patterning transfer and plasma etching of bulk silicon. The aspect ratio is difficult to exceed 10.
Disclosure of Invention
In view of the above problems, an object of the present invention is to provide a fin structure, a semiconductor device and a method for fabricating the same, wherein the fin structure has a larger aspect ratio, and the semiconductor device has a higher integration level.
In order to achieve the purpose, the invention adopts the following technical scheme: a method for preparing a fin-shaped structure comprises the following steps:
providing a substrate, and sequentially forming a first dielectric layer and a first sacrificial layer on the substrate;
forming a plurality of discrete first sacrificial fins based on the first sacrificial layer;
forming a second sacrificial layer, wherein the second sacrificial layer covers the top layer and the side wall of the first sacrificial fin and the top layer of the first dielectric layer;
removing the second sacrificial layer on the top layer of the first sacrificial fin and the top layer of the first dielectric layer, and forming a second sacrificial fin on the side wall of the first sacrificial fin;
forming a second dielectric layer, and flattening to expose the tops of the first sacrificial fin and the second sacrificial fin;
removing the first sacrificial fin;
forming a third dielectric layer and flattening to expose the top layer of the second sacrificial fin;
removing the second sacrificial fin and the first dielectric layer below the second sacrificial fin to form a groove;
epitaxially grown and planarized from the bottom of the recess upward to form a fin structure.
Preferably, the aspect ratio of the fin structure is greater than or equal to 30.
Preferably, the fin structure has a width of 1 to 40 nanometers.
Preferably, the width of the second sacrificial fin is 1 to 40 nanometers; the width of the first sacrificial fin is 20 to 500 nanometers.
Preferably, the material of the first sacrificial layer includes any one of amorphous silicon, amorphous carbon, or single crystal silicon; the material of the second sacrificial layer includes any one of silicon nitride or silicon dioxide.
Preferably, the material of the first sacrificial layer includes any one of amorphous silicon or monocrystalline silicon; the material of the second sacrificial layer includes any one of silicon nitride, silicon dioxide, or amorphous carbon.
Preferably, the materials of the first dielectric layer, the second dielectric layer and the third dielectric layer include oxides.
Preferably, the fin-shaped structure comprises a material layer of any one of monocrystalline silicon, germanium, silicon germanium, gallium nitride, silicon carbide or an InP compound from top to bottom;
or, any one material layer and strain buffer layer of monocrystalline silicon, germanium, silicon germanium, gallium nitride, silicon carbide or InP compound are included;
or a stack of any two of single crystal silicon, germanium, silicon germanium, gallium nitride, silicon carbide, or an InP compound;
or a stack of any two of single crystal silicon, germanium, silicon germanium, gallium nitride, silicon carbide, or an InP compound and a strain buffer layer.
The invention also provides a fin structure, which comprises a substrate and a plurality of discrete fin structures formed on the substrate, wherein the aspect ratio of the fin structure is greater than or equal to 30.
Preferably, the fin structure has a width of 1 to 40 nanometers.
Preferably, the fin-shaped structure comprises a material layer of any one of monocrystalline silicon, germanium, silicon germanium, gallium nitride, silicon carbide or an InP compound from top to bottom;
or, any one material layer and strain buffer layer of monocrystalline silicon, germanium, silicon germanium, gallium nitride, silicon carbide or InP compound are included;
or, a stack of any two of single crystal silicon, germanium, silicon germanium, gallium nitride, silicon carbide, or an InP compound;
or a stack of any two of single crystal silicon, germanium, silicon germanium, gallium nitride, silicon carbide, or an InP compound and a strain buffer layer.
The invention also provides a preparation method of the semiconductor device, which comprises the following steps:
by utilizing the preparation method of the fin-shaped structure, the fin-shaped structure is prepared and formed along the first direction;
forming a dummy gate over each fin structure along a second direction; forming side walls on two sides of the dummy gate;
etching and growing a source-drain epitaxial layer on the fin-shaped structures on the two sides of the side wall to form a source/drain region;
depositing an oxidation dielectric layer on the formed structure, and carrying out planarization treatment on the oxidation dielectric layer to expose the top of the dummy gate;
removing the false gate; and sequentially forming a gate dielectric layer and a gate in the gate region.
The invention also provides a semiconductor device which is formed by adopting the preparation method of the semiconductor device.
In summary, the height of the fin structure finally formed by the method for manufacturing a fin structure provided by the present invention is determined by the thickness of the first sacrificial layer, and the width of the fin structure is determined by the thickness of the second sacrificial layer, and the thicknesses of the first sacrificial layer and the second sacrificial layer can be effectively controlled by a mature deposition method. Compared with the prior art, the height and the width of the finally formed fin-shaped structure are not limited by the plasma etching process.
Furthermore, the second sacrificial fin and the first medium layer below the second sacrificial fin are removed to form a groove, and then the second sacrificial fin is epitaxially grown and flattened to form a fin-shaped structure, wherein the second sacrificial fin can be made of a material with a large etching selection ratio and loose etching conditions, so that compared with the prior art in which the fin-shaped structure is formed by photoetching and etching bulk silicon, the formation of the fin-shaped structure is not limited by the characteristics of silicon materials.
Therefore, the fin-shaped structure formed by the method for preparing the fin-shaped structure provided by the invention has an aspect ratio which is easy to control, namely, the fin-shaped structure with a larger aspect ratio is easier to form, and the number of the fin-shaped structures integrated on the unit area of the substrate is more on the premise that the cross-sectional areas of the fin-shaped structures are equal, while the semiconductor device adopting the fin-shaped structure provided by the invention has higher integration level.
Drawings
Fig. 1 is a flow chart of a method for fabricating a fin structure according to the present invention;
fig. 2 to 10 are structural change diagrams corresponding to each step in the method for manufacturing a fin structure according to the present invention;
fig. 11 is a flowchart of a method for manufacturing a semiconductor device according to the present invention.
The structure comprises a substrate 10, a first dielectric layer 11, a first sacrificial layer 12, a first sacrificial fin 13, a first sacrificial fin 14, a second sacrificial layer 15, a second sacrificial fin 16, a second dielectric layer 17, a third dielectric layer 18, a groove 18 and a fin structure 19.
Detailed Description
The following describes an embodiment according to the present invention with reference to the drawings.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, however, the present invention may be practiced in other ways than those specifically described herein, and thus the present invention is not limited to the specific embodiments disclosed below.
In the semiconductor field, a substrate is generally etched from top to bottom by using a photolithography and plasma etching process to form a plurality of discrete fin structures, and the aspect ratio of the fin structures is limited by the etching process and the bulk silicon characteristics, so that the aspect ratio of the formed fin structures is difficult to exceed 10.
The invention provides a fin-shaped structure, a semiconductor device and a preparation method thereof, aiming at solving the technical problems that the aspect ratio of the fin-shaped structure is limited when the fin-shaped structure is formed by adopting photoetching and plasma etching processes.
The key of the fin-shaped structure, the semiconductor device and the preparation method thereof provided by the invention is that after a first dielectric layer is formed on a substrate, a mature deposition process can be adopted to deposit a first sacrificial layer, the deposition process is mature, so that the thickness of the first sacrificial layer is not limited by the process any more, the first sacrificial layer with a certain thickness can be deposited according to actual requirements, the thickness of the first sacrificial layer directly influences the height of the fin-shaped structure, the thickness of a second sacrificial layer deposited on the top layer, the side wall and the top layer of the first sacrificial fin and the first dielectric layer by the mature process, or the thickness of the second sacrificial fin formed based on the second sacrificial layer directly influences the width of the finally formed fin-shaped structure, and the thicknesses of the first sacrificial layer and the second sacrificial layer can be formed by the mature deposition process, so that the control is easy, and the width and the height of the fin-shaped structure are not limited by the existing photoetching and etching processes, namely the fin-shaped structure with a large aspect ratio is easy to obtain.
And after depositing a second sacrificial layer on the structure with the first sacrificial fin, removing the second sacrificial layer on the top layer of the first sacrificial fin and the top layer of the first medium layer, forming a second sacrificial fin on the side wall of the first sacrificial fin, filling the second medium layer, flattening, removing the first sacrificial fin, then filling a third medium layer, finally removing the second sacrificial fin and the first medium layer below the second sacrificial fin, forming a groove, growing upwards from the bottom of the groove in an epitaxial growth mode, flattening and forming a fin-shaped structure. The second sacrificial fin can be removed by adopting photoetching and etching processes or by adopting a corrosive liquid removing mode, and the material of the second sacrificial fin can be selected from materials with large photoetching and etching selection ratios and wide etching conditions.
Fig. 1 shows an embodiment of a method for manufacturing a fin structure, which includes the following steps:
s10, providing a substrate, and sequentially forming a first dielectric layer and a first sacrificial layer on the substrate;
referring specifically to fig. 2, a substrate 10 is provided, and a first dielectric layer 11 and a first sacrificial layer 12 are sequentially formed on the substrate 10.
The substrate 10 is any one of group IV, II-V, III-V, and II-VI compound semiconductor materials, such as a silicon substrate, a germanium-silicon substrate, an SOI substrate, or a GOI substrate.
The first dielectric layer 11 is preferably grown on the top layer of the substrate 10 by thermal oxidation, but the first dielectric layer 11 may also be formed by chemical vapor deposition, atomic layer deposition, physical vapor deposition or plasma enhanced chemical vapor deposition.
The material of the first dielectric layer 11 comprises an oxide, preferably silicon dioxide.
The thickness of the first dielectric layer 11 is 3 to 100 angstroms.
The first dielectric layer 11 serves to protect the substrate 10 from damage during subsequent removal of the first sacrificial layer 12 to form the first sacrificial fin 13.
After the first dielectric layer 11 is formed on the substrate 10, it is preferably planarized using a chemical mechanical polishing process, and then a first sacrificial layer 12 is formed on the top layer of the first dielectric layer 11.
The first sacrificial layer 12 may be formed on the top layer of the first dielectric layer 11 by using a chemical vapor deposition method, an atomic layer deposition method, a physical vapor deposition method, or a plasma enhanced chemical vapor deposition method.
The material of the first sacrificial layer 12 includes any one of amorphous silicon, amorphous carbon, or single crystal silicon.
The layer thickness of the first sacrificial layer 12 affects the height of the finally formed fin structure 19, i.e. the thicker the thickness of the first sacrificial layer 12, the higher the height of the finally formed fin structure 19 and vice versa. The thickness of the first sacrificial layer 12 may be determined according to the aspect ratio and the width of the fin structure 19 to be formed, for example, when the aspect ratio of the fin structure 19 is 30.
After the first sacrificial layer 12 is formed, a planarization process is preferably performed by using a chemical mechanical polishing process to ensure that the second sacrificial layer 14 deposited thereon later has a better topography, to ensure that the second sacrificial fin 15 formed on the basis of the second sacrificial layer 14 has a better topography, and to finally ensure that the groove 18 formed after the second sacrificial fin 15 and the first dielectric layer 11 therebelow are removed and the fin-shaped structure 19 formed on the basis of the groove 18 have a better topography.
S11, forming a plurality of discrete first sacrificial fins based on the first sacrificial layer;
referring to fig. 3 specifically, a pattern of the first sacrificial fin 13 may be defined by using photoresist on the top layer of the first sacrificial layer 12, and then the first sacrificial fin 13 may be formed by etching from the top layer of the first sacrificial layer 12 down to the first dielectric layer 11, and removing the photoresist.
The height of the first sacrificial fin 13 is substantially equal to the height of the first sacrificial layer 12, and the width of the first sacrificial fin 13 may be selected to be a suitable value between 20 and 500 nm.
The first sacrificial fins 13 are used to assist in forming the second sacrificial fins 15, and the number of the second sacrificial fins 15 is equal to the number of the fin structures 19 to be formed subsequently, so the number of the second sacrificial fins 15 can be determined according to the number of the fin structures 19 to be formed, for example, when 20 fin structures 19 need to be integrated on the substrate 10, 10 first sacrificial fins 13 need to be formed, then one second sacrificial fin 15 needs to be formed on each of the two side walls of the first sacrificial fins 13, and finally the second sacrificial fin 15 is replaced to form the fin structures 19.
After the number of the first sacrificial fins 13 is determined, the width of the first sacrificial fins 13 that can be formed on the first sacrificial layer 12 with a certain width is substantially determined, and when the number of the first sacrificial fins 13 formed on the first sacrificial layer 12 with a certain width is larger, the width of each first sacrificial fin 13 is relatively narrow, and vice versa.
Theoretically, in order to better carry the second sacrificial layer 14, and the second sacrificial fin 15 formed based on the second sacrificial layer 14, the width of the first sacrificial fin 13 is larger than the thickness of the second sacrificial layer 14.
S12, forming a second sacrificial layer, wherein the second sacrificial layer covers the top layer and the side wall of the first sacrificial fin and the top layer of the first dielectric layer;
referring specifically to fig. 4, a second sacrificial layer 14 is formed on the substrate 10 having the first dielectric layer 11 and the first sacrificial fin 13 using an atomic layer deposition method or a vapor deposition method of plasma enhanced chemistry.
The material of the second sacrificial layer 14 includes any one of silicon nitride, silicon dioxide, or amorphous carbon.
Note that when the first sacrificial layer 12 is amorphous carbon, the second sacrificial layer 14 may be any one of silicon nitride or silicon dioxide, but cannot be amorphous carbon; likewise, when the second sacrificial layer 14 is amorphous carbon, the first sacrificial layer 12 may be any one of amorphous silicon or monocrystalline silicon, but not amorphous carbon. To avoid simultaneous removal of the second sacrificial fin 15 formed on the basis of the second sacrificial layer 14 when the first sacrificial fin 13 is removed.
The thickness of the second sacrificial layer 14 can be selected to be a proper value between 1 nm and 40 nm, and the thickness of the second sacrificial layer 14 affects the width of the finally formed fin-shaped structure 19, i.e., the thicker the thickness of the second sacrificial layer 14, the wider the width of the finally formed fin-shaped structure 19, and vice versa.
The second sacrificial layer 14 is formed to completely cover the top and sidewalls of the first sacrificial fin 13 and the first dielectric layer 11 at the bottom of the first sacrificial fin 13.
S13, removing the top layer of the first sacrificial fin and the second sacrificial layer on the top layer of the first dielectric layer, and forming a second sacrificial fin on the side wall of the first sacrificial fin;
referring to fig. 5 specifically, an anisotropic etching process is used to remove the top layer of the first sacrificial fin 13 and the second sacrificial layer 14 on the top layer of the first dielectric layer 11, the second sacrificial layer 14 on the sidewall of the first sacrificial fin 13 is remained, and finally, the second sacrificial fin 15 is formed on the sidewall of the first sacrificial fin 13.
S14, forming a second dielectric layer, and flattening to expose the tops of the first sacrificial fin and the second sacrificial fin;
referring specifically to fig. 6, preferably, a HARP process deposits a second dielectric layer 16 on the structure having the first dielectric layer 11, the first sacrificial fin 13 and the second sacrificial fin 15, the second dielectric layer 16 can completely cover the first sacrificial fin 13 and the second sacrificial fin 15, and after the second dielectric layer 16 is formed, a chemical mechanical polishing process is performed to planarize the structure so as to expose top layers of the first sacrificial fin 13 and the second sacrificial fin 15.
The material of the second dielectric layer 16 comprises an oxide, preferably silicon dioxide.
S15, removing the first sacrificial fin;
referring specifically to fig. 7, the first sacrificial fin 13 may be removed using an etchant having a high selectivity ratio to the first sacrificial fin 13.
For example, when the material of the first sacrificial fin 13 is amorphous silicon, TMAH etching solution is selected to remove the first sacrificial fin 13.
Of course, a plasma etching process may also be selected to remove the first sacrificial fin 13.
S16, forming a third dielectric layer, and flattening to expose the top layer of the second sacrificial fin;
referring specifically to fig. 8, preferably, the HARP process deposits the third dielectric layer 17 on the structure having the first dielectric layer 11 and the second sacrificial fin 15, the third dielectric layer 17 can completely cover the second sacrificial fin 15, and after the third dielectric layer 17 is formed, the planarization process is performed by using a chemical mechanical polishing process to expose the top layer of the second sacrificial fin 15.
The material of the third dielectric layer 17 comprises an oxide, preferably silicon dioxide.
S17, removing the second sacrificial fin and the first dielectric layer below the second sacrificial fin to form a groove;
referring specifically to fig. 9, the second sacrificial fin 15 may be removed using an etchant having a high selectivity ratio to the second sacrificial fin 15.
Illustratively, when the material of the second sacrificial fin 15 is silicon nitride, the second sacrificial fin 15 is removed by selecting hot phosphoric acid at 250 degrees celsius.
Of course, a plasma etch process may also be selected to remove the second sacrificial fin 15.
After the second sacrificial fin 15 is removed, the first dielectric layer 11 under the second sacrificial fin 15 is removed by using an etching solution having a high selectivity ratio to the first dielectric layer 11.
Illustratively, when the first dielectric layer 11 is silicon dioxide, the first dielectric layer 11 may be removed by using 100 a hydrofluoric acid or BOE etchant diluted by a chemical vapor deposition (100 a).
As an alternative to this step, it is also possible to select an etching liquid with a high selectivity for the substrate 10 to continue etching the substrate 10 downwards, so that the bottom of the groove 18 ends up in the substrate 10.
And S18, epitaxially growing and flattening the substrate upwards from the bottom of the groove to form a fin-shaped structure.
Referring specifically to fig. 10, a high mobility material is selectively epitaxially grown from the bottom of the recess 18 upward, and after the growth is completed, a chemical mechanical polishing process is performed to planarize the high mobility material, so as to form a fin structure 19.
The high mobility material includes any one of single crystal silicon, germanium, silicon germanium, gallium nitride, silicon carbide, or an InP compound.
On the basis of the above embodiment, further, the aspect ratio of the fin structure 19 is greater than or equal to 30.
The invention also provides a fin structure comprising a substrate 10 and a plurality of discrete fin structures 19 formed on the substrate 10, wherein the fin structures 19 have an aspect ratio greater than or equal to 30.
On the basis of the above embodiment, further, the width of the fin structure 19 is 1 to 40 nm.
Further, on the basis of the above embodiment, the material of the fin-shaped structure 19 includes any one of single crystal silicon, germanium, silicon germanium, gallium nitride, silicon carbide, or InP compound.
As another alternative, the fin-shaped structure 19 may further include, from top to bottom, a material layer and a strain buffer layer of any one of single crystal silicon, germanium, silicon germanium, gallium nitride, silicon carbide or an InP compound, or a stack of any two of single crystal silicon, germanium, silicon germanium, gallium nitride, silicon carbide or an InP compound and a strain buffer layer.
The invention also provides a preparation method of the semiconductor device (see fig. 11 in particular), which comprises the following steps:
s20, preparing and forming a fin-shaped structure along a first direction by using a preparation method of the fin-shaped structure;
s21, forming a dummy gate above each fin-shaped structure along a second direction; forming side walls on two sides of the dummy gate;
in this step, the second direction may be perpendicular to the first direction, and an included angle between the first direction and the second direction may also be set according to an actual working condition; specifically, a gate material of a dummy gate is deposited on the fin-shaped structures along a second direction, wherein the gate material may be polysilicon; then, a wet etching process or a dry etching process can be adopted to etch the grid material to form a false grid; then, a side wall material of the side wall is deposited, and then the side wall material is etched to form the side wall by adopting a wet etching process or a dry etching process.
S22, etching and growing a source-drain epitaxial layer on the fin-shaped structures on the two sides of the side wall to form a source/drain region;
in the step, fin-shaped structures on two sides of the dummy gate are etched to form a depressed area; and then growing source and drain region materials in the recessed region of the fin-shaped structure to form a source/drain region.
S23, depositing an oxidation dielectric layer on the formed structure, and flattening the oxidation dielectric layer to expose the top of the dummy gate;
in this step, an oxide dielectric layer is deposited on the formed structure, wherein the oxide dielectric layer may be SiO 2 It is deposited to a thickness sufficient to embed the protruding dummy gate; and then, flattening the oxidation dielectric layer by adopting the processes of chemical mechanical polishing and the like so as to expose the top of the false gate.
And S24, removing the dummy gate, and sequentially forming a gate dielectric layer and a gate in the gate region.
In this step, a dry or wet etching process may be used to remove the dummy gate, and after removing the dummy gate, a gate dielectric layer is deposited in the gate region.
Preferably, the gate dielectric layer is a high dielectric constant layer.
In particular, the high dielectric constant layer may be HfO 2 (hafnium oxide) ZrO 2 (zirconium dioxide), tiO 2 (titanium dioxide) or Al 2 O 3 (alumina) etc. having a relatively low dielectric constantHigh material.
After deposition, a gate is formed on the gate dielectric layer, wherein the gate may be a stack of any one or more materials that meet the requirements, such as TaN (tantalum nitride), tiN (titanium nitride), tiAlC (titanium aluminum carbon), and the like.
The thickness of the gate dielectric layer and the gate can be set as the case may be.
It should be noted that, the steps S20 to S24 can be realized in various ways, and how to realize the steps S20 to S24 is not the main feature of the present invention, so in this specification, only brief description is given so that a person skilled in the art can easily implement the present invention. It is fully contemplated by one of ordinary skill in the art that the above-described structures may be otherwise made.
The present invention also provides a semiconductor device manufactured by the steps S20 to S24.
In summary, the height of the fin structure finally formed by the method for manufacturing a fin structure provided by the present invention is determined by the thickness of the first sacrificial layer, and the width of the fin structure is determined by the thickness of the second sacrificial layer, and the thicknesses of the first sacrificial layer and the second sacrificial layer can be effectively controlled by a mature deposition method. Compared with the prior art, the height and the width of the finally formed fin-shaped structure are not limited by the plasma etching process.
Furthermore, the second sacrificial fin and the first medium layer below the second sacrificial fin are removed to form a groove, and then the fin-shaped structure is formed in a mode of epitaxially growing a high-mobility material, and the second sacrificial fin can be made of a material with a large etching selection ratio and a loose etching condition, so that compared with the fin-shaped structure formed in a mode of photoetching and etching bulk silicon in the prior art, the formation of the fin-shaped structure is not limited by the limitation of silicon material characteristics.
Therefore, the fin-shaped structure formed by the method for preparing the fin-shaped structure provided by the invention has an aspect ratio which is easy to control, namely, the fin-shaped structure with a larger aspect ratio is easier to form, and the number of the fin-shaped structures integrated on the unit area of the substrate is more on the premise that the cross-sectional areas of the fin-shaped structures are equal, while the semiconductor device adopting the fin-shaped structure provided by the invention has higher integration level.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A preparation method of a fin-shaped structure is characterized by comprising the following steps:
providing a substrate, and sequentially forming a first dielectric layer and a first sacrificial layer on the substrate;
forming a plurality of discrete first sacrificial fins based on the first sacrificial layer;
forming a second sacrificial layer covering the top layer and the side wall of the first sacrificial fin and the top layer of the first dielectric layer;
removing the second sacrificial layer on the top layer of the first sacrificial fin and the top layer of the first dielectric layer, and forming a second sacrificial fin on the side wall of the first sacrificial fin;
forming a second dielectric layer, and flattening to expose the tops of the first sacrificial fin and the second sacrificial fin;
removing the first sacrificial fin;
forming a third dielectric layer and flattening to expose the top layer of the second sacrificial fin;
removing the second sacrificial fin and the first dielectric layer below the second sacrificial fin to form a groove;
epitaxially grown and planarized from the bottom of the recess upward to form a fin structure.
2. The method of fabricating the fin structure of claim 1, wherein an aspect ratio of the fin structure is greater than or equal to 30.
3. The method of fabricating the fin structure of claim 1, wherein the fin structure has a width of 1 to 40 nanometers.
4. The method of fabricating the fin structure of claim 1, wherein the second sacrificial fin has a width of 1 to 40 nm; the first sacrificial fin has a width of 20 to 500 nanometers.
5. The method for manufacturing a fin-shaped structure according to claim 1, wherein a material of the first sacrificial layer includes any one of amorphous silicon, amorphous carbon, or single crystal silicon; the material of the second sacrificial layer comprises any one of silicon nitride or silicon dioxide.
6. The method of manufacturing a fin-shaped structure according to claim 1, wherein a material of the first sacrificial layer includes any one of amorphous silicon or single crystal silicon; the material of the second sacrificial layer comprises any one of silicon nitride, silicon dioxide or amorphous carbon.
7. The method of claim 1, wherein the material of the first dielectric layer, the second dielectric layer, and the third dielectric layer comprises an oxide.
8. The method for manufacturing the fin-shaped structure according to claim 1, wherein the fin-shaped structure comprises a material layer of any one of monocrystalline silicon, germanium, silicon germanium, gallium nitride, silicon carbide or InP compound from top to bottom;
or, including any one of the material layer and the strain buffer layer of the monocrystalline silicon, germanium, silicon germanium, gallium nitride, silicon carbide or InP compound;
or, a lamination of any two of the single crystal silicon, germanium, silicon germanium, gallium nitride, silicon carbide, or InP compound;
or a stack of any two of the single crystal silicon, germanium, silicon germanium, gallium nitride, silicon carbide, or an InP compound and the strain buffer layer.
9. A method for manufacturing a semiconductor device, comprising the steps of:
preparing the fin structure along the first direction by using the method for preparing the fin structure as claimed in any one of claims 1 to 8;
forming a dummy gate over each of the fin structures along a second direction; forming side walls on two sides of the dummy gate;
etching and growing a source-drain epitaxial layer on the fin-shaped structures on two sides of the side wall to form a source/drain region;
depositing an oxidation dielectric layer on the formed structure, and carrying out planarization treatment on the oxidation dielectric layer to expose the top of the false gate;
removing the false gate; and sequentially forming a gate dielectric layer and a gate in the gate region.
10. A semiconductor device formed by the manufacturing method of claim 9.
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| US8993419B1 (en) * | 2013-10-03 | 2015-03-31 | Applied Materials, Inc. | Trench formation with CD less than 10 NM for replacement Fin growth |
| CN108022882A (en) * | 2016-11-04 | 2018-05-11 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
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| US8993419B1 (en) * | 2013-10-03 | 2015-03-31 | Applied Materials, Inc. | Trench formation with CD less than 10 NM for replacement Fin growth |
| CN108022882A (en) * | 2016-11-04 | 2018-05-11 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
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