CN111143815A - Data processing equipment and method for verifying integrity thereof - Google Patents

Abstract

The invention discloses a data processing device and a method for verifying the integrity thereof, comprising a plurality of data processing hardware components, wherein the data processing hardware components comprise a first hardware component and one or more remaining hardware components, and the data processing hardware components comprise: the first hardware component is configured to send a challenge to one or more remaining hardware components; each remaining hardware component is configured to receive a respective challenge and process the challenge to generate a response; and the device is configured to verify the integrity of the device based on one or more responses generated by the one or more remaining hardware components.

Description

Data processing equipment and method for verifying integrity thereof

Technical Field

The invention relates to the technical field of data processing, in particular to data processing equipment and a method for verifying the integrity of the data processing equipment.

Background

Currently, most attacks intended to hijack digital devices are focused on software, but as the robustness of security software continues to increase, attacks will be more and more focused on hardware. Hardware-based tampering attacks are known by removing, adding or swapping one or more integrated circuits or other hardware components in a device or simulating them using an external device. Therefore, it will become increasingly important to verify device integrity at the hardware level. Especially in situations where the integrity of the device is critical to protect the revenue stream, such as in conditional access systems, such as in television set-top boxes or digital rights management, but also in all general purpose computing platforms (e.g. individuals). Computers and portable devices such as laptops, cell phones, smart phones, tablets, and the like.

Are increasingly used for sensitive applications including privacy and security issues such as electronic banking or electronic medical care. As the connectivity of almost all everyday devices (the internet of things) increases, the need for hardware integrity checks will become ubiquitous.

Several solutions to ensuring software integrity in data processing systems are known and include various methods to create signatures for software components, such as by storing hashes for each software component and comparing the hashes created from each software component at system boot. These solutions are sometimes facilitated by dedicated security hardware, such as a Trusted Platform Module (TPM) developed by the trusted computing group (TGC). In the Trusted Network Connection (TNC) architecture of TCG, a TPM is used for integrity measurements and remote attestation. During boot, the TPM measures (hashes) all critical software and firmware components of the PC, including the BIOS, boot loader, and operating system kernel, prior to loading. By taking these measurements and storing them on the TPM before the software runs, the measurements are isolated and subsequent modification attempts can be prevented. When the PC is connected to the network, the stored measurement results will be sent to the TNC server, checked against the server's acceptable configuration list, and if a mismatch occurs, quarantined as an infected endpoint.

Disclosure of Invention

The invention proposes a data processing device comprising a plurality of data processing hardware components, said data processing hardware components comprising a first hardware component and one or more remaining hardware components, wherein:

the first hardware component is configured to send a challenge to one or more remaining hardware components;

each remaining hardware component is configured to receive a respective challenge and process the challenge to generate a response; and

the device is configured to verify the integrity of the device based on one or more responses generated by one or more remaining hardware components.

The data processing apparatus comprising a memory storing mission critical information in encrypted form, wherein the apparatus or an aspect of the apparatus requires the mission critical information in decrypted form to be acted upon, and wherein the apparatus is configured to decrypt the encrypted mission critical information using one or more apparatus authentication keys based on the one or more responses generated by the one or more remaining hardware components.

The data processing device, the mission critical information comprising one or more software; firmware required by the device or a function of an aspect of the device; a BIOS; an operating system kernel; a hardware component driver; a boot loader; and a content decryption key.

The data processing apparatus comprising a conditional access apparatus, and the mission-critical information comprising a decryption key for use by the conditional access apparatus to control access to content consumables using the data processing apparatus.

The data processing device, the initial remaining hardware component configured to receive its challenge from the first hardware component; the challenge received by each subsequent remaining hardware component is a response generated by the respective previous remaining hardware component; the last remaining hardware component is configured to send its response to the first hardware component; and the device is configured to verify the integrity of the device using the response received from the last of the remaining hardware components.

The data processing device, each of the remaining hardware components configured to apply a non-transfer function to its challenge to generate its response.

In the data processing device, the rest hardware components are connected with the input of the initial rest hardware component in the chain of the output of the first hardware component in a chain manner;

an input of each subsequent remaining hardware component in the chain connected to an output of a corresponding preceding remaining hardware component in the chain; and an input of a first hardware component connected to an output of a last of the remaining hardware components in the chain, and

wherein the first hardware component is configured to send a challenge to an input of an initial remaining hardware component in the chain; and

one or more responses generated by remaining hardware components at the input of the first hardware component are received.

In the data processing apparatus, each remaining hardware component comprises:

an instruction shift register to receive instructions of a set of instructions, the set of instructions including at least a process challenge instruction to process a challenge and generate a response; and a data shift register for receiving a challenge, corresponding to the process challenge instruction,

wherein each remaining hardware component is configured to:

in a first mode, one bit at a time is shifted from its input to the instruction shift register and one bit at a time is shifted from the instruction shift register to its output;

in a second mode, one bit at a time is shifted from the input to the data shift register, one bit at a time is shifted from the data shift register to the output thereof; and

in a third mode, when a process challenge instruction enters the instruction shift register, the challenge in the data shift register is read, the challenge is processed to generate a response, and the response is written to the data shift register, wherein the first hardware component is a mode configured to control the remaining hardware components:

shifting each instruction into an instruction shift register; transferring the challenge to a data shift register;

causing the remaining hardware components to process the challenge to generate a response; and

shifting the response out of the data shift register to receive one or more responses from the remaining hardware components, an

Wherein the first hardware component is configured to control the modes of all remaining hardware components together on a mode control line common to all remaining hardware components.

A method of verifying the integrity of a data processing apparatus, the method comprising:

sending one or more challenges to a plurality of hardware components;

receiving responses from the plurality of hardware components;

the response is used to verify the integrity of the data processing device,

the method of (a), wherein receiving the response comprises receiving the response from one of the plurality of hardware components, the response from the one of the plurality of hardware components being dependent on a corresponding response component from another of the plurality of hardware components, wherein the plurality of hardware components provide the corresponding responses in sequence, a subsequent hardware component in the sequence receiving the response of a previous hardware component in the sequence as a challenge and generating the response in response to the received challenge, and wherein in response to the received challenge, generating the non-pass function as the received challenge.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to embodiments thereof; it should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. Other systems, methods, and/or features of the present embodiments will become apparent to those skilled in the art upon review of the following detailed description. It is intended that all such additional systems, methods, features and advantages be included within this description, be within the scope of the invention, and be protected by the accompanying claims. Additional features of the disclosed embodiments are described in, and will be apparent from, the detailed description that follows.

The first embodiment is as follows:

a data processing apparatus comprising a plurality of data processing hardware components, the data processing hardware components comprising a first hardware component and one or more remaining hardware components, wherein:

the first hardware component is configured to send a challenge to one or more remaining hardware components;

each remaining hardware component is configured to receive a respective challenge and process the challenge to generate a response; and

the device is configured to verify the integrity of the device based on one or more responses generated by one or more remaining hardware components.

The data processing device comprises a memory for storing mission-critical information in encrypted form,

wherein the device or an aspect of the device requires the mission-critical information in decrypted form to be acted upon, and

wherein the device is configured to decrypt the encrypted mission critical information using one or more device authentication keys based on the one or more responses generated by the one or more remaining hardware components.

The data processing apparatus of (a), wherein the mission critical information comprises one or more software; firmware required by the device or a function of an aspect of the device; a BIOS; an operating system kernel; a hardware component driver; a boot loader; and a content decryption key.

The data processing apparatus of, wherein the data processing apparatus comprises a conditional access apparatus, and the mission-critical information comprises a decryption key to be used by the conditional access apparatus to control access to content consumables using the data processing apparatus. .

The data processing apparatus of, wherein,

the initial remaining hardware component is configured to receive its challenge from the first hardware component;

the challenge received by each subsequent remaining hardware component is a response generated by the respective previous remaining hardware component;

the last remaining hardware component is configured to send its response to the first hardware component; and the device is configured to verify the integrity of the device using the response received from the last of the remaining hardware components.

The data processing device of, wherein each of the remaining hardware components is configured to apply a non-transfer function to its challenge to generate its response.

The data-processing device as described above,

wherein the remaining hardware components are linked in a chain

An input of an initial remaining hardware component in the chain connected to the output of the first hardware component;

an input of each subsequent remaining hardware component in the chain connected to an output of a corresponding preceding remaining hardware component in the chain; and

an input of a first hardware component connected to an output of a last of the remaining hardware components in the chain, and

wherein the first hardware component is configured as

Sending a challenge to an input of an initial remaining hardware component in the chain; and

one or more responses generated by remaining hardware components at the input of the first hardware component are received.

The data processing apparatus described, wherein each remaining hardware component comprises:

an instruction shift register to receive instructions of a set of instructions, the set of instructions including at least a process challenge instruction to process a challenge and generate a response; and

a data shift register for receiving a challenge, corresponding to a process challenge instruction,

wherein each remaining hardware component is configured to:

in a first mode, one bit at a time is shifted from its input to the instruction shift register and one bit at a time is shifted from the instruction shift register to its output;

in a second mode, one bit at a time is shifted from the input to the data shift register, one bit at a time is shifted from the data shift register to the output thereof; and

in a third mode, when a process challenge instruction enters the instruction shift register, the challenge in the data shift register is read, the challenge is processed to generate a response, and the response is written to the data shift register, wherein the first hardware component is a mode configured to control the remaining hardware components:

shifting each instruction into an instruction shift register; transferring the challenge to a data shift register;

causing the remaining hardware components to process the challenge to generate a response; and

shifting the response out of the data shift register to receive one or more responses from the remaining hardware components, an

Wherein the first hardware component is configured to control the modes of all remaining hardware components together on a mode control line common to all remaining hardware components.

The data processing apparatus of, wherein the first hardware component is configured such that:

a challenge to shift bits bit by bit into the data shift register of the initial remaining hardware component;

the initial remaining hardware components are used for processing the inquiry and writing the response of the inquiry into the data shift register;

the responses from the data shift registers of the respective preceding hardware components in the chain are bit-by-bit shifted into the data shift register of each subsequent remaining hardware component in the chain;

each subsequent hardware component processes the response from its corresponding previous hardware component in the data shift register as a challenge to write its response to the data shift register; and

the response of the corresponding data shift register of the last remaining hardware component in the write chain shifts the bit-by-bit to the input of the first hardware component.

The data processing device of claim, wherein the first hardware component is configured such that each subsequent remaining hardware component in the chain does not execute the processing challenge instruction until a corresponding preceding hardware component in the chain has been written. Its response to the data register.

The data processing device of claim, wherein the first hardware component is configured such that each remaining hardware component in the chain executes a process challenge instruction only when the challenge is shifted between the data shift registers of the initial remaining hardware components. The chain and shifts the response of the data shift register written to the last remaining hardware component in the chain to the input of the first hardware component.

The data processing apparatus wherein the physical layer communication interface specification for effecting communication between the initial and remaining hardware components and between the remaining hardware components, each of the remaining hardware components. Including TMS, TCK, TDI and TDO pins and specification compliant state machines.

Example two:

a method of verifying the integrity of a data processing apparatus having a plurality of hardware components, the method comprising:

sending one or more challenges to a plurality of hardware components;

receiving responses from the plurality of hardware components;

the response is used to verify the integrity of the data processing device.

The method of (a), wherein receiving the response comprises receiving the response from one of the plurality of hardware components, the response from the one of the plurality of hardware components being dependent on the corresponding response from another of the plurality of hardware components. A component, wherein the plurality of hardware components provide respective responses in sequence, subsequent hardware components in the sequence receive responses of previous hardware components in the sequence as challenges and generate responses in response to the received challenges, and wherein in response to the received challenges, non-pass-through functionality is generated as the received challenges.

The method of (a), wherein each of the remaining hardware components is configured to apply a non-transfer function to its challenge to generate its response.

In the method, the raw material is subjected to a chemical reaction,

wherein the remaining hardware components are linked in a chain

An input of an initial remaining hardware component in the chain connected to the output of the first hardware component;

an input of each subsequent remaining hardware component in the chain connected to an output of a corresponding preceding remaining hardware component in the chain; and

an input of a first hardware component connected to an output of a last of the remaining hardware components in the chain, and

wherein the first hardware component is configured as

Sending a challenge to an input of an initial remaining hardware component in the chain; and

one or more responses generated by remaining hardware components at the input of the first hardware component are received.

The method of, wherein each remaining hardware component comprises:

an instruction shift register to receive instructions of a set of instructions, the set of instructions including at least a process challenge instruction to process a challenge and generate a response; and

a data shift register for receiving a challenge, corresponding to a process challenge instruction,

wherein each remaining hardware component is configured to:

in a first mode, one bit at a time is shifted from its input to the instruction shift register and one bit at a time is shifted from the instruction shift register to its output;

in a second mode, one bit at a time is shifted from the input to the data shift register, one bit at a time is shifted from the data shift register to the output thereof; and

in a third mode, when a process challenge instruction enters the instruction shift register, the challenge in the data shift register is read, the challenge is processed to generate a response, and the response is written to the data shift register, wherein the first hardware component is a mode configured to control the remaining hardware components:

shifting each instruction into an instruction shift register; transferring the challenge to a data shift register;

causing the remaining hardware components to process the challenge to generate a response; and

shifting the response out of the data shift register to receive one or more responses from the remaining hardware components, an

Wherein the first hardware component is configured to control the modes of all remaining hardware components together on a mode control line common to all remaining hardware components.

The method of (a), wherein the first hardware component is configured such that:

a challenge to shift bits bit by bit into the data shift register of the initial remaining hardware component;

the initial remaining hardware components are used for processing the inquiry and writing the response of the inquiry into the data shift register;

the responses from the data shift registers of the respective preceding hardware components in the chain are bit-by-bit shifted into the data shift register of each subsequent remaining hardware component in the chain;

each subsequent hardware component processes the response from its corresponding previous hardware component in the data shift register as a challenge to write its response to the data shift register; and

the response of the corresponding data shift register of the last remaining hardware component in the write chain shifts the bit-by-bit to the input of the first hardware component.

The method of (a), wherein the first hardware component is configured such that each subsequent remaining hardware component in the chain does not execute the processing challenge instruction until a corresponding preceding hardware component in the chain has been written. Its response to the data register.

The method of (a), wherein the first hardware component is configured such that each remaining hardware component in the chain executes a process challenge instruction only when the challenge is shifted between the data shift registers of the initial remaining hardware components. The chain and shifts the response of the data shift register written to the last remaining hardware component in the chain to the input of the first hardware component.

The method described, wherein the physical layer communication interface specification for implementing the communication between the initial and remaining hardware components and between the remaining hardware components, each remaining hardware component. Including TMS, TCK, TDI and TDO pins and specification compliant state machines.

Although the invention has been described above with reference to various embodiments, it should be understood that many changes and modifications may be made without departing from the scope of the invention. That is, the methods, systems or devices discussed above are examples. Various configurations may omit, substitute, or add various procedures or components as appropriate. For example, in alternative configurations, the methods may be performed in an order different than that described, and/or various stages may be added, omitted, and/or combined. Also, features described with respect to certain configurations may be combined in various other configurations. Different aspects and elements of the configuration may be combined in a similar manner. Furthermore, many of the elements that follow as technology develops are merely examples and do not limit the scope of the disclosure or claims.

Specific details are given in the description to provide a thorough understanding of the exemplary configurations including implementations. However, configurations may be practiced without these specific details, for example, well-known circuits, processes, algorithms, structures, and techniques have been shown without unnecessary detail in order to avoid obscuring the configurations. This description provides example configurations only, and does not limit the scope, applicability, or configuration of the claims. Rather, the foregoing description of the configurations will provide those skilled in the art with an enabling description for implementing the described techniques. Various changes may be made in the function and arrangement of elements without departing from the spirit or scope of the disclosure.

Further, although each operation may describe the operation as a sequential process, many of the operations can be performed in parallel or concurrently. In addition, the order of the operations may be rearranged. There may be other steps in a process. Furthermore, examples of the methods may be implemented by hardware, software, firmware, middleware, code, hardware description languages, or any combination thereof. When implemented in software, firmware, middleware or code, the program code or code segments to perform the necessary tasks may be stored in a non-transitory computer-readable medium such as a storage medium and the described tasks are performed by a processor.

It is intended that the foregoing detailed description be regarded as illustrative rather than limiting, and that it be understood that it is the following claims, including all equivalents, that are intended to define the spirit and scope of this invention. The above examples are to be construed as merely illustrative and not limitative of the remainder of the disclosure. After reading the description of the invention, the skilled person can make various changes or modifications to the invention, and these equivalent changes and modifications also fall into the scope of the invention defined by the claims.

Claims (9)

1. A data processing apparatus comprising a plurality of data processing hardware components, the data processing hardware components comprising a first hardware component and one or more remaining hardware components, wherein:

the first hardware component is configured to send a challenge to one or more remaining hardware components;

each remaining hardware component is configured to receive a respective challenge and process the challenge to generate a response; and

the device is configured to verify the integrity of the device based on one or more responses generated by one or more remaining hardware components.

2. The data processing device of claim 1, comprising a memory storing the mission critical information in encrypted form,

wherein the device or an aspect of the device requires the mission-critical information in decrypted form to be acted upon, and

wherein the device is configured to decrypt the encrypted mission critical information using one or more device authentication keys based on the one or more responses generated by the one or more remaining hardware components.

3. The data processing device of claim 2, wherein the mission critical information comprises one or more software; firmware required by the device or a function of an aspect of the device; a BIOS; an operating system kernel; a hardware component driver; a boot loader; and a content decryption key.

4. A data processing apparatus according to claim 2 or 3, wherein the data processing apparatus comprises a conditional access apparatus and the mission critical information comprises a decryption key for use by the conditional access apparatus to control access to content consumables using the data processing apparatus.

5. The data processing device of any preceding claim, wherein the initial remaining hardware component is configured to receive its challenge from the first hardware component; the challenge received by each subsequent remaining hardware component is a response generated by the respective previous remaining hardware component; the last remaining hardware component is configured to send its response to the first hardware component; and the device is configured to verify the integrity of the device using the response received from the last of the remaining hardware components.

6. The data processing device of claim 5, wherein each of the remaining hardware components is configured to apply a non-transfer function to its challenge to generate its response.

7. A data processing apparatus as claimed in any preceding claim, wherein the remaining hardware components are linked in a chain with the input of the initial remaining hardware component in the chain of outputs of the first hardware component;

an input of each subsequent remaining hardware component in the chain connected to an output of a corresponding preceding remaining hardware component in the chain; and an input of a first hardware component connected to an output of a last of the remaining hardware components in the chain, and

wherein the first hardware component is configured to send a challenge to an input of an initial remaining hardware component in the chain; and

one or more responses generated by remaining hardware components at the input of the first hardware component are received.

8. The data processing device of claim 7, wherein each remaining hardware component comprises:

an instruction shift register to receive instructions of a set of instructions, the set of instructions including at least a process challenge instruction to process a challenge and generate a response; and a data shift register for receiving a challenge, corresponding to the process challenge instruction,

wherein each remaining hardware component is configured to:

in a first mode, one bit at a time is shifted from its input to the instruction shift register and one bit at a time is shifted from the instruction shift register to its output;

in a second mode, one bit at a time is shifted from the input to the data shift register, one bit at a time is shifted from the data shift register to the output thereof; and

in a third mode, when a process challenge instruction enters the instruction shift register, the challenge in the data shift register is read, the challenge is processed to generate a response, and the response is written to the data shift register, wherein the first hardware component is a mode configured to control the remaining hardware components:

shifting each instruction into an instruction shift register; transferring the challenge to a data shift register;

causing the remaining hardware components to process the challenge to generate a response; and

shifting the response out of the data shift register to receive one or more responses from the remaining hardware components, an

Wherein the first hardware component is configured to control the modes of all remaining hardware components together on a mode control line common to all remaining hardware components.

9. A method of verifying the integrity of a data processing apparatus, the method comprising:

sending one or more challenges to a plurality of hardware components;

receiving responses from the plurality of hardware components;

the response is used to verify the integrity of the data processing device,

the method of (a), wherein receiving the response comprises receiving the response from one of the plurality of hardware components, the response from the one of the plurality of hardware components being dependent on a corresponding response component from another of the plurality of hardware components, wherein the plurality of hardware components provide the corresponding responses in sequence, a subsequent hardware component in the sequence receiving the response of a previous hardware component in the sequence as a challenge and generating the response in response to the received challenge, and wherein in response to the received challenge, generating the non-pass function as the received challenge.