CN111143273A - System on chip - Google Patents
System on chip Download PDFInfo
- Publication number
- CN111143273A CN111143273A CN201911101722.5A CN201911101722A CN111143273A CN 111143273 A CN111143273 A CN 111143273A CN 201911101722 A CN201911101722 A CN 201911101722A CN 111143273 A CN111143273 A CN 111143273A
- Authority
- CN
- China
- Prior art keywords
- real
- register
- peripheral
- processor
- address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/14—Time supervision arrangements, e.g. real time clock
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Microcomputers (AREA)
Abstract
The application discloses system on chip, system on chip include through system bus connection's treater and FPGA, wherein, logic resource based on FPGA realizes: a plurality of peripheral real time clocks; the system bus interface is connected with a plurality of peripheral real-time clocks and is connected with the processor through the system bus, and the bus interface is used for mapping peripheral address signals sent by the processor through the system bus into register address signals of the corresponding peripheral real-time clocks so as to operate the corresponding peripheral real-time clocks. By the method, dynamic adjustment can be performed according to the requirements on the functions and the number of the real-time clocks, and the expansibility and the usability of the processor are improved.
Description
Technical Field
The present application relates to the field of on-chip design technologies, and in particular, to a system on a chip.
Background
System on Chip, also known as System on Chip (SoC). From a narrow sense, the method is the chip integration of the core of an information system, and integrates key components of the system on one chip; in a broad sense, the SoC is a micro-miniature system. The academia generally tends to define a SoC as one that integrates a microprocessor, an analog IP core, a digital IP core, and a memory (or off-chip memory control interface) on a single chip, which is typically custom-made or standard product oriented for a particular use.
The real-time clock is an independent timer and is provided with a group of counters for continuous counting, under the corresponding software configuration, the functions of a clock and a calendar can be provided, and if the value of the counter is modified, the current time and date of the system can be reset. The real-time clock internally contains a 32-bit programmable counter for longer-period measurements.
Disclosure of Invention
In order to solve the above problems, the present application provides a system on chip, which can dynamically adjust according to the requirements on the functions and number of real-time clocks, and improve the expansibility and usability of a processor.
The technical scheme adopted by the application is as follows: providing a system on chip, wherein the system on chip comprises a processor and an FPGA which are connected through a system bus, and the logic resource implementation based on the FPGA is as follows: a plurality of peripheral real time clocks; the system bus interface is used for mapping peripheral address signals sent by the processor through the system bus into register address signals of the corresponding peripheral real-time clocks so as to operate the corresponding peripheral real-time clocks.
Wherein, the peripheral hardware real-time clock includes: the internal bus interface is connected with the system bus interface; the controller is connected with the internal bus interface and is used for mapping the register of the real-time clock kernel; the real-time clock kernel is connected with the controller and used for mapping the register of the real-time clock kernel to a corresponding address position in the peripheral address space of the processor, so that the processor realizes the operation of the real-time clock kernel by controlling the register of the corresponding address position in the peripheral address space.
Wherein the real time clock core comprises: the register module is connected with the controller and used for mapping the register address to the controller; the control module is connected with the register module; the clock updating module is connected with the register module and the control module; the synchronization module is connected with the clock updating module; and the timer module is connected with the clock updating module and the synchronization module.
Wherein the timer module is a 32-bit timer module.
The register module comprises a data register, a clock matching register, a current clock reloading register, a control register, an interrupt mask setting and clearing register, an original interrupt state register and an interrupt clearing register.
The internal bus interface comprises a clock signal end, a reset signal end, a chip selection signal end, an address signal end, an enabling signal end, a read-write control signal end, a read data signal end and a write data signal end.
The system bus interface is used for decoding the peripheral address space of the processor and mapping a register of a peripheral real-time clock in the processor.
Wherein, system bus interface includes: the address decoding unit is connected with the system bus and the plurality of peripheral real-time clocks and is used for decoding the peripheral address signals sent by the processor through the system bus into register address signals of the corresponding peripheral real-time clocks; the chip selection unit is connected with the system bus and the plurality of peripheral real-time clocks and used for enabling the corresponding peripheral real-time clocks according to the chip selection information sent by the processor; and the data channel is connected with the system bus and the plurality of peripheral real-time clocks and is used for data interaction between the processor and the plurality of peripheral real-time clocks.
The peripheral real-time clock comprises an internal bus interface, a controller and a real-time clock core which are connected in sequence; the address decoding unit is also used for analyzing the address depth of the register of the real-time clock kernel mapped by the controller and calculating the address space depth required by the register of the real-time clock kernel mapped in the peripheral address space of the processor; and analyzing the number of the pre-configured real-time clock cores, and calculating the external device address space depth of the processor used by the registers of all the real-time clock cores.
The processor is further configured to allocate an address location of each real-time clock core in the address space according to the address depth calculated by the address decoding unit, so that the processor operates the real-time clock cores by operating registers of the real-time clock cores in the address space.
The system on chip provided by the application comprises a processor and an FPGA which are connected through a system bus, wherein the logic resource based on the FPGA is realized as follows: a plurality of peripheral real time clocks; the system bus interface is connected with a plurality of peripheral real-time clocks and is connected with the processor through the system bus, and the bus interface is used for mapping peripheral address signals sent by the processor through the system bus into register address signals of the corresponding peripheral real-time clocks so as to operate the corresponding peripheral real-time clocks. By the mode, the real-time clock is designed by utilizing the programmable characteristic of the FPGA to be used as the external equipment of the processor, the design can be dynamically adjusted according to the requirements on the functions and the number of the real-time clock, the expansibility and the usability of the processor are improved, and the development efficiency of designers is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts. Wherein:
FIG. 1 is a schematic diagram of an embodiment of a system on a chip provided herein;
FIG. 2 is a schematic structural diagram of an embodiment of a peripheral real-time clock provided herein;
FIG. 3 is a schematic diagram of a real-time clock core provided herein;
fig. 4 is a schematic structural diagram of a system bus interface provided in the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the specific embodiments described herein are merely illustrative of the application and are not limiting of the application. It should be further noted that, for the convenience of description, only some of the structures related to the present application are shown in the drawings, not all of the structures. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The terms "first", "second", etc. in this application are used to distinguish between different objects and not to describe a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.
Referring to fig. 1, fig. 1 is a schematic structural diagram of an embodiment of a system on chip provided in the present application, where the system on chip 10 includes a processor 11, a Field-Programmable Gate Array (FPGA) 12, and a system bus 13 connecting the processor 11 and the FPGA 12.
The processor 11 may be a Central Processing Unit (CPU), or an MCU (micro controller Unit), which is not limited herein.
Alternatively, in the present embodiment, the system bus interface 20 and the plurality of peripheral real-time clocks 30 are implemented using the logic resources of the field programmable gate array 12. The system bus interface 20 is connected to the processor 11 via the system bus 13, and is connected to a plurality of peripheral real-time clocks 30.
The system bus interface 20 is configured to map a peripheral address signal sent by the processor through the system bus to a register address signal of a corresponding peripheral real-time clock, so as to operate the corresponding peripheral real-time clock.
Referring to fig. 2, fig. 2 is a schematic structural diagram of an embodiment of a peripheral real-time clock 30 provided in the present application, which includes an internal bus interface 31, a controller 32, and a real-time clock core 33.
Wherein, the internal bus interface 31 is connected with the system bus interface 20; the controller 32 is connected to the internal bus interface 31, and is configured to map registers of the real-time clock core 33; the real-time clock core 33 is connected to the controller 32, and is configured to map a register of the real-time clock core 33 to a corresponding address location in the peripheral address space of the processor 11, so that the processor 11 controls the register of the corresponding address location in the peripheral address space to implement an operation on the real-time clock core 33.
Specifically, the internal bus interface 31 may include a clock signal terminal, a reset signal terminal, a chip select signal terminal, an address signal terminal, an enable signal terminal, a read/write control signal terminal, a read data signal terminal, and a write data signal terminal.
The clock signal terminal and the reset signal terminal may be directly connected to the system bus 13, and are used for obtaining the clock signal and the reset signal from the system bus 13.
The chip select signal terminal, the address signal terminal, the enable signal terminal, the read/write control signal terminal, the read data signal terminal and the write data signal terminal are connected to the system bus interface 20.
The bus clock signal provides the peripheral real-time clock 30 clock signal. A bus reset signal providing a reset signal for the peripheral real time clock 30. When the system bus 13 is connected to a plurality of peripheral real-time clocks 30 by a chip select signal, a certain peripheral real-time clock 30 is selected by the chip select signal. The enable signal enables the peripheral real time clock 30 selected by the chip select signal. The read/write control signal enables the read function or write function of the peripheral real-time clock 30.
Referring to fig. 2 and fig. 3, fig. 3 is a schematic structural diagram of a real-time clock core provided in the present application, where the real-time clock core 33 includes a register module 331, a control module 332, a clock update module 333, a synchronization module 334, and a timer module 335.
The register module 331 is connected to the controller 32, and is configured to map a register address to the controller 32; the control module 332 is connected with the register module 331; the clock updating module 333 is connected with the register module 331 and the control module 332; the synchronization module 334 is connected to the clock update module 333; a timer module 335 is connected to the clock update module 333 and the synchronization module 334.
The register module 331 is configured to implement writing and reading of signals, the control module 332 is configured to control the clock updating module 333 and obtain state information of the clock updating module 333, and the clock updating module 333 and the synchronization module 334 are configured to synchronously update the latest clock and maintain a real-time clock. Timer module 335 may be a 32-bit timer module comprising a 32-bit programmable timer that provides a countdown clock function, which generates a real time clock interrupt to reload the real time clock when the countdown time is zero. The rtc core 33 includes an interrupt signal, which is coupled to an interrupt controller interrupt signal of the processor 11 core and generates an interrupt request signal requesting the processor 11 core to interrupt processing when the 32-bit timer counts down to zero.
Optionally, in an embodiment, the register module 331 may include a data register, a clock matching register, a current clock override register, a control register, an interrupt mask set and clear register, a raw interrupt status register, and an interrupt clear register.
Referring to fig. 4, fig. 4 is a schematic structural diagram of a system bus interface 20 provided in the present application, the system bus interface being used for decoding a peripheral address space of a processor 11 and mapping registers of a peripheral real-time clock 30 in the processor 11.
The system bus interface 20 includes an address decoding unit 21, a chip selecting unit 22, and a data channel 23. The address decoding unit 21 is connected to the system bus 13 and the plurality of peripheral real-time clocks 30, and is configured to decode a peripheral address signal sent by the processor 11 through the system bus 13 into a register address signal of the corresponding peripheral real-time clock 30; the chip selection unit 23 is connected to the system bus 13 and the plurality of peripheral real-time clocks 30, and is configured to enable the corresponding peripheral real-time clocks 30 according to the chip selection information sent by the processor 11; the data channel 22 connects the system bus 13 and the plurality of peripheral real-time clocks 30 for data interaction between the processor 11 and the plurality of peripheral real-time clocks 30.
With reference to fig. 2, optionally, the address decoding unit 21 is further configured to analyze the address depth of the register 331 of the rtc core 33 mapped by the control unit 32, and calculate the address space depth required for mapping the register 331 of one rtc core 33 in the peripheral address space of the processor 13; and analyzing the pre-configured number of rtc cores 33 to calculate the depth of the external device address space of the processor 11 used by the registers 331 of all the rtc cores 33 in common.
The processor 11 is further configured to allocate an address location of each real-time clock core 33 in the address space according to the address depth calculated by the address decoding unit 21, so that the processor 11 operates the real-time clock core 33 by operating the register 331 of the real-time clock core 33 in the address space.
The above process is described below with reference to fig. 1 to 4 by way of a specific example:
1. the address decoder 21 first performs address segmentation on the peripheral address space of the processor 11 according to the address depth of the register 331 in the real-time clock core 33 of the connected peripheral real-time clock 30, and forms a mapping relationship between the address segmentation and the register address, and the address decoder 21 further sends the mapping relationship to the processor 11.
2. The processor 11 sends the peripheral address signal to the system bus 13, and the address decoder 21 obtains the peripheral address signal from the system bus 13, and maps the peripheral address signal to the address signal of the register 331 in the real-time clock core 33 in the corresponding peripheral real-time clock 30, and further sends the address signal to the corresponding peripheral real-time clock 30.
3. Further, the processor 11 sends a chip select signal to the system bus 13, and the chip select unit 23 obtains the chip select signal from the system bus 13 and enables the peripheral real-time clock 30 corresponding to the chip select signal.
Here, the steps 2 and 3 are not limited to the execution order, and may be executed simultaneously.
4. The enabled peripheral real-time clock 30 can obtain a control instruction, such as a read data instruction, a write data instruction, etc., sent by the processor 11, so that the processor 11 operates the peripheral real-time clock 30.
Different from the prior art, the system on chip provided by this embodiment includes a processor and an FPGA connected by a system bus, where the logic resource implementation based on the FPGA: a plurality of peripheral real time clocks; the system bus interface is connected with a plurality of peripheral real-time clocks and is connected with the processor through the system bus, and the bus interface is used for mapping peripheral address signals sent by the processor through the system bus into register address signals of the corresponding peripheral real-time clocks so as to operate the corresponding peripheral real-time clocks. By the mode, the real-time clock is designed by utilizing the programmable characteristic of the FPGA to be used as the external equipment of the processor, the design can be dynamically adjusted according to the requirements on the functions and the number of the real-time clock, the expansibility and the usability of the processor are improved, and the development efficiency of designers is improved.
In the several embodiments provided in the present application, it should be understood that the disclosed method and apparatus may be implemented in other manners. For example, the above-described device embodiments are merely illustrative, and for example, the division of the modules or units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The above description is only for the purpose of illustrating embodiments of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made according to the content of the present specification and the accompanying drawings, or which are directly or indirectly applied to other related technical fields, are also included in the scope of the present application.
Claims (10)
1. A system on a chip, comprising a processor and an FPGA connected by a system bus, wherein the logic resources based on the FPGA implement:
a plurality of peripheral real time clocks;
and the system bus interface is used for mapping peripheral address signals sent by the processor through the system bus into corresponding register address signals of the peripheral real-time clocks so as to operate the corresponding peripheral real-time clocks.
2. The system-on-chip of claim 1,
the peripheral real-time clock includes:
the internal bus interface is connected with the system bus interface;
the controller is connected with the internal bus interface and is used for mapping the register of the real-time clock kernel;
and the real-time clock kernel is connected with the controller and is used for mapping the register of the real-time clock kernel to a corresponding address position in a peripheral address space of the processor, so that the processor realizes the operation of the real-time clock kernel by controlling the register of the corresponding address position in the peripheral address space.
3. The system-on-chip of claim 2,
the real-time clock core includes:
the register module is connected with the controller and used for mapping a register address to the controller;
the control module is connected with the register module;
the clock updating module is connected with the register module and the control module;
the synchronization module is connected with the clock updating module;
and the timer module is connected with the clock updating module and the synchronization module.
4. The system-on-chip of claim 3,
the timer module is a 32-bit timer module.
5. The system-on-chip of claim 3,
the register module comprises a data register, a clock matching register, a current clock reloading register, a control register, an interrupt mask setting and clearing register, an original interrupt state register and an interrupt clearing register.
6. The system-on-chip of claim 2,
the internal bus interface comprises a clock signal end, a reset signal end, a chip selection signal end, an address signal end, an enable signal end, a read-write control signal end, a read data signal end and a write data signal end.
7. The system-on-chip of claim 1,
the system bus interface is used for decoding the peripheral address space of the processor and mapping the register of the peripheral real-time clock in the processor.
8. The system-on-chip of claim 7,
the system bus interface includes:
the address decoding unit is connected with the system bus and the plurality of peripheral real-time clocks and is used for decoding peripheral address signals sent by the processor through the system bus into corresponding register address signals of the peripheral real-time clocks;
the chip selection unit is connected with the system bus and the plurality of peripheral real-time clocks and used for enabling the corresponding peripheral real-time clocks according to the chip selection information sent by the processor;
and the data channel is connected with the system bus and the plurality of peripheral real-time clocks and is used for data interaction between the processor and the plurality of peripheral real-time clocks.
9. The system-on-chip of claim 8,
the peripheral real-time clock comprises an internal bus interface, a controller and a real-time clock kernel which are connected in sequence;
the address decoding unit is further configured to analyze an address depth of a register of the real-time clock core mapped by the controller, and calculate an address space depth required for mapping the register of the real-time clock core in an external address space of the processor; and analyzing the number of the pre-configured real-time clock cores, and calculating the external device address space depth of the processor used by the registers of all the real-time clock cores.
10. The system-on-chip of claim 9,
the processor is further configured to allocate an address location of each real-time clock core in an address space according to the address depth calculated by the address decoding unit, so that the processor operates the real-time clock cores by operating registers of the real-time clock cores in the address space.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911101722.5A CN111143273B (en) | 2019-11-12 | 2019-11-12 | System on chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911101722.5A CN111143273B (en) | 2019-11-12 | 2019-11-12 | System on chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111143273A true CN111143273A (en) | 2020-05-12 |
| CN111143273B CN111143273B (en) | 2023-07-04 |
Family
ID=70517043
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911101722.5A Active CN111143273B (en) | 2019-11-12 | 2019-11-12 | System on chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111143273B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112039745A (en) * | 2020-09-17 | 2020-12-04 | 广东高云半导体科技股份有限公司 | CAN bus communication control system and communication system |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7020231B1 (en) * | 2004-10-21 | 2006-03-28 | Delphi Technologies, Inc. | Technique for creating extended bit timer on a time processing unit |
| US20080148087A1 (en) * | 2006-12-19 | 2008-06-19 | Samsung Electronics Co., Ltd. | Apparatus and method of time keeping for non-real-time operating system |
| CN102254218A (en) * | 2011-07-02 | 2011-11-23 | 广西工学院 | Counter device composed of Advanced RISC Machine (ARM) and Field Programmable Gate Array (FPGA), and implementation method thereof |
| CN102323786A (en) * | 2011-07-01 | 2012-01-18 | 广西工学院 | Timer device comprising advanced reduced instruction set computer machine (ARM) and field programmable gate array (FPGA) and implementation method thereof |
| CN106525231A (en) * | 2016-10-28 | 2017-03-22 | 中国科学技术大学 | Multi-photon coincidence counter based on programmable logic device |
-
2019
- 2019-11-12 CN CN201911101722.5A patent/CN111143273B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7020231B1 (en) * | 2004-10-21 | 2006-03-28 | Delphi Technologies, Inc. | Technique for creating extended bit timer on a time processing unit |
| US20080148087A1 (en) * | 2006-12-19 | 2008-06-19 | Samsung Electronics Co., Ltd. | Apparatus and method of time keeping for non-real-time operating system |
| CN102323786A (en) * | 2011-07-01 | 2012-01-18 | 广西工学院 | Timer device comprising advanced reduced instruction set computer machine (ARM) and field programmable gate array (FPGA) and implementation method thereof |
| CN102254218A (en) * | 2011-07-02 | 2011-11-23 | 广西工学院 | Counter device composed of Advanced RISC Machine (ARM) and Field Programmable Gate Array (FPGA), and implementation method thereof |
| CN106525231A (en) * | 2016-10-28 | 2017-03-22 | 中国科学技术大学 | Multi-photon coincidence counter based on programmable logic device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112039745A (en) * | 2020-09-17 | 2020-12-04 | 广东高云半导体科技股份有限公司 | CAN bus communication control system and communication system |
| CN112039745B (en) * | 2020-09-17 | 2021-06-22 | 广东高云半导体科技股份有限公司 | CAN bus communication control system and communication system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111143273B (en) | 2023-07-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101739283B (en) | Computer and method for virtual system to directly access computer hardware | |
| US6212625B1 (en) | General purpose dynamically programmable state engine for executing finite state machines | |
| CN113849433B (en) | Execution method and device of bus controller, computer equipment and storage medium | |
| CN102981892A (en) | Centralized device virtualization layer for heterogeneous processing units | |
| US20040117743A1 (en) | Heterogeneous multi-processor reference design | |
| EP0355463B1 (en) | Timer channel with multiple timer reference features | |
| CN103460202A (en) | Facilitating, at least in part, by circuitry, accessing of at least one controller command interface | |
| CN110806997B (en) | System on chip and memory | |
| CN112835846A (en) | System on chip | |
| CN107562496A (en) | A kind of method and device of page configuration and page presentation | |
| US6611796B1 (en) | Method and apparatus for combining memory blocks for in circuit emulation | |
| CN111143273A (en) | System on chip | |
| CN107660282B (en) | Handling partition resets in multi-root systems | |
| US6678803B2 (en) | Method and device to use memory access request tags | |
| CN111666557B (en) | Apparatus and method for software-enabled access to protected hardware resources | |
| US20170139726A1 (en) | Serial device emulator using two memory levels with dynamic and configurable response | |
| US20140181491A1 (en) | Field-programmable module for interface bridging and input/output expansion | |
| WO2013148439A1 (en) | Hardware managed allocation and deallocation evaluation circuit | |
| CN107533443B (en) | Providing multiple roots in a semiconductor device | |
| US20040236923A1 (en) | Variable sized flash memory in PCI | |
| CN105528300A (en) | DDR memory controller and access monitoring method thereof | |
| CN117480498A (en) | Dynamically provisioning PCIe devices for bare metal servers at run-time | |
| US9442788B2 (en) | Bus protocol checker, system on chip including the same, bus protocol checking method | |
| CN117555669A (en) | Resource scheduling method, device, computing device cluster, medium and program product | |
| CN112882960A (en) | Data acquisition method and device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |