CN111143238A - Data erasing method and system based on eFlash memory chip - Google Patents
Data erasing method and system based on eFlash memory chip Download PDFInfo
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- CN111143238A CN111143238A CN201911375135.5A CN201911375135A CN111143238A CN 111143238 A CN111143238 A CN 111143238A CN 201911375135 A CN201911375135 A CN 201911375135A CN 111143238 A CN111143238 A CN 111143238A
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
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- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
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- G06F11/1446—Point-in-time backing up or restoration of persistent data
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Abstract
The invention discloses a data erasing method and a system based on an eFlash memory chip, wherein the method comprises the following steps: acquiring application data; calling a writing interface, and judging whether a target erasing unit needs to start balanced exchange or not; when the balance exchange does not need to be started, the application data is directly written into the target erasing unit; when the equilibrium exchange needs to be started, an available exchange unit is obtained, and application data is written into the available exchange unit, wherein the method for judging whether the target erasing unit needs to start the equilibrium exchange comprises the following steps: calculating to obtain the height of a reference erasing balance line; calculating to obtain the erasing balance height of the target erasing unit; if the erase-verify height is greater than or equal to the reference erase-verify line height, then a verify swap is initiated. On the premise of ensuring that the eFlash memory chip has higher erasing times, the invention effectively reduces the erasing performance overhead additionally generated by introducing the balanced erasing algorithm and improves the efficiency of searching the balanced exchange target object.
Description
Technical Field
The invention relates to the technical field of data storage, in particular to a data erasing method and a data erasing system based on an eFlash storage chip.
Background
The embedded system is mainly applied to the control field in the past, and the requirement on data storage is not very high. With the continuous development of information technology, embedded technology is widely applied in many fields, the amount of data information to be stored in an embedded system is continuously increased, the requirements on data storage and management are higher and higher, and the requirements of embedded equipment on volume, power consumption, shock resistance and the like are more strict. The Flash (a general term for Flash as a storage medium in an embedded device) memory has the characteristics of small volume, large storage capacity, low energy consumption, high cost performance and the like, and is more suitable for storing data in an embedded system compared with the traditional storage medium. Therefore, the eFlash memory has become one of the storage media mainly used in the embedded system. The eFlash is based on a mode of erasing first and then writing, the erasing frequency of each erasing unit is limited, and the life cycle of the whole eFlash can be influenced by blocks which are abraded due to excessive erasing frequency.
In order to solve the above problems, the first conventional solution is to erase and write a plurality of spare sectors instead of the worn sectors, and when a single spare sector is worn, the spare sector is replaced with another unworn spare sector to write, so as to increase the number of times of the flash erase and write. However, when the method is used for frequently writing the fixed sector, the non-spare sector is easily caused to far fall short of the service life limit, and the technical defects that the fixed sector and the spare sector are damaged, so that the device cannot be used due to too many bad blocks occur.
The second existing solution is to divide the storage units according to the storage capacity of the eFlash chip and the number of sectors, sequentially write the statistical data and the mapping data into the different storage units corresponding to the sectors, query the management information of the erasure unit before each erasure, calculate the average value of the logical write times and the average value, the root-mean-square error, the maximum value and the minimum value of the actual write times of the physical sub-sectors for the management information of all the erasure units, and thus determine whether the balance exchange is needed. The method solves the technical defects in the first solution, but the method has the technical defect of low execution efficiency because all erasing units are read, calculated and judged in each erasing process.
The existing third solution is to divide an erasure unit state bitmap table and a DATA sector based on a polling algorithm of an idle erasure unit, so as to implement the mapping relationship of the erasure unit. And effectively scheduling the DATA sector by a search algorithm of the idle erasing unit when DATA is written each time, and then writing the target erasing unit by a mapping relation so as to improve the erasing times. This method solves the technical drawback of the second solution, but it needs to search for an idle erase unit by polling the bit map table before each erase and write, and the efficiency of searching for the target object of the balanced exchange is relatively low.
Therefore, there is a need to provide an improved technical solution to overcome the above technical problems in the prior art.
Disclosure of Invention
In order to solve the technical problems, the invention provides a data erasing method and a data erasing system based on an eFlash memory chip, which effectively reduce the erasing performance overhead additionally generated by introducing a balanced erasing algorithm and improve the efficiency of searching a balanced exchange target object on the premise of ensuring that the eFlash memory chip has higher erasing times.
The data erasing method based on the eFlash memory chip provided by the invention comprises the following steps: acquiring application data; calling a writing interface, starting a balance management mechanism, and judging whether a target erasing unit needs to start balance exchange; when the balance exchange does not need to be started, ending the balance management mechanism, and directly writing the application data into the target erasing unit; when the equilibrium exchange needs to be started, an available exchange unit is obtained, and the application data is written into the available exchange unit, wherein the method for judging whether the target erasing unit needs to start the equilibrium exchange comprises the following steps: acquiring the recorded balance round number and each round of balance erasing times of the eFlash memory chip, and calculating to obtain the height of a reference erasing balance line; acquiring recorded erased times and balanced round numbers of the target erasing unit, and calculating to obtain an erasing balance height of the target erasing unit; and comparing the erasure balance height with the reference erasure balance line height, and starting balance exchange if the erasure balance height is greater than or equal to the reference erasure balance line height.
Preferably, the height of the reference erasure-and-writing equalization line is equal to the product of the number of equalization rounds and the number of equalization rounds of each round, and the erasure-and-writing equalization height of the target erasure-and-writing unit is equal to the product of the number of erased rounds and the number of equalized rounds.
Preferably, writing the application data directly into the target erasure unit or writing the application data into the available swap unit further comprises: returning the writing state of the application data; judging whether the target erasing unit or the available exchange unit is damaged or not according to the writing state, and if the data is successfully written, indicating that the target erasing unit or the available exchange unit is not damaged; if the data writing fails, it indicates that the target erasure unit or the available swap unit is damaged, and the rest of the erasure units are about to be damaged.
Preferably, when it is necessary to start the equalization switching, acquiring an available switching unit, and writing the application data into the available switching unit includes: judging whether the current exchange unit is available; if the current exchange unit is available, starting balanced exchange, and writing the application data into the current exchange unit; and if the current exchange unit is unavailable, updating the current exchange unit, starting balanced exchange after the updating is successful, and writing the application data into the available exchange unit.
Preferably, the determining whether the current switching unit is available comprises: acquiring recorded erased times and balanced round numbers of the current exchange unit, and calculating to acquire an erased balanced height of the current exchange unit; comparing the erasing balance height of the current switching unit with the size of the reference erasing balance line height, and if the erasing balance height of the current switching unit is smaller than the reference erasing balance line height, the current switching unit is available; and if the erasure balance height of the current switching unit is greater than or equal to the reference erasure balance line height, the current switching unit is unavailable.
Preferably, the height of the reference erasure equalizing line is equal to the product of the number of equalizing rounds and the number of equalizing erasures of each round.
Preferably, updating the current switching unit comprises: judging whether the current exchange unit is the last erasing unit or not; if the current exchange unit is not the last erasing unit, sequentially judging whether the next erasing unit is available one by one to obtain an available exchange unit; after the available switching units are obtained, the information management table is updated.
Preferably, updating the current switching unit comprises: judging whether the current exchange unit is the last erasing unit or not; if the current exchange unit is the last erasing unit, adding one to the current balancing round number, and entering the next round of balancing; the first erasing unit is planned to be the current exchange unit; judging whether the proposed current exchange unit is available, if so, taking the proposed current exchange unit as an available exchange unit, and updating an information management table; if the proposed current exchange unit is unavailable, sequentially judging whether the next erasing unit is available one by one to obtain an available exchange unit; after the available switching units are obtained, the information management table is updated.
Preferably, whether the current swap unit is the last erasure unit is determined according to the address of the erasure unit corresponding to the current swap unit.
Preferably, initiating the equalization exchange comprises: carrying out data exchange on the erasing units mapped between the balancing object and the balanced object; and after the data exchange of the erasing units mapped between the balancing object and the balanced object is finished, the corresponding mapping units between the balancing object and the balanced object exchange data, wherein the balancing object comprises the target erasing units, and the balanced object comprises the available exchanging units.
Preferably, the data exchange of the erasure units mapped between the equalization object and the equalized object comprises: the erasing units mapped between the balancing object and the balanced object exchange data of a storage unit; the erasing units mapped between the balancing object and the balanced object exchange mapping unit addresses.
Preferably, the data exchange of the corresponding mapping unit between the balancing object and the balanced object includes: and the corresponding mapping unit between the balancing object and the balanced object exchanges pointed erasing unit addresses.
Preferably, the updating of the information management table further includes: performing power failure protection when updating data; and carrying out power failure detection when the power is on.
Preferably, performing power down protection when updating data includes: backing up data to be updated; setting a flag indicating that the backup data is completed; updating the data; and clearing the mark, wherein the mark comprises the current operation information.
Preferably, the power down detection comprises: detecting whether a mark exists during power-on, if so, performing power-down processing and completing power-down detection; and if the mark does not exist, directly finishing the power failure detection.
Preferably, the power down process comprises: loading current operation information in the mark; updating data according to the current operation information; the flag is cleared.
The invention provides a data erasing and writing system based on an eFlash storage chip, which comprises: the logical division module is used for carrying out space division on the eFlash memory chip; the calculation module is used for calculating the divided spaces to obtain the size information and the quantity information of each divided space and calculating the height of the obtained reference erasing balance line and the erasing balance height of the erasing unit; the balance management module is called before the eFlash memory chip performs data erasing and writing, is used for effectively scheduling balance exchange, judges whether to start the balance exchange according to the comparison result of the height of the reference erasing and writing balance line and the erasing and writing balance height of the erasing and writing unit, and performs data erasing and writing after balance management is quitted; and the power failure protection module is used for ensuring that the data updating is not influenced by power failure.
Preferably, the eFlash memory chip after space division includes: the system comprises an interval mapping table, an information management table and an interval, wherein the interval mapping table comprises a plurality of mapping units and is used for managing the mapping relation between the interval and a virtual interval; the information management table is used for recording the current balancing round number and the current exchange unit; the interval comprises a plurality of erasing units and a virtual unit, wherein the erasing units are used for recording the addresses of the mapping units, the erased times and the balanced round number of each erasing unit in the erasing units and storing application data, and the virtual unit is used for representing all storage units in the interval.
Preferably, the information management table includes: the first information unit is used for recording the current balancing round number; and the second information unit is used for caching the balanced object.
Preferably, the eFlash memory chip after space division further includes: and the temporary backup area comprises a first backup unit and a second backup unit, wherein the first backup unit is used for backing up the information management table, and the second backup unit is used for backing up the erasing unit for performing balance exchange.
Preferably, each of the plurality of erase-write units includes: the management unit is used for recording the addresses of the mapping units, the erased times and the balanced round number of each erasing unit in the erasing units; and the storage unit is used for storing the application data.
Preferably, the balance management module includes: the first judging unit is used for judging whether the target erasing unit needs to carry out balanced exchange when the data is written; the second judging unit is used for judging whether the current switching unit is available or not in balanced switching; the query unit is used for searching and obtaining an available exchange unit when the current exchange unit is unavailable; and the exchange unit is used for realizing balanced exchange between the balanced object and the balanced object.
The invention has the beneficial effects that: the invention discloses a data erasing method and a system based on an eFlash memory chip, wherein a writing interface of the chip is packaged, a balance management mechanism can be automatically started when the writing interface is called by an application layer, and whether balanced exchange is needed or not is judged by comparing the erasing balance height of a reference erasing balance line and a target erasing unit.
And the balance management mechanism ensures the balance of data erasing and writing.
Only 2 times of multiplication operation is needed for judging whether the target erasing unit meets the balance requirement, and compared with the prior art which needs a large amount of reading judgment and complex operation, the efficiency is greatly improved.
When the space is divided, the total size of the virtual interval is ensured to be integral multiple of the size of a storage unit, one application data can be stored in the same erasing unit as much as possible, the addressing times of the erasing unit and the complexity of subsequent data reading are reduced, and further the additional performance expense is reduced.
When the exchange units are updated, whether each erasing unit is available or not is judged one by one, so that any erasing unit which can be used as exchange can be avoided being missed, and the balance of data erasing and writing of the erasing units in the eFlash memory chip and the erasable times of the eFlash memory chip are improved.
The power-down protection can avoid data loss, and improve the safety and integrity of data erasing, thereby improving the stability of the application program.
The method has the advantages that the eFlash memory chip is reasonably divided into spaces, so that the eFlash memory chip can have a better structure to execute corresponding balanced erasing operation, and further, a foundation is provided for improving the erasing times of the eFlash memory chip, enhancing the erasing balance and reducing the erasing performance overhead.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.
FIG. 1 is a schematic structural diagram of a balanced erase/write module of an eFlash memory chip according to an embodiment of the present invention;
FIGS. 2(a) to 2(d) are schematic structural diagrams of the sections of the eFlash memory chip in FIG. 1;
FIG. 3 is a flowchart illustrating a data erasing method based on an eFlash memory chip according to an embodiment of the present invention;
FIG. 4 is a flowchart illustrating an application layer of an eFlash memory chip according to an embodiment of the present invention invoking a write interface for performing balanced erasing;
FIGS. 5(a) and 5(b) are flow charts illustrating the equalizing erase and write operations of the eFlash memory chip according to the embodiment of the present invention;
6(a) to 6(d) are schematic diagrams illustrating the balance exchange of the eFlash memory chip provided by the embodiment of the invention;
7(a) to 7(c) show a flow chart of performing power down protection when updating data provided by an embodiment of the present invention;
fig. 8 is a schematic structural diagram of a data erasing system based on an eFlash memory chip according to an embodiment of the present invention.
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. The invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.
The present invention will be described in detail below with reference to the accompanying drawings.
Fig. 1 shows a schematic structural diagram of an eFlash memory chip according to an embodiment of the present invention, and fig. 2(a) to fig. 2(d) show schematic structural diagrams of respective intervals of the eFlash memory chip in fig. 1.
The embodiment of the invention mainly takes a whole or partial memory chip such as an eFlash memory chip as a target operation object.
As shown in fig. 1 and fig. 2(a) to 2(d), in this embodiment, the eFlash memory chip includes an interval mapping table 110, an information management table 120, a temporary backup area 130, and an interval 140.
The interval mapping table 110 includes a plurality of mapping units 111 for managing a mapping relationship between the interval 140 and the virtual interval 150.
The virtual interval 150 is an abstraction of the interval 140, and the entire virtual interval 150 represents all the storage cells 1412 of the entire interval 140. For the application layer, only the virtual partition 150 needs to be known, i.e. the erasure unit known by the application layer is the storage unit of the partition.
If it is not stated explicitly, the application layer writes data to the erasure unit, which indicates that the application layer operates as the erasure unit in the virtual interval, the erasure unit described below is always the erasure unit in the interval by default.
The information management table 120 includes a first information unit 121 and a second information unit 122, the first information unit 121 is used to record the current number of equalization rounds, and the current number of equalization rounds determines the height of the erasure equalization line. The second information unit 122 is used to buffer the balanced object, so as to avoid the need to start from the first erasure unit of the interval each time the balanced object is sought, and improve the efficiency of seeking the balanced exchange target object (balanced object).
Further, in the embodiment, the number of equalization rounds is expressed by equally dividing the theoretical value of the number of times that the erasing unit 141 can erase, and the size of each equally divided block is the limit of the number of times that each round of equalization can erase.
The temporary backup area 130 is used for backing up the information management table, and two erasure units for performing balance exchange.
In one possible embodiment, the temporary backup area 130 fixedly occupies 3 erasure units, and includes a first backup unit 131 and a second backup unit 132, where the first backup unit 131 occupies 1 erasure unit for backing up the information management table 102; the second backup unit 132 occupies the other 2 erasure units for backing up the two erasure units for performing the balance exchange.
Further, the temporary backup area 130 is an optional support item for power down protection. If power-down protection is not required to be supported, the flash memory chip does not need to allocate the temporary backup area 130, so that the erasing performance of the flash memory chip can be greatly improved, but the stability of an application program is greatly reduced, and once power-down occurs, the validity and the correctness of data stored in the flash memory chip cannot be guaranteed.
The section 140 includes a plurality of erasure units 141, each of which is logically divided into a management unit 1411 and a storage unit 1412. All the management units 1411 record a non-conflicting mapping unit address, the erased number and the equalized round number of the erasing unit, and the storage unit 1412 stores data written by the application program.
It is understood that the sum of the sizes of all the storage units 1412 in the whole interval 140 is the size of the virtual interval 150.
Fig. 3 shows a flowchart of a data erasing and writing method based on an eFlash memory chip according to an embodiment of the present invention, fig. 4 shows a flowchart of an application layer of the eFlash memory chip according to an embodiment of the present invention calling a write interface to perform balanced erasing and writing, and fig. 5(a) and fig. 5(b) show flowcharts of an eFlash memory chip according to an embodiment of the present invention performing balanced erasing and writing.
In this embodiment, before performing the erasing operation on the eFlash memory chip, space division (structures shown in fig. 1 and fig. 2(a) to fig. 2 (d)) should be further included to the eFlash memory chip, so that the eFlash memory chip can have a better structure to perform the subsequent corresponding operation, and further, a basis is provided for improving the erasing frequency of the eFlash memory chip and reducing the erasing performance overhead.
As described above, the space division of the eFlash memory chip includes: a physical division information management table 120 and a temporary backup area 130, and a virtual section 150; calculating to obtain the number of the storage units 1412; calculating the size of the obtained interval 140 according to the number of the storage units 1412 and the size of the erasing unit 141; the size of the interval mapping table 110 is obtained by calculation.
The formula for calculating the number of the obtained storage cells 1412 is as follows:
the formula for calculating the size of the obtained interval 140 is as follows:
the number of memory cells is multiplied by the size of the erase/write cell (equation 2)
The formula for calculating the size of the interval mapping table 110 is as follows:
in this embodiment, for the above reasonable space division, it should be noted that: (1) the production process of the eFlash memory chip leads the performance cost of byte reading and writing and erasing unit reading and writing to be almost the same, and some eFlash memory chips do not support direct byte writing, so the soft implementation of byte writing of the invention has larger performance cost compared with the direct byte writing. To further reduce the performance overhead, the data should be controlled to be in the same erasure 141 as much as possible, and therefore the dummy section 150 is preferably an integer multiple of the size of the memory cell 1412. (2) The information management table 120 actually uses only 2 spatial address sizes, but 1 erasure unit is allocated in total for performance. (3) The temporary backup area 130 only needs to be partitioned if power down protection is supported. (4) The size of the management unit 1411 is a fixed 3-space address size. (5) The size of the mapping unit 201 is a fixed 1-space address size. The size of 1 space address is 4 bytes in a 32-bit system, and 8 bytes in a 64-bit system.
In order to make the reasonable eFlash memory chip space division more obvious and understandable, the following will describe in detail with reference to the idea of the embodiment.
Assuming a 32-bit system, 510 erasure units of the eFlash memory chip, i.e. 500 × 512+512 size, are used as the target operation object of the present embodiment, each erasure unit 141 occupies 512 bytes, wherein the management unit 1411 occupies 12 bytes, the storage unit 1412 occupies 500 bytes, and the mapping unit 111 occupies 4 bytes, which needs to support power-down protection. The specific space division steps can refer to: (1) the size of the virtual section 150 is logically divided into 250000 bytes, (2) the number of the storage units 1412 is 501 according to formula 1, the size of the section 140 is 256512 bytes according to formula 2, and (3) the size of the mapping unit 111 is 2048 bytes according to formula 3.
The spatial structure and size of the above embodiment are: the section mapping table 110 occupies 2048 bytes, the information management table 120 occupies 512 bytes, the temporary backup area 130 occupies 1536 bytes, and the section 140 occupies 256512 bytes. A total of 260608 bytes, i.e. 509 erasure cells, are actually occupied.
The specific numerical values in the above embodiments are only exemplary and should not be construed as limiting the scope of the present invention.
As shown in fig. 3 and referring to fig. 1 and fig. 2(a) to fig. 2(d), in this embodiment, the data erasing method based on the eFlash memory chip specifically includes the following steps:
in step S1, application data is acquired.
In step S2, the write interface is called, and the balance management mechanism is started to determine whether the target erasure unit needs to start balance swap.
In this embodiment, the application layer performs data erasing by calling an interface provided by the present invention, as shown in fig. 4, the application layer 160 calls the write interface 170 to finally write the application data into the erasing unit 141, and finally returns the write state of the application data.
The method specifically comprises the following steps:
in step S201, the application layer 160 writes the application data to the write interface 170.
In step S202, the write interface 170 performs an interface self-call to start a balance management mechanism.
In step S203, the write interface 170 calls the available address of the flash unit 141 and writes the application data into the flash unit 141.
In step S204, the erasing unit 141 returns the writing status of the application data to the writing interface 170.
In step S205, the write interface 170 returns the write status of the application data to the application layer 160.
Further, the write status of the application data includes write success and write failure. If the write is successful, it means that the erasure unit 141 is not damaged, and the application layer 160 writes data into the target erasure unit 141 through the write interface 170, and successfully writes the data. The write failure indicates that the application layer 160 writes data into the target erase/write unit 141 through the write interface 170, but fails to write the data successfully. For balanced erasures using the present invention, a failure to successfully write data indicates that the target erase-write cell 141 is defective, which in turn means that the remaining erase-cells are about to be defective. Through the steps, the writing error of the application data caused by the damage of the erasing unit can be avoided, so that the erasing efficiency and the erasing quality are improved.
As shown in fig. 5(a), in this embodiment, the balancing management mechanism when the write interface is called includes the following steps:
in step S211, it is determined whether the target erase/write unit needs to initiate a balance swap.
In this embodiment, the method for determining whether the target erasure unit needs to start the equalization swap includes: acquiring the recorded balance round number and each round of balance erasing times of the eFlash memory chip, and calculating to obtain the height of a reference erasing balance line; acquiring the recorded erased times and the number of balanced rounds of the target erasing unit, and calculating to obtain the erasing balance height of the target erasing unit; comparing the magnitude of the erasure balance height of the target erasure unit with the magnitude of the height of the reference erasure balance line; if the erasure balance height of the target erasure unit is smaller than the height of the reference erasure balance line, the target erasure unit does not need to start balance exchange, and the balance management is finished; if the erase balance height of the target erase/write unit is greater than or equal to the reference erase/write balance line height, it indicates that the target erase/write unit needs to initiate balance swap, and then step S212 is executed.
In step S3, when the balance swap does not need to be started, the balance management mechanism is terminated, and the application data is directly written into the target erasure unit.
In this embodiment, the erasure balance height of the target erasure unit is compared with the size of the reference erasure balance line height, and if the erasure balance line height of the target erasure unit is smaller than the reference erasure balance line height, it indicates that the target erasure unit does not need to start balance exchange, at this time, balance management (i.e., a balance management mechanism) is finished, and the obtained application data is directly written into the target erasure unit.
In step S4, when the equalization switching needs to be started, the available switching unit is acquired, and the application data is written into the available switching unit.
In this embodiment, the erasure balance height of the target erasure unit is compared with the size of the reference erasure balance line height, and if the erasure balance height of the target erasure unit is greater than or equal to the reference erasure balance line height, it indicates that the target erasure unit needs to start balance exchange, and at this time, an available exchange unit needs to be obtained, so as to write the application data into the available exchange unit.
In a preferred embodiment, the step S212 is further performed before the available switching units are obtained, so that the available switching units can be quickly determined and found, and the writing efficiency of the application data is improved.
Step S212, determine whether the current switching unit is available.
In this embodiment, the method for determining whether the current switching unit needs to start the balanced switching includes: acquiring the recorded balance round number and each round of balance erasing times of the eFlash memory chip, and calculating to obtain the height of a reference erasing balance line; acquiring recorded erased times and balanced round numbers of the current exchange unit, and calculating to acquire an erased balanced height of the current exchange unit; comparing the magnitude of the erasing balance height of the current exchange unit with the magnitude of the reference erasing balance line height; if the erasure balance height of the current switching unit is smaller than the height of the reference erasure balance line, it indicates that the current switching unit is available, and continues to execute step S214; if the erase balance height of the current swap unit is greater than or equal to the reference erase balance line height, it indicates that the current swap unit is not available, and then step S213 is performed.
Step S213, updates the current switching unit.
As shown in fig. 5(b), in this embodiment, updating the current switching unit includes performing the following steps:
in step S2131, it is determined whether the current swap unit is the last erasure unit.
In this embodiment, whether the current swap unit is the last erasure unit in the span can be determined according to the erasure unit address recorded in the management unit 1411. If the last erasing unit in the interval is, continuing to sequentially execute step S2132 and step S2133; if not, step S2134 is executed directly.
Step S2132, add one to the current number of equalization rounds, and enter the next round of equalization.
In this embodiment, when the process from the last erasure unit in the interval to the first erasure unit in the interval occurs to acquire the available swap unit, the number of the leveling rounds recorded in the information management table 120 should be increased by one to indicate that the erasure unit in the eFlash memory chip is about to enter the leveling erasure stage of the next round, and then step S2133 is executed continuously.
In step 2133, the current swap unit points to the first erase/write unit.
In this embodiment, when the erase/write unit in the interval enters the next round of balanced erase/write, the first erase/write unit in the interval is used as the proposed swap unit, and step S2135 is executed.
In step 2134, the current swap unit points to the next erase/write unit.
In this embodiment, if the currently available erase-write unit is not the last erase-write unit in the interval, the next new erase-write unit in the interval is used as the proposed exchange unit to execute step S2135 according to the address of the erase-write unit corresponding to the current exchange unit. When available exchange units are searched subsequently, any erasing unit which can be used as exchange is not missed, the data erasing balance of the erasing unit in the eFlash memory chip is improved, and the erasing times of the eFlash memory chip are further improved.
Further, in a preferred embodiment, if the currently available erasure unit is not the last erasure unit in the interval, the current erasure unit should be sequentially searched down one by one according to the address of the current swap unit. By the method, the difference of the erased times of each erasing unit can be reduced as much as possible in multiple rounds of balanced erasing and writing operation, the balance of data erasing and writing of the erasing and writing units in the eFlash memory chip is further improved, and the erasable times of the eFlash memory chip are further improved.
Step S2135, whether the proposed switching unit is available is determined.
In this embodiment, after the proposed switching unit is acquired, whether the proposed switching unit is available or not is determined again, and step S2136 is executed when the proposed switching unit is determined to be available, and step S2134 is returned to be executed again when the proposed switching unit is determined to be unavailable until the available switching unit is acquired.
Further, the method for determining whether the currently pending switching unit is available is consistent with the foregoing determination method, which is not described herein again.
Further, if the available exchange unit is not obtained after the above steps are repeatedly executed for many times, it indicates that the number of times of erasing and writing of the eFlash memory chip currently used as the operation target is full, and a new memory chip needs to be replaced.
In step S2136, the information management table is updated.
In this embodiment, after the available switching unit is obtained, the information management table is updated, then the update process of the current switching unit is ended, the current switching unit stored in the information management table is replaced and updated, and the application data is written into the switching unit stored in the information management table. At the same time, the current number of equalization rounds recorded in the information management table is also updated.
Step S214, start the equalization exchange.
In this embodiment, assuming that when the application layer writes data to the erase unit, the balance management compares the erase balance height of the target erase unit to be erased with the height of the reference erase balance line, and as a result of the comparison, the target erase unit touches the reference erase balance line, the target erase unit and the target object are subjected to balance exchange, so that the erase of the application layer is transferred to other erasable erase units (available erase units), thereby ensuring balanced erase.
Wherein, the calculation formula of the erasure balance height of the target erasure unit is as follows:
erased count of target Erase cell equalized round number (equation 4)
The calculation formula of the height of the reference erasure balance line is as follows:
current number of equalization rounds per round of equalization erasure number (equation 5)
As described above, the equalization management is to use the product of the number of equalization cycles per round of the memory chip and the current number of equalization cycles (as in formula 5) to perform a numerical value comparison with the product of the number of erased cycles and the number of equalized cycles of the target erasure unit (as in formula 4) recorded by the corresponding management unit when the application layer writes data into the erasure unit, and the equalization management considers that equalization swapping is not needed to be started only if the product of the latter is smaller than the product of the former, otherwise, the equalization management is started.
It should be noted that, the number of erasing times of each round of equalization of the memory chip may be flexibly configured according to actual needs, for example, an erasing unit may be erased 10 ten thousand times in an ideal environment, and the number of erasing times of each round of equalization is 3 ten thousand times or 5 ten thousand times. In contrast, the lower the numerical value distribution, the more uniform the erasing times of each erasing unit, that is, the better the equalization effect, but the performance overhead increases as the equalization exchange times increase; it should also be noted that it is not feasible to match the value too high, for example 10 ten thousand times, which is almost equivalent to no equalization effect.
As shown in fig. 6(a), the step of performing equalization switching includes:
in step S2141 and step S2142, the erasure unit 141 mapped between the equalization object and the equalized object starts to exchange data.
Further, exchanging data contents of the erasure unit 141 mapped between the equalization object (including the target erasure unit) and the equalized object (including the available erasure unit) includes: the erasure unit 141 mapped between the equalization object and the equalized object exchanges data of the memory cell (steps S2143 and S2144), and the erasure unit 141 mapped between the equalization object and the equalized object exchanges a mapping cell address (steps S2145 and S2146).
In steps S2147 and S2148, the erasure unit 141 mapped between the equalization object and the equalized object completes data exchange.
In steps S2149 and S2150, the corresponding mapping unit 111 between the equalization object and the equalized object starts exchanging data.
Further, the exchange data content of the corresponding mapping unit 111 between the equalization object and the equalized object includes: the mapping unit 111 corresponding between the balancing object and the balanced object exchanges the pointed erasure unit address (steps S2151 and S2152).
In steps S2153 and S2154, the corresponding mapping unit 111 between the equalization object and the equalized object completes data exchange.
Step S2155 and step S2156, the equalization exchange between the equalization object and the equalized object is completed.
When no balance exchange occurs, the mapping relationship between the virtual interval 150 and the interval 140 is shown in fig. 6(b), and it can be understood that: (1) the erasing unit 141 of the virtual interval and the mapping unit 111 of the interval mapping table are in one-to-one correspondence and are constant. (2) For the interval mapping table and the interval, an arrow pointing to the erasing unit 141 by the mapping unit 111 indicates that when the application layer erases the memory unit of the virtual interval 150, the embodiment of the present invention performs space access through the erasing unit address stored by the mapping unit 111; while the arrow pointing to the mapping unit 111 from the erasing unit 141 indicates that the mapping unit is accessed through the mapping unit address of the erasing unit 141 when the balanced exchange is performed, so that the two mapping units exchange data; the dashed line between the mapping unit 111 and the erasing unit 141 indicates that equalization swapping may occur. (3) Two mapping units do not point to the same erasure unit at the same time, and two erasure units do not point to one mapping unit at the same time. (4) For the application layer, 210 and 220 respectively represent a set of virtual partition erasure units with mapping relationships established. (5) Assuming that the application layer erases 210, the balancing management initiates balancing exchange, and finds 220 by the polling algorithm (refer to fig. 5(b)) of the current switch unit, that is, finds an available switch unit, where 210 is the balancing object and 220 is the balanced object.
When the balance exchange has occurred, the mapping relationship between the virtual intervals is as shown in fig. 6(c), and referring to fig. 6(a) and fig. 6(b), when the balance exchange has not occurred, it can be understood that 230 is a schematic diagram after the balance exchange is performed for 210 and 220, and 240 is a schematic diagram after the balance exchange is performed for 220 and 210.
It will be appreciated that the erasure records are erroneous if the equalization exchange exchanges data with the erasure records of both erasure units simultaneously. For example, one 10-time erased cell is considered to be erased 500 times, and another 500-time erased cell is considered to be erased 10 times. Therefore, during the equalizing exchange, the erased times and the equalized rounds of the unique erasure unit are not exchanged.
FIG. 6(d) shows a schematic diagram of an erasure equalization line, where the current swap unit 122 points to the first erasure of the interval during initialization, and the dashed line of the arrow indicates that the current swap unit can point to other erasure; rectangles of the bar graph represent erasing units, the leftmost rectangle is the first erasing unit, the next rectangle is the second erasing unit, and so on; the number of rectangles indicates the number of times the erasure unit has been erased. As can be seen from fig. 6(d), the erased number of all rectangles (erased cells) does not reach the height of the reference erase/write equalization line, for example, 50 times.
Fig. 7(a) to 7(c) show flowcharts for performing power down protection when updating data according to an embodiment of the present invention.
With reference to fig. 5(b), when the information management table is updated, power down protection is performed when data is updated, and power down detection is performed when power is turned on. As shown in fig. 7(a), performing power down protection when updating data includes performing the following steps:
in step S01, the data to be updated is backed up.
Before data updating, original data in the information management table and the two storage units which are subjected to balanced exchange are backed up in the temporary backup area to prevent data loss in the case of power failure, guarantee is provided for subsequent data updating, and data erasing safety and data integrity are improved.
In step S02, a flag indicating that the backup data is completed is set.
In this embodiment, after the data is successfully backed up to the temporary backup area, the set flag indicates that the backup data is completed. The mark contains the current operation information, so that the corresponding operation can be directly continued to be finished after the mark is detected, all data information does not need to be scanned, and the data erasing and balanced exchange efficiency is improved.
In step S03, the data is updated.
When a flag indicating that the backup data is completed is detected, updating of the data is started.
Step S04, the flag is cleared.
And after the data updating is finished, clearing the mark to avoid influencing the power failure detection in the next power-on process.
As shown in fig. 7(b), performing power down detection at power up includes performing the following steps:
step S011, detecting whether a mark exists or not when power is on, and if so, executing step S022 and step S033 in sequence; if no flag is present, step S033 is performed.
When the mark that the backup data is completed is detected, the data is indicated to be successfully backed up without worrying about data loss caused by power failure, at the moment, power failure processing is carried out, and an incomplete data updating process is continued. And when the mark that the backup data exists to complete is not detected, the last power failure does not cause data loss, and power failure processing is not needed.
And step S022, if the mark exists, performing power-down processing.
In this embodiment, as shown in fig. 7(c), the power-down processing includes the following steps:
step S0111, current operation information in the mark is loaded.
Step S0222, data update is performed according to the current operation information.
Step S0333, clears the flag.
At this point, the power down process is completed and step S033 is continuously performed.
Step S033, completing the power failure detection.
When the mark that the backup data is completed is not detected, or after the power down process is completed in step S022, the power down detection is completed, and other subsequent operations are continuously performed.
It can be understood that if the power down protection is not required to be supported in the data erasing, the data updating is directly performed.
Further, in this embodiment, the power failure may occur at any time, for example, the following situations may occur:
1. prior to backing up the data.
2. During the backup of data.
3. After backing up the data, before setting the flag.
4. During the setting of the flag.
5. After the flag is set, before the data is updated.
6. After updating the data, before clearing the flag.
7. During the clearing of the mark.
8. After the mark is cleared.
According to the power failure protection principle, the fact that the correctness and the validity of the data after power failure need to be ensured in updating the data can be known. Therefore, for the situations 1-4, data is not modified, if power failure occurs, the correctness and the effectiveness of the data are not influenced, and the set mark is not legal due to the power failure, so that power failure processing is not needed; and in the cases 5-7, the flag is successfully set to indicate that an operation of updating data is in progress, and at the moment, if power failure occurs, it cannot be ensured that the updated data is correct and effective, so that the data must be updated again according to the current operation information in the flag when power is turned on, and finally the flag is cleared, thereby completing an operation of updating data. By the method, the problem of data loss in the eFlash memory chip caused by abnormal power failure of the system can be effectively prevented.
For example: the operation object contains 80 erasure units, the space allocated to the management equalization algorithm such as the information management table is 5 erasure units, and the remaining 75 erasure units are used for data erasure. For the scheme of the embodiment, data needs to be erased and written for 1 time after one balanced erasing and writing is completed; if the equilibrium exchange occurs, 3 times are needed; if the two mapping units are not in the same erasing unit when the equilibrium exchange occurs, 4 times of erasing operation are needed; if the current exchange unit is updated when the balanced exchange occurs, increasing 1-time data erasing on the basis of the balanced exchange erasing operation; if the number of balanced erasures in each round is 2 ten thousand or 5 thousand, and 4 rounds, 30 balanced swaps in each round, and 20 additional updates to the current swap unit are required in the second round and the subsequent rounds, which is about 750 ten thousand erasures.
As described above, in most cases, the erasing and writing of the technical scheme provided by the present invention do not need to increase the performance overhead of an additional equalization algorithm, so that the efficiency of the present invention is greatly improved compared with the prior art.
It should be noted that the above numerical value lists are only exemplary, and the present invention may have other various embodiments according to different basic conditions, which should not be construed as limiting the technical solution of the present invention.
Based on the same inventive concept, the present invention also discloses a data erasing system based on the eFlash memory chip, as shown in fig. 8, fig. 8 shows a schematic structural diagram of the data erasing system based on the eFlash memory chip provided by the embodiment of the present invention, the data erasing system based on the eFlash memory chip includes: the device comprises a logic division module 010, a calculation module 020, a balance management module 030 and a power failure protection module 040.
The logical division module is used for carrying out space division on the eFlash storage chip.
In this embodiment, the logic dividing module 010 mainly divides the eFlash memory chip into the space structures shown in fig. 1 and fig. 2(a) to fig. 2 (d).
The calculating module 020 is configured to calculate the divided spaces to obtain size information and quantity information of each divided space, and is further configured to calculate and obtain a height of the reference erasure and writing equalization line and an erasure and writing equalization height of the erasure and writing unit.
In this embodiment, the calculation unit may perform the calculation according to the above formulas 1 to 5. Without limitation, the calculating unit may also calculate the values required for the balance erasing of other memory chips according to other simple formulas.
The balance management module 030 is called before the eFlash memory chip performs data erasing, and is used for effectively scheduling balance exchange, judging whether to start the balance exchange according to the comparison result of the height of the reference erasing and writing balance line and the erasing and writing balance height of the erasing and writing unit, and performing data erasing and writing after balance management is quitted.
Further, in this embodiment, the balance management module 030 includes: a first determining unit 031, configured to determine whether the target erasure unit needs to perform balanced swapping when writing data; a second determining unit 032, configured to determine whether the current switch unit is available during balanced switching; a query unit 033, configured to search for an available switching unit when the current switching unit is unavailable; and a switching unit 034, configured to implement equalization switching between the equalization object and the equalized object.
The power down protection module 040 is used to ensure that data update is not affected by power down according to the above-mentioned data erasing and writing method.
It should be noted that, in the data erasing system based on the eFlash memory chip, the division spaces all satisfy the above-mentioned various corresponding relationships.
In summary, the invention provides a data erasing method and system based on an eFlash memory chip, a write interface of the chip is packaged, and a balance management mechanism can be automatically started when an application layer calls the write interface. In most cases, the performance overhead of the invention only needs 2 times of multiplication operation, compared with the prior art which needs a large amount of reading judgment and complex operation, the efficiency is greatly improved, on the premise of ensuring higher erasing times, the problem of large performance overhead of the prior art is solved, and the efficiency of searching the balanced exchange target object is improved.
It should be noted that, in this document, the "target erasure unit" is all referred to as the first erasure unit accessed by the application layer invoking the write interface, and the erasure unit may be available or not.
It should be noted that, in this document, the contained terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Finally, it should be noted that: it should be understood that the above examples are only for clearly illustrating the present invention and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of the invention may be made without departing from the scope of the invention.
Claims (22)
1. A data erasing method based on an eFlash memory chip comprises the following steps:
acquiring application data;
calling a writing interface, starting a balance management mechanism, and judging whether a target erasing unit needs to start balance exchange;
when the balance exchange does not need to be started, ending the balance management mechanism, and directly writing the application data into the target erasing unit;
when the equilibrium exchange needs to be started, acquiring an available exchange unit, writing the application data into the available exchange unit,
the method for judging whether the target erasing unit needs to start the balance exchange comprises the following steps:
acquiring the recorded balance round number and each round of balance erasing times of the eFlash memory chip, and calculating to obtain the height of a reference erasing balance line;
acquiring recorded erased times and balanced round numbers of the target erasing unit, and calculating to obtain an erasing balance height of the target erasing unit;
and comparing the erasure balance height with the reference erasure balance line height, and starting balance exchange if the erasure balance height is greater than or equal to the reference erasure balance line height.
2. The data erasure method according to claim 1, wherein said reference erasure equalization line height is equal to a product of said number of equalization rounds and said number of equalization erases per round,
the erasure balance height of the target erasure unit is equal to the product of the erased times and the balanced round number.
3. The data erasure method according to claim 1, wherein writing the application data directly to the target erasure unit or writing the application data to the available swap unit further comprises:
returning the writing state of the application data;
judging whether the target erasing unit or the available exchange unit is damaged according to the writing state,
if the data writing is successful, the target erasing unit or the available exchange unit is not damaged;
if the data writing fails, it indicates that the target erasure unit or the available swap unit is damaged, and the rest of the erasure units are about to be damaged.
4. The data erasure method of claim 1, wherein when it is desired to initiate a balanced swap, obtaining an available swap unit, writing the application data to the available swap unit comprises:
judging whether the current exchange unit is available;
if the current exchange unit is available, starting balanced exchange, and writing the application data into the current exchange unit;
and if the current exchange unit is unavailable, updating the current exchange unit, starting balanced exchange after the updating is successful, and writing the application data into the available exchange unit.
5. The data erasure method of claim 4, wherein determining whether the current swap unit is available comprises:
acquiring recorded erased times and balanced round numbers of the current exchange unit, and calculating to acquire an erased balanced height of the current exchange unit;
comparing the magnitudes of the erase-verify height of the current swap unit and the reference erase-verify line height,
if the erasure balance height of the current switching unit is smaller than the height of the reference erasure balance line, the current switching unit is available;
and if the erasure balance height of the current switching unit is greater than or equal to the reference erasure balance line height, the current switching unit is unavailable.
6. The data erasure method according to any one of claims 2 and 5, wherein the reference erasure-equalizing line height is a product of the number of equalizing rounds and the number of equalizing erasures per round.
7. The data erasure method of claim 4, wherein updating the current swap unit comprises:
judging whether the current exchange unit is the last erasing unit or not;
if the current exchange unit is not the last erasing unit, sequentially judging whether the next erasing unit is available one by one to obtain an available exchange unit;
after the available switching units are obtained, the information management table is updated.
8. The data erasure method of claim 4, wherein updating the current swap unit comprises:
judging whether the current exchange unit is the last erasing unit or not;
if the current exchange unit is the last erasing unit, adding one to the current balancing round number, and entering the next round of balancing;
the first erasing unit is planned to be the current exchange unit;
determining whether the proposed current switching unit is available,
if the proposed current exchange unit is available, the proposed current exchange unit is used as an available exchange unit, and an information management table is updated;
if the proposed current exchange unit is unavailable, sequentially judging whether the next erasing unit is available one by one to obtain an available exchange unit;
after the available switching units are obtained, the information management table is updated.
9. The data erasure method according to any one of claims 7 and 8, wherein whether the current swap unit is the last erasure unit is determined according to the address of the erasure unit corresponding to the current swap unit.
10. The data erasure method of claim 4, wherein initiating a balanced swap comprises:
carrying out data exchange on the erasing units mapped between the balancing object and the balanced object;
after the data exchange of the erasing units mapped between the balancing object and the balanced object is finished, the corresponding mapping units between the balancing object and the balanced object exchange data,
wherein the balancing object comprises the target erasure unit and the balanced object comprises the available swap unit.
11. The method of claim 10, wherein the data exchange between the equalization object and the mapped erasure unit of the equalized object comprises:
the erasing units mapped between the balancing object and the balanced object exchange data of a storage unit;
the erasing units mapped between the balancing object and the balanced object exchange mapping unit addresses.
12. The data erasure method according to claim 10, wherein the data exchange between the corresponding mapping units of the equalization object and the equalized object comprises:
and the corresponding mapping unit between the balancing object and the balanced object exchanges pointed erasing unit addresses.
13. The data erasure method according to any one of claims 7 and 8, wherein the updating of the information management table further includes:
performing power failure protection when updating data;
and carrying out power failure detection when the power is on.
14. A data erasure method as claimed in claim 13, wherein the power down protection while updating the data includes:
backing up data to be updated;
setting a flag indicating that the backup data is completed;
updating the data;
the mark is cleared away and the mark is cleared,
wherein the mark comprises the current operation information.
15. A data erasure method as claimed in claim 13, wherein the power down detection at power up comprises:
detecting the presence of a flag at power-up,
if the mark exists, performing power failure processing and completing power failure detection;
and if the mark does not exist, directly finishing the power failure detection.
16. A data erasure method as claimed in claim 15, wherein the step of performing a power down process in the presence of the flag comprises:
loading current operation information in the mark;
updating data according to the current operation information;
the flag is cleared.
17. A data erasing and writing system based on an eFlash storage chip comprises:
the logical division module is used for carrying out space division on the eFlash memory chip;
the calculation module is used for calculating the divided spaces to obtain the size information and the quantity information of each divided space and calculating the height of the obtained reference erasing balance line and the erasing balance height of the erasing unit;
the balance management module is called before the eFlash memory chip performs data erasing, and is used for judging whether balance exchange is started or not according to the comparison result of the height of the reference erasing balance line and the erasing balance height of the erasing unit, and performing data erasing after balance management quits;
and the power failure protection module is used for ensuring that the data updating is not influenced by power failure.
18. The data erasure system of claim 17, wherein the eFlash memory chip after space division comprises: an interval mapping table, an information management table, and an interval,
the interval mapping table comprises a plurality of mapping units and is used for managing the mapping relation between the interval and the virtual interval;
the information management table is used for recording the current balancing round number and the current exchange unit;
the interval comprises a plurality of erasing units, is used for recording the addresses of the mapping units, the erased times and the balanced round number of each erasing unit in the erasing units and storing application data,
wherein the dummy cells are used to characterize all memory cells within the interval.
19. The data erasure system according to claim 18, wherein said information management table includes:
the first information unit is used for recording the current balancing round number;
and the second information unit is used for caching the balanced object.
20. The data erasure system of claim 18, wherein the eFlash memory chip after space division further comprises:
and the temporary backup area comprises a first backup unit and a second backup unit, wherein the first backup unit is used for backing up the information management table, and the second backup unit is used for backing up the erasing unit for performing balance exchange.
21. The data-erasure system of claim 18 wherein each of the plurality of erasure cells includes:
the management unit is used for recording the addresses of the mapping units, the erased times and the balanced round number of each erasing unit in the erasing units;
and the storage unit is used for storing the application data.
22. The data erasure system of claim 17, wherein said balance management module includes:
the first judging unit is used for judging whether the target erasing unit needs to carry out balanced exchange when the data is written;
the second judging unit is used for judging whether the current switching unit is available or not in balanced switching;
the query unit is used for searching and obtaining an available exchange unit when the current exchange unit is unavailable;
and the exchange unit is used for realizing balanced exchange between the balanced object and the balanced object.
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| CN115357953A (en) * | 2022-10-21 | 2022-11-18 | 山东三未信安信息科技有限公司 | Dynamic distribution method and system for cipher card key storage |
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