CN111142000A - SMD transformer partial discharge detection system - Google Patents
SMD transformer partial discharge detection system Download PDFInfo
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- CN111142000A CN111142000A CN202010008924.1A CN202010008924A CN111142000A CN 111142000 A CN111142000 A CN 111142000A CN 202010008924 A CN202010008924 A CN 202010008924A CN 111142000 A CN111142000 A CN 111142000A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/12—Testing dielectric strength or breakdown voltage ; Testing or monitoring effectiveness or level of insulation, e.g. of a cable or of an apparatus, for example using partial discharge measurements; Electrostatic testing
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/12—Testing dielectric strength or breakdown voltage ; Testing or monitoring effectiveness or level of insulation, e.g. of a cable or of an apparatus, for example using partial discharge measurements; Electrostatic testing
- G01R31/14—Circuits therefor, e.g. for generating test voltages, sensing circuits
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Abstract
The invention provides a chip transformer partial discharge detection system which comprises an ultrahigh frequency partial discharge detection sensor module, a venation detection module and an FPGA (field programmable gate array) parallel acquisition module, wherein the ultrahigh frequency partial discharge detection sensor module adopts a chip structure, the output end of the ultrahigh frequency partial discharge detection sensor module is connected with the venation detection module, the output end of the venation detection module is connected with the FPGA parallel acquisition module, the ultrahigh frequency partial discharge detection sensor module is used for receiving an ultrahigh frequency partial discharge signal generated by partial discharge of a transformer, the venation detection module is used for reducing the signal frequency, the ultrahigh frequency partial discharge signal received by the ultrahigh frequency partial discharge detection sensor module is converted into an envelope wave, the FPGA parallel acquisition module is used for carrying out multichannel parallel sampling, and the obtained partial discharge detection signal is transmitted to a digital signal processor. The detection system can be applied to a running transformer, the frequency receiving range of the ultrahigh frequency is expanded, and ultrahigh frequency electromagnetic waves generated by partial discharge can be received in a wider area.
Description
[ technical field ] A method for producing a semiconductor device
The invention relates to the technical field of transformer partial discharge fault detection, in particular to a patch type transformer partial discharge detection system.
[ background of the invention ]
The transformer is one of core devices of the power system, and the importance is very prominent. Therefore, the reliability of its operation is critical to the safety and stability of the power system, and the safety and reliability of the power transformer depends greatly on the reliability of its insulation. Partial discharge is one of the most important manifestations of insulation performance and also an important source of serious accidents in transformers. Because of the power transformer, especially large and huge power transformer, the scheduled time for power failure inspection and maintenance is relatively short. Therefore, the method and the device can effectively detect the discharge in the transformer on line and identify the running condition of the transformer in real time, and are important methods and means for finding the internal defects of the transformer in advance and preventing serious safety accidents.
However, there are many kinds of interference on the site of the transformer, specifically including frequency conversion electronic device interference, mobile communication interference, carrier communication interference, external corona, etc., according to experimental research, the frequency band of these interferences is mostly below 500MHz, the transformer partial discharge pulse current method mainly adopts a high-frequency current sensor (rogowski coil) as a sensor for detection, the upper limit of the detection frequency band is about 50MHz, the ultrasonic method mainly selects an ultrasonic detection element as a sensor, the upper limit of the detection frequency of the sensor is near 10MHz, obviously, there is an overlapping portion between the above two methods and the transformer field interference, so that the electromagnetic interference on the site of the transformer cannot be avoided, and erroneous measurement is easily caused, therefore, the traditional transformer partial discharge monitoring device faces the problem that noise cannot be eliminated due to low monitoring frequency band. The oil chromatography monitoring method is mainly realized by measuring gas dissolved in oil generated by high-temperature decomposition of transformer oil (partial discharge is an important factor causing the oil to be decomposed into the gas), essentially belongs to indirect measurement, and practice proves that the measurement result is accurate, so that the method is one of the mainstream methods for monitoring the transformer at present. Therefore, it is necessary to research a new detection method for the transformer, so that the transformer can meet the requirements in terms of noise suppression, real-time performance of monitoring and rapidity. When the oil-immersed transformer generates partial discharge inside, a large amount of high-frequency electromagnetic waves are diffracted, the frequency range of the high-frequency electromagnetic waves is generally between 300 and 1500MHz, and the monitoring of the discharge inside the transformer can be realized by effectively detecting the electromagnetic waves diffracted by the partial discharge inside the transformer.
Although an ultrahigh frequency partial discharge detection sensor is available at present, the ultrahigh frequency partial discharge detection sensor is generally in an oval structure, and is inserted into a transformer through a valve in practical use, so that the ultrahigh frequency partial discharge detection sensor cannot be suitable for the running transformer, and the distance between the ultrahigh frequency partial discharge detection sensor and a sensor inserted into the transformer is calculated to avoid breakdown of a high-voltage winding inside a transformer iron core or insulation short circuit. For this reason, the first task of monitoring partial discharges by means of the uhf method is to develop a suitable antenna sensor. To receive the partially discharged ultrahigh frequency electromagnetic wave. In order to meet the demand of small size and integration, the research and application of the ultra-wideband planar antenna draw attention. Generally, the smaller the size of the antenna, the inverse relationship between the efficiency and bandwidth performance of the antenna is, and therefore, a balance needs to be found between the size and the efficiency and bandwidth. The ultra-wideband printed monopole antenna has the advantages of light weight, small volume, low profile, omnidirectional directional pattern, easiness in conformality and integration and the like, and is widely applied to a short-distance wireless communication system. The printed antenna fed by the coplanar waveguide has the advantages of wide frequency band, simple impedance matching, small radiation loss, easy integration and the like.
[ summary of the invention ]
The invention aims to solve the problems in the prior art, and provides a patch type transformer partial discharge detection system which can be applied to a running transformer, enlarges the frequency receiving range of ultrahigh frequency and can receive ultrahigh frequency electromagnetic waves generated by partial discharge in a wider area.
In order to achieve the purpose, the invention provides a patch type transformer partial discharge detection system which comprises an ultrahigh frequency partial discharge detection sensor module, a vein detection module and an FPGA parallel acquisition module, wherein the ultrahigh frequency partial discharge detection sensor module is of a patch type structure, the output end of the ultrahigh frequency partial discharge detection sensor module is connected with the vein detection module, the output end of the vein detection module is connected with the FPGA parallel acquisition module, the ultrahigh frequency partial discharge detection sensor module is used for receiving an ultrahigh frequency partial discharge signal generated by partial discharge of a transformer, the vein detection module is used for reducing the signal frequency, the ultrahigh frequency partial discharge signal received by the ultrahigh frequency partial discharge detection sensor module is converted into an envelope wave, the FPGA parallel acquisition module is used for carrying out multichannel parallel sampling, and the obtained partial discharge detection signal is transmitted to a digital signal processor.
Preferably, the antenna of the ultrahigh frequency partial discharge detection sensor module includes a dielectric substrate, and a radiation patch, a coplanar waveguide feeder, a first coplanar waveguide ground patch, and a second coplanar waveguide ground patch printed on a top surface of the dielectric substrate, the radiation patch and the coplanar waveguide feeder are sequentially disposed from top to bottom, the first coplanar waveguide ground patch and the second coplanar waveguide ground patch are symmetrically disposed on two sides of the coplanar waveguide feeder, gaps are formed between the first coplanar waveguide ground patch, the second coplanar waveguide ground patch, and the coplanar waveguide feeder, and the first coplanar waveguide ground patch and the second coplanar waveguide ground patch have the same structure.
Preferably, the dielectric substrate is made of an epoxy resin having a relative dielectric constant ∈ r of 4.4 and a dielectric loss tangent tan δ of 0.030, and the dielectric substrate has a thickness of 0.8 mm.
Preferably, the first coplanar waveguide ground patch and the second coplanar waveguide ground patch are fan-shaped structures with an arc-shaped edge, and the cross section of the fan-shaped structures has a radius R2 mm.
Preferably, the impedance of the first coplanar waveguide ground patch and the impedance of the second coplanar waveguide ground patch are 50 Ω.
Preferably, the radiation patch is of a circular structure, the radius R1 of the radiation patch is 90mm, and a plurality of fan-shaped annular grooves are arranged at intervals on the periphery of the radiation patch.
Preferably, the FPGA parallel acquisition module adopts an EP1C6T144C8 chip of Altera corporation, and includes a decoder, 4 partial discharge pulse width detection output comparison modules, an interrupt request or gate, and twenty-four partial discharge detection signal outputs, the partial discharge pulse signals generated by the FPGA parallel acquisition module can generate different partial discharge pulse width numbers by setting different partial discharge threshold values, and according to the relationship between the numbers and the threshold values, the discharge amplitude and phase of the partial discharge can be obtained and locked in the data latch module of the FPGA parallel acquisition module, so that the digital signal processor can evaluate and distinguish the amplitude and phase of the partial discharge signals.
Preferably, the PB port and the PE port of the digital signal processor are used as sixteen-bit data lines for transmitting partial discharge pulse width values; four lower bits of the PF port of the digital signal processor are used as address lines for distinguishing pulse width data of different partial discharge sensing devices; WE of the digital signal processor is a write enable gating pin, the low level is effective, and when the WE is used as an output CS of a decoder of the FPGA parallel acquisition moduleiMeanwhile, when the current level is low, sending data on the data line into a shadow register corresponding to the FPGA parallel acquisition module, wherein i is 0-11; the EN1 of the digital signal processor is a reference counter enabling signal and is used for initializing four reference counters of the FPGA parallel acquisition module; the EN2 of the digital signal processor is an interrupt request or gate enable signal of the FPGA parallel acquisition module; the EN3 of the digital signal processor outputs an enabling blocking signal of a three-state gate for twenty-four paths of partial discharge detection signals, so that the correctness of partial discharge data pulses is ensured, and when the partial discharge data detection fails, the output pulses are blocked through EN3, so that the reliable operation of partial discharge detection is ensured; the external interrupt XINT1 of the digital signal processor receives an interrupt signal generated by a reference counter of the FPGA parallel acquisition module, and after responding to the interrupt, the interrupt signal is calculated and then a new partial discharge detection request value is sent to the FPGA parallel acquisition module.
The invention has the beneficial effects that: the invention adopts a surface-mounted coplanar waveguide feed monopole antenna model as a partial discharge detection sensor, can be directly attached to the outer wall of the transformer, does not need to be inserted into the transformer through a valve hole, and is suitable for operating the transformer; the edges of the ground plane of the coplanar waveguide of the antenna are subjected to smooth processing, and the structural parameters of the patch are simulated and optimized, so that the receiving frequency band of the antenna covers the range of 0.3-3 GHz, ultrahigh frequency electromagnetic waves generated by partial discharge can be received in a wider range, the anti-interference capability is better, and the partial discharge detection effect is better; by adopting the vein detection technology, the ultrahigh frequency partial discharge signal forms an envelope wave, the frequency of the envelope wave is reduced to be about 30M, so that the FPGA circuit can effectively sample. And finally, by means of an FPGA multi-path parallel sampling algorithm and a hardware structure, a partial discharge detection signal can be quickly obtained and sent to a digital signal processor.
The features and advantages of the present invention will be described in detail by embodiments in conjunction with the accompanying drawings.
[ description of the drawings ]
FIG. 1 is an architectural diagram of the present invention;
FIG. 2 is a top view of an antenna of the UHF partial discharge detection sensor module of the present invention;
fig. 3 is a surface current distribution diagram of the 1.65GHz antenna of the present invention;
fig. 4 is the surface current distribution diagram of the 1.65GHz antenna of the present invention;
FIG. 5 is a graph of the effect of the present invention R1 on antenna VSWR;
FIG. 6 is a graph of the effect of the present invention R2 on antenna VSWR;
fig. 7 is a 0.05GHz pattern according to the present invention;
fig. 8 is a 1.65GHz pattern according to the present invention;
fig. 9 is the f-2.8 GHz pattern of the present invention;
FIG. 10 is an equivalent circuit of the context detection module of the present invention;
FIG. 11 is a block diagram of the signal connection structure between the DSP and the FPGA according to the present invention;
FIG. 12 is a block diagram of the FPGA generating multiple partial discharge signal output pulse waveforms according to the present invention;
fig. 13 is a partial discharge amplitude and phase output encoding of the present invention.
[ detailed description ] embodiments
Referring to fig. 1, the partial discharge detection system for a surface mount type transformer of the present invention comprises an ultrahigh frequency partial discharge detection sensor module 10, a vein detection module 20, and an FPGA parallel acquisition module 30, the ultrahigh frequency partial discharge detection sensor module 10 adopts a patch type structure, the output end of the ultrahigh frequency partial discharge detection sensor module 10 is connected with the vein detection module 20, the output end of the venation detection module 20 is connected with the FPGA parallel acquisition module 30, the ultrahigh frequency partial discharge detection sensor module 10 is used for receiving an ultrahigh frequency partial discharge signal generated by partial discharge of the transformer, the venation detection module 20 is configured to reduce the signal frequency, convert the ehf partial discharge signal received by the ehf partial discharge detection sensor module 10 into an envelope wave, perform multi-channel parallel sampling by the FPGA parallel acquisition module 30, and transmit the obtained partial discharge detection signal to the digital signal processor.
Further, referring to fig. 2, the antenna of the ultrahigh frequency partial discharge detection sensor module 10 includes a dielectric substrate 1, and a radiation patch 2, a coplanar waveguide feed line 3, a first coplanar waveguide ground patch 4, and a second coplanar waveguide ground patch 5 printed on the top surface of the dielectric substrate 1, where the radiation patch 2 and the coplanar waveguide feed line 3 are sequentially disposed from top to bottom, the first coplanar waveguide ground patch 4 and the second coplanar waveguide ground patch 5 are symmetrically disposed on two sides of the coplanar waveguide feed line 3, a gap is formed between the first coplanar waveguide ground patch 4, the second coplanar waveguide ground patch 5, and the coplanar waveguide feed line 3, and the first coplanar waveguide ground patch 4 and the second coplanar waveguide ground patch 5 have the same structure.
a. Antenna main parameter of ultrahigh frequency partial discharge detection sensor module
1) Radius of great circle
The ultra-wideband printed monopole antenna is evolved from a cylindrical array antenna, so that the ultra-wideband printed monopole antenna can be equivalent to the cylindrical array in a certain mode, and the performance of the ultra-wideband printed monopole antenna can be analyzed. Theoretically, the monopole printing patch structure with the radius R can be approximately equivalent to a cylindrical array with the height of L and the radius of R. The method for determining the lower limit frequency of the ultra-wideband printing monopole antenna can use a related formula of a planar monopole antenna:
wherein, L is the length of the circular radiation patch 2, namely 2R; w1, W2 are equivalent upper and lower edge widths, respectively, here equivalent to the horizontal projected lengths of the upper and lower semi-circles, respectively, i.e. the diameter 2R. The estimation error obtained by the formula is within +/-9%, units of L, W1 and W2 are m, and the lower limit frequency estimation value obtained by the formula is 0.32 GHz.
The expression for determining the lower limit frequency (in GHz) is:
where R is in mm, the estimate of the lower limit frequency of the antenna using this formula is 0.35GHz, which is very close to the 0.32GHz result estimated by formula (1).
2) Feed transmission line width G2 and coplanar waveguide gap G (identified with reference to FIG. 2)
The characteristic impedance of the coplanar waveguide can be represented
In the formula: k (k) is Legendre class 1 elliptic integral; epsiloneffIs a coplanar waveguide dielectric slab having a relative equivalent dielectric constant
In the formula:
the characteristic impedance of the coplanar waveguide is determined by the width G2 of the feed line and the gap G between the feed line and the ground, the relative dielectric constant epsilonr and the thickness H of the dielectric substrate 1. For a selected dielectric substrate (H is 1mm, and ∈ r is 4.4), if the distance between two ground plates (G2+2G) is constant, for example, 2mm, a one-to-one correspondence relationship between G2 and characteristic impedance Z can be obtained, and then initial values of G2 and G are calculated according to the principle of impedance matching between a waveguide transmission line and an antenna output port.
Antenna parameter optimization
b. Distribution of current
And (3) adopting HFSS software of Ansoft company to optimize parameters of the fractal antenna. A profile of the surface current of the 2 nd-order fractal antenna at the center f of the frequency band, 1.65GHz is shown in fig. 3. The current distribution on the antenna patch shows that at all operating frequency points, the surface current intensity has lower amplitude at the middle position of the antenna, and the amplitude is larger closer to the boundary, so that a large current density is formed at the feed source because all radiation currents pass through the feed source, as shown in fig. 4.
b1. Optimization of radius R1 of radiation patch 2
Changing R1 observes the effect on antenna VSWR:
the optimized design of fig. 5 shows that the antenna has a plurality of resonance points in the working range of 0.3 GHz. From the engineering application point of view, in order to make the antenna as little as possible to affect the insulation integrity of the electrical device to be tested, it is desirable that the antenna has a smaller size as well as better. As can be seen from the attached figure 5, the curve "R1 is 90 mm", and the S11 (reflection loss) of the antenna in the frequency band of 0.3-3 GHz is less than-10, so that the requirement of engineering application is met.
b2. And (3) changing the corner cutting radius of the coplanar waveguide grounding surface patch to optimize:
compared with the antenna without the corner cutting treatment, the S11 (reflection loss) value near 3GHz is effectively reduced after the corner cutting and rounding treatment is carried out on the coplanar waveguide ground plane patch. As can be seen from fig. 6, the curve "R2 ═ 78 mm" has the minimum value of S11 (reflection loss) of the antenna in the frequency band around 1.85GHz, and meets the requirements of engineering applications.
b3. Gain directional diagram
Fig. 7, 8 and 9 show the directional diagrams of the antenna designed by the invention at 0.5GHz, 1.65GHz and 2.8GHz respectively.
Fig. 7, 8 and 9 show the optimized design results of the E-plane and the H-plane of the antenna at 0.5GHz, 1.65GHz and 2.8GHz, respectively. As can be seen from the figure, the E-plane and H-plane directional patterns of the antenna have good symmetry at the frequency points of 0.5GHz, 1.65GHz and 2.8 GHz. The optimization results show that the pattern deteriorates at 2.8 GHz. As the frequency increases, the performance of the antenna gradually deteriorates and the pattern is distorted, probably because the antenna receives and radiates higher order electromagnetic wave modes as the frequency increases.
To sum up, the parameters of the antenna are optimized as follows: the dielectric substrate 1 is made of epoxy resin with a relative dielectric constant epsilon r of 4.4 and a dielectric loss tangent tan delta of 0.030, and the thickness of the dielectric substrate 1 is 0.8 mm. The first coplanar waveguide ground patch 4 and the second coplanar waveguide ground patch 5 are fan-shaped structures with an arc-shaped edge, and the radius R2 of the cross section of each fan-shaped structure is 78 mm. The impedance of the first coplanar waveguide grounding patch 4 and the second coplanar waveguide grounding patch 5 is 50 omega. The radiating patch 2 is a circular structure, the radius R1 of the radiating patch 2 is 90mm, and a plurality of fan-shaped ring grooves 20 are arranged at the periphery of the radiating patch 2 at intervals so as to improve the matching of the antenna and expand the bandwidth.
Further, the venation detection circuit of the venation detection module 20 includes a diode D, a capacitor C, and a resistor R, wherein the anode of the diode D is connected to the anode of the input terminal, one end of the capacitor C is connected in parallel with one end of the resistor R and then connected to the cathode of the diode D, the other end of the capacitor C is connected in parallel with the other end of the resistor R and then connected to the cathode of the input terminal, the two ends of the resistor R are used as output terminals, and the internal resistance of the diode D is smaller than the resistance value of the resistor R.
The detection method is one of the commonly used methods for reducing the signal frequency, and the specific principle is shown in fig. 10, and it can be known from the figure that when a high frequency signal pulse occurs, if the peak value is larger than the residual voltage of the capacitor, the diode D is turned on, the high frequency pulse signal is continuously charged to the capacitor C through the diode D until the instantaneous value of the high frequency pulse signal voltage is equal to the residual voltage of the capacitor, at this time, the diode D is turned off, and the capacitor C starts to release energy through the resistor R. The detection loop is easy to couple background noise generally, and in order to improve the accuracy of the online detection of the partial discharge, the background noise must be effectively suppressed to ensure the authenticity of the partial discharge detection, and the background noise can be suppressed through wavelet transformation. However, the wavelet desiccation effect depends on the similarity degree of the mother wavelet and the original pulse signal on the time domain waveform to a certain extent, and the relevance degree of the transformer partial discharge signal obtained by the ultrahigh frequency partial discharge detection antenna and the environment is very large. Therefore, certain difficulty is brought to the selection of the mother wavelet, different mother wavelets are required to be adopted for matching signals in a layered mode, and wavelets with high matching degree are selected as the optimal mother wavelet of the layer in different layers. The circuit, the matching and decoupling circuit of the resistor and the inductor can be properly added in the detection circuit, or eliminated in the later sampling circuit and the algorithm of the FPGA.
Further, referring to fig. 11, the FPGA parallel acquisition module 30 employs an EP1C6T144C8 chip from Altera corporation. Fig. 11 is a schematic diagram showing an output structure of a group of 6 signal pulses, and the other three groups of modules have the same structure except that the initial value of the reference counter is different.
In fig. 11, a PB port and a PE port of the digital signal processor are used as sixteen bit data lines for transmitting partial discharge pulse width values; four bits below the PF port of the digital signal processor are used as address lines for distinguishing pulse width data of different partial discharge sensing devices; WE of the digital signal processor is a write enable strobe pin, the low level is active, and when the WE is in parallel with the output CS of the decoder of the FPGA parallel acquisition module 30iMeanwhile, when the current level is low, the data on the data line is sent to a shadow register corresponding to the FPGA parallel acquisition module 30, wherein i is 0-11; the EN1 of the digital signal processor is a reference counter enable signal for initializing four reference counters of the FPGA parallel acquisition module 30; the EN2 of the digital signal processor is an interrupt request or gate enable signal of the FPGA parallel acquisition module 30; EN3 of the digital signal processor outputs an enabling blocking signal of a three-state gate for twenty-four-path partial discharge detection signals, the correctness of partial discharge data pulse is ensured, and the partial discharge detection signal is used in a stationWhen the discharge data detection fault occurs, the output pulse is blocked through EN3, so that the reliable operation of partial discharge detection is ensured; the external interrupt XINT1 of the digital signal processor receives an interrupt signal generated by a reference counter of the FPGA parallel acquisition module 30, and after responding to the interrupt, the external interrupt XINT1 calculates and sends a new partial discharge detection request value to the FPGA parallel acquisition module 30.
Fig. 12 is a hardware timing diagram of a FPGA parallel computing partial discharge acquisition data trigger pulse, and different partial discharge pulse width numbers can be generated by setting different partial discharge threshold values according to the partial discharge pulse signal generated in fig. 12, as shown in fig. 13. According to the relation between the serial number and the threshold value, the discharge amplitude and the phase of the partial discharge can be obtained, and the discharge amplitude and the phase of the partial discharge can be locked in a data latch module of the FPGA parallel acquisition module 30, so that the digital signal processor can evaluate and judge the amplitude and the phase of the partial discharge signal.
The above embodiments are illustrative of the present invention, and are not intended to limit the present invention, and any simple modifications of the present invention are within the scope of the present invention.
Claims (8)
1. The utility model provides a detecting system is put in SMD transformer office which characterized in that: comprises an ultrahigh frequency partial discharge detection sensor module (10), a venation detection module (20) and an FPGA parallel acquisition module (30), the ultrahigh frequency partial discharge detection sensor module (10) adopts a patch type structure, the output end of the ultrahigh frequency partial discharge detection sensor module (10) is connected with the venation detection module (20), the output end of the venation detection module (20) is connected with an FPGA parallel acquisition module (30), the ultrahigh frequency partial discharge detection sensor module (10) is used for receiving an ultrahigh frequency partial discharge signal generated by partial discharge of the transformer, the venation detection module (20) is used for reducing signal frequency, converting an ultrahigh frequency partial discharge signal received by the ultrahigh frequency partial discharge detection sensor module (10) into an envelope wave, carrying out multi-path parallel sampling by the FPGA parallel acquisition module (30), and transmitting the obtained partial discharge detection signal to the digital signal processor.
2. The patch type transformer partial discharge detection system according to claim 1, wherein: the antenna of the ultrahigh frequency partial discharge detection sensor module (10) comprises a dielectric substrate (1), a radiation patch (2), a coplanar waveguide feeder line (3), a first coplanar waveguide grounding patch (4) and a second coplanar waveguide grounding patch (5) which are printed on the top surface of the dielectric substrate (1), wherein the radiation patch (2) and the coplanar waveguide feeder line (3) are sequentially arranged from top to bottom, the first coplanar waveguide grounding patch (4) and the second coplanar waveguide grounding patch (5) are symmetrically arranged on two sides of the coplanar waveguide feeder line (3), gaps are reserved between the first coplanar waveguide grounding patch (4), the second coplanar waveguide grounding patch (5) and the coplanar waveguide feeder line (3), and the structures of the first coplanar waveguide grounding patch (4) and the second grounding patch (5) are the same.
3. The partial discharge detection system for the surface mounted transformer according to claim 2, wherein: the dielectric substrate (1) is made of epoxy resin with the relative dielectric constant epsilon r of 4.4 and the dielectric loss tangent tan delta of 0.030, and the thickness of the dielectric substrate (1) is 0.8 mm.
4. The partial discharge detection system for the surface mounted transformer according to claim 2, wherein: the first coplanar waveguide ground patch (4) and the second coplanar waveguide ground patch (5) are fan-shaped structures with an arc-shaped edge, and the radius R2 of the cross section of each fan-shaped structure is 78 mm.
5. The partial discharge detection system for the surface mounted transformer according to claim 3, wherein: the impedance of the first coplanar waveguide grounding patch (4) and the impedance of the second coplanar waveguide grounding patch (5) are 50 omega.
6. The partial discharge detection system for the surface mounted transformer according to claim 2, wherein: the radiation patch (2) is of a circular structure, the radius R1 of the radiation patch (2) is 90mm, and a plurality of fan-shaped annular grooves (20) are formed in the periphery of the radiation patch (2) at intervals.
7. The patch type transformer partial discharge detection system according to claim 1, wherein: the FPGA parallel acquisition module (30) adopts an EP1C6T144C8 chip and comprises a decoder, 4 partial discharge pulse width detection output comparison modules, an interrupt request OR gate and twenty-four partial discharge detection signal outputs, partial discharge pulse signals generated by the FPGA parallel acquisition module (30) can generate different partial discharge pulse width numbers by setting different partial discharge threshold values, the discharge amplitude and the phase of partial discharge can be obtained according to the relation between the numbers and the threshold values, and the partial discharge pulse signals are locked in a data latch module of the FPGA parallel acquisition module (30) so that a digital signal processor can evaluate and judge the amplitude and the phase of the partial discharge signals.
8. The system according to claim 7, wherein: the PB port and the PE port of the digital signal processor are used as sixteen-bit data lines and are used for transmitting partial discharge pulse width values; four lower bits of the PF port of the digital signal processor are used as address lines for distinguishing pulse width data of different partial discharge sensing devices; WE of the digital signal processor is a write enable strobe pin, the low level is effective, and when the WE is in parallel with the output CS of the decoder of the FPGA parallel acquisition module (30)iMeanwhile, when the current level is low, the data on the data line is sent into a shadow register corresponding to the FPGA parallel acquisition module (30), wherein i is 0-11; the EN1 of the digital signal processor is a reference counter enabling signal and is used for initializing four reference counters of the FPGA parallel acquisition module (30); the EN2 of the digital signal processor is an interrupt request or gate enable signal of the FPGA parallel acquisition module (30); the EN3 of the digital signal processor outputs enable blocking signals of a three-state gate for twenty-four paths of partial discharge detection signals, and blocks output pulses through EN3 when partial discharge data detection fails; the external interrupt XINT1 of the digital signal processor receives an interrupt signal generated by a reference counter of the FPGA parallel acquisition module (30), and after responding to the interrupt, the interrupt signal is calculated and then a new partial discharge detection request value is sent to the FPGA parallel acquisition module (30).
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114372063A (en) * | 2022-01-21 | 2022-04-19 | 华谱科仪(北京)科技有限公司 | Fault detection method based on chromatograph and electronic equipment |
| CN115575867A (en) * | 2022-11-28 | 2023-01-06 | 中国科学院合肥物质科学研究院 | Noise suppression compensation device suitable for multi-signal mixing operation and with output |
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