CN111128718A - Gap filling method - Google Patents

Gap filling method Download PDF

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Publication number
CN111128718A
CN111128718A CN201911363222.9A CN201911363222A CN111128718A CN 111128718 A CN111128718 A CN 111128718A CN 201911363222 A CN201911363222 A CN 201911363222A CN 111128718 A CN111128718 A CN 111128718A
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CN
China
Prior art keywords
medium
rate
groove
substrate
silane
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CN201911363222.9A
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Chinese (zh)
Inventor
王晓日
程刘锁
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Hua Hong Semiconductor Wuxi Co Ltd
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Hua Hong Semiconductor Wuxi Co Ltd
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Priority to CN201911363222.9A priority Critical patent/CN111128718A/en
Publication of CN111128718A publication Critical patent/CN111128718A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers

Abstract

The application discloses a gap filling method, which comprises the following steps: step S1, providing a substrate, wherein a groove is formed on the substrate; step S2, depositing a medium on the surfaces of the substrate and the groove by a PECVD process; step S3, sputtering the medium to flatten the surface of the medium; and step S4, repeating the step S2 and the step S3 until the groove is filled with the medium. According to the method, after the medium is deposited on the surfaces of the substrate and the groove of the substrate through the PECVD process, the medium is sputtered to flatten the surface of the medium, the two steps are repeatedly executed until the groove is filled with the medium to finish gap filling, and the surface of the medium is flattened in a sputtering mode in the filling process, so that the problem of cavities caused by uneven deposited medium films can be solved to a certain extent, and the yield is improved.

Description

Gap filling method
Technical Field
The application relates to the technical field of semiconductor manufacturing, in particular to a gap filling method.
Background
In the semiconductor manufacturing industry, as semiconductor devices continue to shrink, the aspect ratio of trenches of Shallow Trench Isolation (STI) structures is increasing. In view of this, the STI structure is typically filled by High Density Plasma Chemical Vapor Deposition (HDPCVD) Process or High Aspect-Ratio Process (HARP) Process to Fill the trench of the STI structure with a Gap (Gap Fill).
For shallow trenches with a depth of less than 500 nm and an aspect ratio of about 10, a Plasma Enhanced Chemical Vapor Deposition (PECVD) process is usually used for gap filling.
However, the STI structure filled by the PECVD process has a certain probability of voids (Void), which results in a low yield of the semiconductor device.
Disclosure of Invention
The application provides a gap filling method, which can solve the problem that the yield is low due to the fact that a cavity occurs at a certain probability in the gap filling method in the related art.
In one aspect, an embodiment of the present application provides a gap filling method, including:
step S1, providing a substrate, wherein a groove is formed on the substrate;
step S2, depositing media on the surfaces of the substrate and the groove through a PECVD process;
step S3, sputtering the medium to flatten the surface of the medium;
and step S4, repeating the step S2 and the step S3 until the groove is filled with the medium.
Optionally, the depth of the trench is less than 800 nm, and a ratio of the depth to the width of the trench is greater than 5.
Optionally, the dielectric comprises silicon oxide;
the depositing of the medium on the surface of the substrate and the groove by the PECVD process comprises the following steps:
introducing Silane (SH) into the reaction cavity by a PECVD process4) And oxygen, depositing the silicon oxide on the substrate and the trench surface by a reaction of silane and oxygen.
Optionally, in the process of depositing the silicon oxide, the rate of introducing the silane is reduced, and the rate of introducing the oxygen is increased to reduce the rate of depositing the silicon oxide.
Optionally, the silane is introduced at a rate of 700 Standard milliliter per Minute (SCCM) to 1100SCCM, and the oxygen is introduced at a rate of 1800SCCM to 2200 SCCM.
Optionally, the dielectric comprises silicon nitride;
the depositing of the medium on the surface of the substrate and the groove by the PECVD process comprises the following steps:
introducing silane and ammonia (NH) into the reaction cavity by PECVD process3) And depositing the silicon nitride on the substrate and the surface of the groove by reacting silane and ammonia gas.
Optionally, in the process of depositing the silicon nitride, the rate of introducing the ammonia gas is increased to reduce the rate of depositing the silicon nitride by reducing the rate of introducing the silane.
Optionally, the silane is introduced at a rate of 700SCCM to 1100SCCM and the ammonia is introduced at a rate of 1800SCCM to 2200 SCCM.
Optionally, the sputtering the medium to planarize a surface of the medium includes:
passing through nitrogen (N)2) Bombarding the medium to planarize a surface of the medium.
Optionally, the ratio of the time for performing the step S3 to the time for performing the step S2 is 3 to 7.
Optionally, the time for executing the step S2 is 5 seconds to 9 seconds.
Optionally, the time for executing the step S3 is 27 seconds to 40 seconds.
Optionally, the medium is bombarded by the nitrogen gas at a power of 600 watts to 1000 watts.
Optionally, after step S4, the method further includes:
step S5, performing planarization to remove the dielectric outside the trench, and forming a Shallow Trench Isolation (STI) structure.
Optionally, the removing the medium outside the trench by performing the planarization process includes:
the dielectric outside the trench is removed by a Chemical Mechanical Polishing (CMP) process.
The technical scheme at least comprises the following advantages:
after a medium is deposited on the surfaces of the substrate and the groove of the substrate through a PECVD process, the medium is sputtered to flatten the surface of the medium, the two steps are repeatedly executed until the groove is filled with the medium to finish gap filling, and the surface of the medium is flattened in a sputtering mode in the filling process, so that the problem of cavities caused by non-uniform deposited medium films can be solved to a certain extent, and the yield is improved.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a method flow diagram of a gap filling method provided by an exemplary embodiment of the present application;
FIG. 2 is a schematic illustration of a process for deposition of silane during a PECVD process;
fig. 3 to 5 are schematic diagrams of a gap filling process provided in an exemplary embodiment of the present application.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Exemplary embodiment 1:
referring to fig. 1, a flowchart of a method of gap filling provided in an exemplary embodiment of the present application is shown, and as shown in fig. 1, the method includes:
in step S1, a substrate having a trench formed thereon is provided.
Optionally, the depth of the trench is less than 800 nm, and the ratio of the depth to the width of the trench is greater than 5. For example, the depth of the trench may be less than 500 nanometers, with the ratio of the depth to the width of the trench being 10: 1.
Step S2, a dielectric is deposited on the surface of the substrate and the trench by a PECVD process.
Referring to fig. 2, a schematic diagram of the deposition of silane during a PECVD process is shown. As shown in fig. 2, in the deposition process, the phase of the alkylsilicon molecule 201 includes a gas phase, a gas phase and a solid phase mixture of an interface boundary layer, an adsorption layer and a solid phase of a thin film layer, and the deposition process includes:
in stage I, the silane molecules 201 move towards the surface of the substrate;
in stage II, the alkylsilicon molecules 201 are adsorbed or desorbed, and the reaction formula in this stage is: SiH4+ substrate Surface Site → SiH4(adsorbed);
in the stage III, the silane molecules 201 diffuse and migrate on the surface of the adsorption layer;
in stage IV, a reactive group (Precursor) is generated, and the reaction formula in the stage is as follows: SiH4(adsorbed) → SiH2(adsorbed) + H2(gas);
and a V stage, deposition reaction, wherein the reaction formula of the stage is as follows: SiH2(atom Abatom) → Si (solid) + H2(gas).
Referring to fig. 3, a cross-sectional view of a dielectric 320 deposited by a PECVD process on the surface of the substrate 310 and the trench 301 is shown. As shown in fig. 3, the dielectric 320 deposited on the surface of the substrate 310 and the trench 301 by the PECVD process has a poor surface topography.
In step S3, the medium is sputtered to planarize the surface of the medium.
Referring to fig. 4, a schematic illustration of the media 320 deposited in step S2 after sputtering is shown. By sputtering the deposited dielectric 320, the surface of the dielectric 320 is relatively flat, as shown in fig. 2.
Optionally, in this embodiment, the medium 520 is bombarded by nitrogen gas to planarize the surface of the medium 520; optionally, the medium 520 is bombarded with nitrogen gas at a power of 600 watts to 1000 watts. For example, the media 520 may be bombarded with nitrogen gas at a power of 800 watts.
And step S4, repeating the step S2 and the step S3 until the groove is filled with the medium.
Referring to fig. 5, a schematic illustration of the planarized surface of the medium after depositing the medium in step S3 is shown. By repeating the steps S2 and S3, the problem of voids caused by non-uniformity of the deposited dielectric thin film can be solved to some extent.
Optionally, in this embodiment, the ratio of the time for executing step S3 to the time for executing step S2 is 3 to 7; alternatively, the time for performing step S2 is 5 seconds to 9 seconds, and the time for performing step S3 is 27 seconds to 40 seconds. For example, the time for performing step S2 is 6 seconds, and the time for performing step S3 is 35 seconds.
It should be noted that, the trenches 301 are exemplarily illustrated in fig. 3 to 5, the number of the trenches is not limited in the present application, and one or more trenches may be formed on the substrate 310.
In summary, in the embodiment, after the dielectric is deposited on the surface of the substrate and the trench of the substrate by the PECVD process, the dielectric is sputtered to planarize the surface of the dielectric, and the two steps are repeatedly performed until the gap filling of the trench filling dielectric is completed.
Exemplary embodiment 2:
referring to exemplary embodiment 1, in the present embodiment, dielectric 320 includes silicon oxide (e.g., silicon dioxide, SiO)2) In step S2 of exemplary embodiment 1, "depositing a medium on the surface of the substrate and the trench by a PECVD process" includes, but is not limited to: silane and oxygen are introduced into the reaction cavity through a PECVD process, and silicon oxide is deposited on the surfaces of the substrate 310 and the groove 301 through the reaction of the silane and the oxygen.
Optionally, in this embodiment, in the process of depositing silicon oxide, the rate of introducing silane is reduced, and the rate of introducing oxygen is increased to reduce the rate of depositing silicon oxide. The density of the silicon oxide can be improved to a certain extent by reducing the rate of depositing the silicon oxide.
Optionally, in this embodiment, the silane is introduced at a rate of 700SCCM to 1100SCCM, and the oxygen is introduced at a rate of 1800SCCM to 2200 SCCM. For example, the silane was introduced at a rate of 900SCCM and the oxygen was introduced at a rate of 2000 SCCM.
Exemplary embodiment 3:
referring to exemplary embodiment 1, in the present embodiment, the medium 320 includes silicon nitride (e.g., silicon nitride SiN), and the "depositing a medium on the surface of the substrate and the trench by a PECVD process" in step S2 of exemplary embodiment 1 includes but is not limited to: silane and ammonia gas are introduced into the reaction cavity through a PECVD process, and silicon nitride is deposited on the surfaces of the substrate 310 and the groove 301 through the reaction of the silane and the ammonia gas.
Optionally, in this embodiment, in the process of depositing the silicon nitride, the rate of introducing the silane is reduced, and the rate of introducing the ammonia gas is increased to reduce the rate of depositing the silicon nitride. The densification of the silicon nitride can be improved to some extent by reducing the rate at which the silicon nitride is deposited.
Optionally, in this embodiment, the silane is introduced at a rate of 700SCCM to 1100SCCM, and the ammonia is introduced at a rate of 1800SCCM to 2200 SCCM. For example, the silane was fed at a rate of 900SCCM and the ammonia was fed at a rate of 2000 SCCM.
Example 4:
referring to exemplary embodiment 1 to exemplary embodiment 3, in the present embodiment, after step S4, the method further includes: in step S5, a planarization process is performed to remove the dielectric outside the trench 301, thereby forming an STI structure.
Optionally, the dielectric outside the trench 301 may be removed by a CMP process.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.

Claims (15)

1. A gap filling method, comprising:
step S1, providing a substrate, wherein a groove is formed on the substrate;
step S2, depositing media on the surfaces of the substrate and the groove through a PECVD process;
step S3, sputtering the medium to flatten the surface of the medium;
and step S4, repeating the step S2 and the step S3 until the groove is filled with the medium.
2. The method of claim 1 wherein the depth of the trench is less than 800 nanometers and the ratio of the depth to the width of the trench is greater than 5.
3. The method of claim 2, wherein the dielectric comprises silicon oxide;
the depositing of the medium on the surface of the substrate and the groove by the PECVD process comprises the following steps:
introducing silane and oxygen into the reaction cavity through a PECVD process, and depositing the silicon oxide on the substrate and the surface of the groove through the reaction of the silane and the oxygen.
4. The method of claim 3 wherein increasing the rate of oxygen decreases the rate of deposition of the silicon oxide by decreasing the rate of silane introduction during deposition of the silicon oxide.
5. The method of claim 4, wherein the silane is introduced at a rate of 700 to 1100SCCM and the oxygen is introduced at a rate of 1800 to 2200 SCCM.
6. The method of claim 2, wherein the dielectric comprises silicon nitride;
the depositing of the medium on the surface of the substrate and the groove by the PECVD process comprises the following steps:
introducing silane and ammonia gas into the reaction cavity through a PECVD process, and depositing the silicon nitride on the surfaces of the substrate and the groove through the reaction of the silane and the ammonia gas.
7. The method of claim 6 wherein increasing the rate of ammonia gas flow reduces the rate of deposition of the silicon nitride by reducing the rate of silane flow during deposition of the silicon nitride.
8. The method of claim 7, wherein the silane is introduced at a rate of 700 to 1100SCCM and the ammonia gas is introduced at a rate of 1800 to 2200 SCCM.
9. The method of any of claims 1 to 8, wherein sputtering the medium to planarize a surface of the medium comprises:
the medium is bombarded by nitrogen gas to planarize the surface of the medium.
10. The method as claimed in claim 9, wherein the ratio of the time for performing the step S3 to the time for performing the step S2 is 3 to 7.
11. The method of claim 10, wherein the step S2 is performed for 5 to 9 seconds.
12. The method of claim 11, wherein the step S3 is performed for 27 seconds to 40 seconds.
13. The method of claim 12, wherein the medium is bombarded by the nitrogen gas at a power of 600 to 1000 watts.
14. The method according to any one of claims 1 to 8, wherein after the step S4, the method further comprises:
and step S5, performing planarization treatment to remove the medium outside the groove, and forming an STI structure.
15. The method of claim 13, wherein the planarizing to remove the dielectric outside the trench comprises:
and removing the medium outside the groove through a CMP process.
CN201911363222.9A 2019-12-26 2019-12-26 Gap filling method Pending CN111128718A (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6191026B1 (en) * 1996-01-09 2001-02-20 Applied Materials, Inc. Method for submicron gap filling on a semiconductor substrate
US20060154494A1 (en) * 2005-01-08 2006-07-13 Applied Materials, Inc., A Delaware Corporation High-throughput HDP-CVD processes for advanced gapfill applications

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6191026B1 (en) * 1996-01-09 2001-02-20 Applied Materials, Inc. Method for submicron gap filling on a semiconductor substrate
US20060154494A1 (en) * 2005-01-08 2006-07-13 Applied Materials, Inc., A Delaware Corporation High-throughput HDP-CVD processes for advanced gapfill applications

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Application publication date: 20200508