CN111128259A - Power supply regulating circuit and method and memory - Google Patents
Power supply regulating circuit and method and memory Download PDFInfo
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
Abstract
The present disclosure relates to a power supply regulating circuit and method, and a memory, including: the device comprises a frequency control module, a clock module and a charge pump; the frequency control module is used for determining the frequency of the memory according to the configuration value of the column address gating delay of the memory; the clock module is connected with the frequency control module and is used for outputting a clock signal with a specified frequency according to the frequency of the memory; the charge pump is connected with the clock module, and the clock signal is used for controlling the charge pump to carry out boosting operation on the power supply voltage and outputting a trigger power supply. The method and the device realize real-time adjustment of the working frequency of the charge pump, and improve the transient response speed of the trigger power supply when the working frequency of the memory changes. And adjusting the operating frequency of the charge pump in real time according to the operating frequency of the memory reduces noise on the trigger power supply.
Description
Technical Field
The disclosure relates to the technical field of memories, in particular to a power supply regulating circuit and method and a memory.
Background
With the development and progress of the technology, the memory chip is more and more widely applied to various electronic products, in the working process of the memory, the switching frequency of the word line is related to the working frequency of the memory chip, and the trigger power supply VPP provides a high-voltage power supply for the turning on of the word line, so that the stability of the trigger power supply VPP is very important for the normal operation of the memory chip.
Currently, during the operation of a memory chip, the VPP voltage amplitude is dynamically monitored in real time, so as to control the on/off of the oscillation clock of the charge pump circuit, thereby obtaining a stable trigger power VPP. However, when the operating frequency of the memory changes, the clock frequency of the charge pump circuit is not adaptively adjusted, which results in a low transient response speed of the trigger power supply VPP and a high noise of the trigger power supply VPP.
It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.
Disclosure of Invention
The present disclosure is directed to a power supply regulation circuit, a power supply regulation method, and a memory, which overcome, at least to some extent, the problems of low transient response speed and high noise of a trigger power supply VPP due to the limitations and disadvantages of the related art.
According to a first aspect of the present disclosure, there is provided a power supply regulation circuit, comprising:
the frequency control module is used for outputting a first control signal according to the configuration value of the column address gating delay of the memory;
the clock module is connected with the frequency control module and used for outputting a clock signal with a specified frequency according to the first control signal;
and the clock signal is used for controlling the charge pump to carry out boosting operation on the power supply voltage and outputting a trigger power supply for starting a word line.
According to an embodiment of the present disclosure, the frequency control module includes:
the selection circuit acquires the configuration value, determines the frequency of the memory according to the configuration value and outputs a first control signal.
According to an embodiment of the present disclosure, the power supply regulating circuit further includes:
and the mode register is connected with the frequency control module and is used for storing the configuration value of the column address gating delay.
According to an embodiment of the present disclosure, the power supply regulating circuit further includes:
and the input end of the comparator is connected with the output end of the charge pump, and the output end of the comparator is connected with the clock module and used for comparing the trigger power supply with a preset voltage value and feeding back a comparison result to the clock module.
According to an embodiment of the present disclosure, the clock module includes:
the oscillator is connected with the frequency control module and used for generating a first clock signal according to the first control signal;
the input end of the non-overlapping clock generating circuit is connected with the oscillator, and the output end of the non-overlapping clock generating circuit is connected with the charge pump and used for converting a first clock signal into a second clock signal;
the second clock signal is a non-overlapping clock signal and is used for controlling the charge pump to perform boosting operation on the power supply voltage.
According to an embodiment of the present disclosure, the memory includes a dynamic random access memory.
According to a second aspect of the present disclosure, there is provided a power supply regulation method comprising:
outputting a first control signal according to a configuration value of a column address strobe delay of a memory;
outputting a clock signal with a specified frequency according to the first control signal;
and controlling the charge pump to boost the power supply voltage through the clock signal, and outputting the boosted trigger power supply.
According to an embodiment of the present disclosure, before outputting the first control signal according to the configuration value of the column address strobe delay of the memory, the method further includes:
and acquiring the configuration value of the column address gating delay, wherein the configuration value of the column address gating delay is stored in a mode register.
According to an embodiment of the present disclosure, outputting a clock signal of a specified frequency according to the first control signal includes:
generating a first clock signal according to the first control signal;
and converting the first clock signal into a second clock signal, wherein the second clock signal is a non-overlapping clock signal and is used for controlling the charge pump to perform boosting operation on the power supply voltage.
According to an embodiment of the present disclosure, after controlling the charge pump to boost the power supply voltage and output the boosted trigger power supply by the clock signal, the method further includes:
and comparing the trigger power supply with a preset voltage, controlling the charge pump to reduce the voltage of the output trigger power supply when the trigger power supply is higher than the preset voltage, and controlling the charge pump to increase the voltage of the output trigger power supply when the trigger power supply is lower than the preset voltage.
According to a third aspect of the present disclosure, there is provided a memory including the above power supply regulating circuit.
The utility model provides a power supply regulating circuit, through the frequency control module frequency of confirming the memory, clock module exports the clock signal of appointed frequency according to the frequency of memory, triggers the power supply through clock signal control charge pump output. The clock signal is determined according to the configuration value of the column address gating delay, when the configuration value of the column address gating delay changes, the clock module outputs the clock signal with the corresponding frequency according to the configuration value of the column address gating delay, the charge pump outputs the trigger power supply according to the clock signal, the trigger power supply is adjusted according to the working frequency change of the storage, the problems of low transient response speed and high noise of the trigger power supply caused by the fact that the frequency of the clock signal is unchanged due to the frequency change of the storage are solved, the transient response speed of the trigger power supply is improved, and the noise of the trigger power supply is reduced.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty.
Fig. 1 is a schematic diagram of a power supply regulating circuit according to an exemplary embodiment of the present disclosure.
Fig. 2 is a circuit diagram of a selection circuit according to an exemplary embodiment of the disclosure.
Fig. 3 is a flowchart of a first power supply regulation method according to an exemplary embodiment of the present disclosure.
Fig. 4 is a flowchart of a second power supply regulation method provided in an exemplary embodiment of the present disclosure.
Fig. 5 is a flowchart of a second power supply regulation method provided in an exemplary embodiment of the present disclosure.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed description will be omitted.
The terms "a," "an," "the," "said," and "at least one" are used to indicate the presence of one or more elements/components/parts/etc.; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. other than the listed elements/components/etc.; the terms "first," "second," and "third," etc. are used merely as labels, and are not limiting on the number of their objects.
The block diagrams shown in the figures are functional entities only and do not necessarily correspond to physically separate entities. That is, these functional entities may be implemented in software, or in one or more software hardened modules, or in different networks and/or processor circuits and/or microcontroller circuits.
In the related art, a word line in a memory is triggered by an internal trigger power supply VPP, and the frequency of the memory is related to the switching frequency of the word line. When the frequency of the memory changes, the clock frequency of the charge pump circuit cannot be adaptively adjusted, so that the transient response speed of the trigger power supply VPP is low, and the trigger power supply VPP is easily interfered by noise.
First, a power supply regulating circuit is provided in the present exemplary embodiment, as shown in fig. 1, the power supply regulating circuit includes a frequency control module 100, a clock module 200 and a charge pump 300, the frequency control module 100 is configured to output a first control signal according to a configuration value of a Column Address Strobe delay (CL) of a memory; the clock module 200 is connected to the frequency control module 100, and receives a first control signal, and is configured to output a clock signal with a specified frequency according to a first control; the charge pump 300 is connected to the clock module 200, and the clock signal is used to control the charge pump 300 to perform a boosting operation on the power supply voltage and output a trigger power supply VPP.
The power supply regulating circuit provided by the embodiment of the disclosure determines the frequency of the memory through the frequency control module 100, the clock module 200 outputs a clock signal with a specified frequency according to the frequency of the memory, and controls the charge pump 300 to output the trigger power supply VPP through the clock signal. Since the clock signal is determined according to the configuration value of CL, when the frequency of the memory changes, the configuration value of CL changes, the clock module 200 outputs the clock signal with the corresponding frequency according to the configuration value of CL, and the charge pump 300 outputs the trigger power VPP according to the clock signal. When the configuration of the working frequency of the memory is changed, the load current of the trigger power supply VPP is changed, and the frequency of the clock signal output by the clock module is not changed, so that the transient response speed of the trigger power supply VPP is low and the noise is large.
When the working frequency of the memory changes, the working frequency and the working current value of a load connected with the trigger power supply VPP also change, when the word line is conducted, the voltage value of the trigger power supply VPP fluctuates, and the trigger power supply VPP can be quickly adjusted to be recovered to the preset voltage range through the clock signal matched with the working frequency of the memory. The response speed of the trigger power supply VPP to the load change is improved, and the noise generated by the influence of the load change on the trigger power supply VPP is reduced.
Further, the power supply regulating circuit provided by the embodiment of the present disclosure further includes a mode register 500, where the mode register 500 is used for storing the configuration value of CL, and is connected to the frequency control module 100. The mode register 500 may be, among other things, an MRS register.
The frequency control module 100 obtains the configuration value signal of CL from the mode register 500. The configuration values of the CL are preset in the mode register 500, and the configuration values of the CL may correspond to the memory cycles one to one, that is, correspond to the frequencies of the memory one to one, for example, the corresponding relationship between the configuration values of the CL and the memory cycles may be as shown in table 1.
TABLE 1
The frequency control module obtains the current configuration value signal of the CL from the mode register 500, determines the frequency of the memory according to the current configuration value of the CL, and the clock module may preset a plurality of operation modes corresponding to the configuration value of the CL, and selects one operation mode of the clock module through the first control signal corresponding to the configuration value of the CL, so that the clock module outputs the clock signal of the preset frequency.
The frequency control module 100 may include a selection circuit having multiple input terminals, and the mode register 500 may output multiple signals when outputting the configuration value signal of CL, where each of the configuration value signals of CL corresponds to an input terminal of the selection circuit.
For example, as shown in the CL in table 1, the mode register 500 may output four signals to control the selection circuit to determine the configuration value of the corresponding CL, and thus determine the frequency of the memory. The selection circuit shown in fig. 2 has four signal inputs. The signal of the first input terminal S1 is input into nine three-input and gates, wherein inverters are arranged between the first three-input and gate a11, the second three-input and gate a12, the third three-input and gate a13 and the first input terminal S1; nine three-input and gates are input by signals of the second input end S2, wherein inverters are arranged among the fourth three-input and gate a14, the fifth three-input and gate a15, the sixth three-input and gate a16 and the second input end S2, nine three-input and gates are input by signals of the third input end, and inverters are arranged among the first three-input and gate a11, the fourth three-input and gate a14, the fifth three-input and gate a15, the eighth three-input and gate a18 and the third input end S3.
The output end of the three-input AND gate is connected with one input end of the two-input AND gate, the other input end of the two-input AND gate inputs a signal of a fourth input end S4, wherein an inverter is arranged among the first two-input AND gate A21, the second two-input AND gate A22, the fourth two-input AND gate A24, the sixth two-input AND gate A26, the eighth two-input AND gate A28 and the fourth input end S4.
The output ends of a second input AND gate A22 and a third second input AND gate A23 are respectively connected with the input of a first OR gate O1, the output ends of a fifth second input AND gate A25 and a ninth second input AND gate A29 are respectively connected with the input of a second OR gate O2, the output ends of a fourth second input AND gate A24 and an eighth second input AND gate A28 are respectively connected with the input of a third OR gate O3, and the output ends of a third second input AND gate A23 and a seventh second input AND gate A27 are respectively connected with the input of a fourth OR gate O4.
The output signals of the first two-input AND gate A21 correspond to DDR4-1866, the output signals of the sixth two-input AND gate A26 correspond to DDR4-3200, the output signals of the first OR gate O1 correspond to DDR4-2133, the output signals of the second OR gate O2 correspond to DDR4-2933, the output signals of the third OR gate O3 correspond to DDR4-2666, and the output signals of the fourth OR gate O4 correspond to DDR 4-2400. The correspondence between the CL configuration value signal and the CL configuration value output from the mode register 500 is shown in table 2.
TABLE 2
| Period of time | CL | CL signal |
| 0.625ns | 22(DDR4-3200) | 1010 |
| 0.682ns | 21(DDR4-2933) | 1001 |
| 0.682ns | 20(DDR4-2933) | 1111 |
| 0.750ns | 19(DDR4-2666) | 1000 |
| 0.750ns | 18(DDR4-2666) | 1110 |
| 0.833ns | 17(DDR4-2400) | 0111 |
| 0.833ns | 16(DDR4-2400) | 1101 |
| 0.937ns | 15(DDR4-2133) | 0110 |
| 0.937ns | 14(DDR4-2133) | 0111 |
| 1.071ns | 13(DDR4-1866) | 0100 |
In the table, the configuration value signals of CL are arranged in the order of the first input second input terminal, the third input terminal, and the fourth input terminal.
For another example, if CL is 4bit, its value may be 0000 to 1111, and when CL is 0000 to 0011, the frequency control module outputs the first control signal 00; when CL is 0100-0111, the frequency control module outputs a first control signal 01; when CL is 1000-1011, the frequency control module outputs a first control signal 10; when CL is 1100-1111, the frequency control module outputs a first control signal 11. At the moment, the oscillator can preset four working modes, and 00-11 respectively control the four working modes of the oscillator to generate four clock signals with different frequencies.
The clock module 200 may include: an oscillator 210 and a non-overlap clock generating circuit 220, wherein the oscillator 210 is connected to the frequency control module 100 and is used for generating a first clock signal according to the frequency of the memory; the non-overlap clock generation circuit 220 has an input terminal connected to the oscillator 210 and an output terminal connected to the charge pump 300, and is configured to convert the first clock signal into a second clock signal; the second clock signal is a non-overlapping clock signal, and is used to control the charge pump 300 to perform a boosting operation on the power supply voltage and output a trigger power supply VPP.
The frequency control module 100 outputs a first control signal to control the oscillator 210 to output a first clock signal after determining the memory frequency. The first clock signal may be a voltage signal, in which case the oscillator 210 may be a voltage-controlled oscillator, the frequency of the first clock signal that the oscillator 210 needs to output is determined according to the frequency of the memory, and the oscillator 210 is controlled to output the first clock signal of the designated frequency by responding to the voltage signal of the amplitude. For example, eight configuration values of CL are set in the mode register 500, the output frequency of the vco 210 required by the memory frequency corresponding to each configuration value of CL can be calculated, eight control voltage values are set according to the output frequency requirement of the oscillator 210, and correspond to the first control signals one to one, and when the corresponding first control signal is triggered, the oscillator 210 is controlled to output the first clock signal through the corresponding voltage signal.
Certainly, in practical applications, the oscillator 210 may also be another type of oscillator, and the frequency of the first clock signal output by the oscillator 210 may be controlled by controlling the input current of the oscillator 210 or the capacitor in the oscillator 210 through the first control signal, which is not specifically limited in this embodiment of the disclosure.
In order to avoid that the capacitor in the charge pump 300 enters a working state when the capacitor is not fully charged and discharged, and the conduction time and the performance of the switching tube are affected, the first clock signal can be converted into a non-overlapping second clock signal through the non-overlapping clock generation circuit 220, and the second clock signal controls the charge pump 300 to output the trigger power supply VPP, so that the accuracy of the conduction time of the charge pump 300 is ensured, and the switching performance is improved, wherein the second clock signal can comprise two paths of signals.
The working state of the charge pump 300 is controlled by a second clock signal, when the voltage of the trigger power supply VPP is low, the comparator 400 does not work, and the second clock signal is generated to raise the voltage of the trigger power supply VPP; when the voltage of the trigger power VPP is higher, the comparator 400 generates a signal to turn off the clock module 200, the second clock signal is turned off, and the trigger power VPP is gradually lowered. When the word line of the memory is triggered, the trigger power supply VPP reaches a preset voltage, which is a voltage value capable of turning on the word line in the memory, and then the word line is turned on. In order to control the size of the trigger power VPP, the power conditioning circuit provided in the embodiment of the present disclosure may further include: a comparator 400, an input terminal of which is connected to the output terminal of the charge pump 300, and an output terminal of which is connected to the oscillator 210, for comparing the trigger power VPP with a preset voltage value. The comparator 400 obtains the trigger power VPP outputted by the charge pump 300, compares the trigger power VPP with a preset voltage value, and controls the oscillator 210 to adjust the outputted first clock signal and reduce the trigger power VPP if the trigger power VPP is greater than the preset voltage value; when the trigger power VPP is smaller than the predetermined voltage value, the control oscillator 210 adjusts the output first clock signal to increase the trigger power VPP. For example, when the trigger power VPP is higher than the preset voltage, the oscillator 210 is turned off, the output of the first clock signal is stopped, and the trigger power VPP is lowered, and when the trigger power VPP is lower than the preset voltage, the oscillator 210 is turned on, and the first clock signal is output, and the trigger power VPP is raised.
The memory described in the embodiment of the present disclosure may be a DRAM, and certainly may also be an SRAM or a NAND in practical applications, which is not specifically limited in the embodiment of the present disclosure.
There is also provided in this example embodiment a power supply regulation method, as shown in fig. 3, including the steps of:
step S310, outputting a first control signal according to the configuration value of the column address strobe delay CL of the memory;
step S320, outputting a clock signal with a specified frequency according to the first control signal;
and step S330, controlling the charge pump to boost the power supply voltage through the clock signal, and outputting the boosted trigger power supply.
According to the power supply adjusting method provided by the embodiment of the disclosure, the first control signal is output through the configuration value of the column address gating delay CL of the memory, the clock module outputs the clock signal with the designated frequency according to the first control signal, and the output of the charge pump is controlled to trigger the power supply through the clock signal. The clock signal is determined according to the configuration value of the column address gating delay CL, when the frequency of the memory changes, the configuration value of the column address gating delay CL changes, the clock module outputs the clock signal with the corresponding frequency according to the configuration value of the column address gating delay CL, the charge pump outputs the trigger power supply according to the clock signal, real-time adjustment of the trigger power supply is achieved, the problems that the transient response speed of the trigger power supply is low and the noise is large due to the fact that the frequency of the clock signal is unchanged due to the change of the frequency of the memory are solved, the transient response speed of the trigger power supply is improved, and the noise of the trigger power supply is reduced.
In step S310, a first control signal is output according to the configuration value of the column address strobe delay CL of the memory.
The configuration value of the CL corresponds to the operating frequency of the memory one to one, the frequency determining circuit determines the frequency of the memory according to the configuration value of the CL, and the frequency control module 100 obtains the configuration value signal of the CL, determines the memory frequency corresponding to the configuration value of the current CL, and outputs a first control signal. The frequency of the memory can be determined by a selection circuit as shown in fig. 2, multiple input signals are input into the selection circuit, the selection circuit determines the configuration value of CL, and further determines the frequency of the memory, and a first control signal is output according to the frequency of the memory.
In step S320, a clock signal of a designated frequency may be output according to the first control signal.
The clock module 200 outputs a clock signal, and the frequency of the clock signal is controlled by a first control signal, for example, eight CL configuration values are set in the memory, and each CL configuration value corresponds to one first control signal. Each of the first control signals may control the clock module 200 to output a clock signal of a designated frequency.
In step S330, the charge pump 300 may be controlled to perform a boosting operation on the power supply voltage by the clock signal, and output the boosted trigger power supply.
The charge pump 300 is controlled by a clock signal, and a trigger power VPP is output to trigger the word line in the memory to be turned on.
Optionally, as shown in fig. 4, before step S310, the method further includes:
step S340, obtaining the configuration value of the column address gating delay CL, where the configuration value of the column address gating delay CL is stored in the mode register.
The mode register 500 is connected to the frequency control module 100, and the frequency control module 100 obtains the configuration value of CL from the mode register 500. The configuration values of CL, which are preset in the mode register 500, may correspond to the memory cycles, i.e., the frequencies of the memory.
Further, as shown in fig. 5, step S320 may include:
step S321, generating a first clock signal according to the first control signal;
step S322, converting the first clock signal into a second clock signal, where the second clock signal is a non-overlapping clock signal, and is used to control the charge pump to perform a voltage boosting operation on the power supply voltage and output a trigger power supply.
In step S321, a first clock signal may be generated by the oscillator 210 under the control of a first control signal, and a frequency of the first clock signal is determined by a frequency of the memory and is used for controlling the charge pump output trigger power supply VPP.
In step S322, the first clock signal may be converted into a second clock signal by the non-overlap clock circuit, and the second clock signal is a non-overlap clock signal. The charge pump 300 is controlled to output the trigger power supply VPP through the second clock signal, so that the accuracy of the conduction time of the charge pump 300 is ensured, and the switching performance is improved.
Further, after step S330, the method may further include:
step S350, comparing the trigger power supply with a preset voltage, controlling the charge pump to decrease the voltage of the output trigger power supply when the trigger power supply is higher than the preset voltage, and controlling the charge pump 300 to increase the voltage of the output trigger power supply when the trigger power supply is lower than the preset voltage.
The trigger power supply VPP and the preset voltage value can be compared by the comparator 400, the comparator 400 obtains the trigger power supply VPP output by the charge pump 300, compares the trigger power supply VPP with the preset voltage value, and controls the oscillator 210 to adjust the output first clock signal if the trigger power supply VPP is greater than the preset voltage value, thereby reducing the trigger power supply VPP and power consumption; when the trigger power VPP is smaller than the predetermined voltage value, the control oscillator 210 adjusts the output first clock signal to increase the trigger power VPP. For example, when the trigger power VPP is higher than the preset voltage, the oscillator 210 may be turned off to stop outputting the first clock signal, so that the trigger power VPP is lowered, and when the trigger power VPP is lower than the preset voltage, the oscillator 210 may be turned on to output the first clock signal, so that the trigger power VPP is raised.
It should be noted that although the various steps of the methods of the present disclosure are depicted in the drawings in a particular order, this does not require or imply that these steps must be performed in this particular order, or that all of the depicted steps must be performed, to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step execution, and/or one step broken down into multiple step executions, etc.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
Claims (11)
1. A power supply regulation circuit, comprising:
the frequency control module is used for outputting a first control signal according to the configuration value of the column address gating delay of the memory;
the clock module is connected with the frequency control module and used for outputting a clock signal with a specified frequency according to the first control signal;
and the clock signal is used for controlling the charge pump to carry out boosting operation on the power supply voltage and outputting a trigger power supply for starting a word line.
2. The power supply regulation circuit of claim 1, wherein the frequency control module comprises:
and the selection circuit acquires the configuration value of the column address gating delay, determines the frequency of the memory according to the configuration value of the column address gating delay and outputs a first control signal.
3. The power supply regulation circuit of claim 1, further comprising:
and the mode register is connected with the frequency control module and is used for storing the configuration value of the column address gating delay.
4. The power supply regulation circuit of claim 1, further comprising:
and the input end of the comparator is connected with the output end of the charge pump, and the output end of the comparator is connected with the clock module and used for comparing the trigger power supply with a preset voltage value and feeding back a comparison result to the clock module.
5. The power supply regulation circuit of claim 1, wherein the clock module comprises:
the oscillator is connected with the frequency control module and used for generating a first clock signal according to the first control signal;
the input end of the non-overlapping clock generating circuit is connected with the oscillator, and the output end of the non-overlapping clock generating circuit is connected with the charge pump and used for converting a first clock signal into a second clock signal;
the second clock signal is a non-overlapping clock signal and is used for controlling the charge pump to perform boosting operation on the power supply voltage.
6. The power supply regulation circuit of any one of claims 1 to 5 wherein the memory comprises a dynamic random access memory.
7. A method of regulating a power supply, comprising:
outputting a first control signal according to a configuration value of a column address strobe delay of a memory;
outputting a clock signal with a specified frequency according to the first control signal;
and controlling the charge pump to boost the power supply voltage through the clock signal, and outputting the boosted trigger power supply.
8. The power supply regulation method of claim 7 wherein before outputting the first control signal according to the configuration value of the column address strobe delay of the memory, further comprising:
and acquiring the configuration value of the column address gating delay, wherein the configuration value of the column address gating delay is stored in a mode register.
9. The power supply regulation method of claim 7 wherein outputting a clock signal of a specified frequency in accordance with the first control signal comprises:
generating a first clock signal according to the first control signal;
and converting the first clock signal into a second clock signal, wherein the second clock signal is a non-overlapping clock signal and is used for controlling the charge pump to perform boosting operation on the power supply voltage.
10. The power supply regulation method of claim 7, wherein after controlling the charge pump to perform a boosting operation of the power supply voltage and outputting the boosted trigger power supply by the clock signal, further comprising:
and comparing the trigger power supply with a preset voltage, controlling the charge pump to reduce the voltage of the output trigger power supply when the trigger power supply is higher than the preset voltage, and controlling the charge pump to increase the voltage of the output trigger power supply when the trigger power supply is lower than the preset voltage.
11. A memory comprising a power supply regulation circuit as claimed in any one of claims 1 to 6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811278867.8A CN111128259A (en) | 2018-10-30 | 2018-10-30 | Power supply regulating circuit and method and memory |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201811278867.8A CN111128259A (en) | 2018-10-30 | 2018-10-30 | Power supply regulating circuit and method and memory |
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| CN111128259A true CN111128259A (en) | 2020-05-08 |
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| CN201811278867.8A Pending CN111128259A (en) | 2018-10-30 | 2018-10-30 | Power supply regulating circuit and method and memory |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08180676A (en) * | 1994-12-22 | 1996-07-12 | Mitsubishi Electric Corp | Synchronous semiconductor memory |
| JPH09245476A (en) * | 1996-03-05 | 1997-09-19 | Mitsubishi Electric Corp | Semiconductor memory |
| US5754838A (en) * | 1994-12-27 | 1998-05-19 | Hitachi, Ltd. | Synchronous dynamic memory device capable of operating over wide range of operation frequencies |
| US20090257289A1 (en) * | 2008-04-14 | 2009-10-15 | Sang-Jin Byeon | Internal voltage generator and semiconductor memory device including the same |
| CN108399930A (en) * | 2018-02-12 | 2018-08-14 | 宁波宇喆电子科技有限公司 | A kind of low-power consumption programming high voltage generation circuit |
| CN209281892U (en) * | 2018-10-30 | 2019-08-20 | 长鑫存储技术有限公司 | Power source regulating circuit and memory |
-
2018
- 2018-10-30 CN CN201811278867.8A patent/CN111128259A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08180676A (en) * | 1994-12-22 | 1996-07-12 | Mitsubishi Electric Corp | Synchronous semiconductor memory |
| US5754838A (en) * | 1994-12-27 | 1998-05-19 | Hitachi, Ltd. | Synchronous dynamic memory device capable of operating over wide range of operation frequencies |
| JPH09245476A (en) * | 1996-03-05 | 1997-09-19 | Mitsubishi Electric Corp | Semiconductor memory |
| US20090257289A1 (en) * | 2008-04-14 | 2009-10-15 | Sang-Jin Byeon | Internal voltage generator and semiconductor memory device including the same |
| CN108399930A (en) * | 2018-02-12 | 2018-08-14 | 宁波宇喆电子科技有限公司 | A kind of low-power consumption programming high voltage generation circuit |
| CN209281892U (en) * | 2018-10-30 | 2019-08-20 | 长鑫存储技术有限公司 | Power source regulating circuit and memory |
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