CN111128093B - Image zooming circuit, image zooming controller and display device - Google Patents
Image zooming circuit, image zooming controller and display device Download PDFInfo
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- CN111128093B CN111128093B CN201911329209.1A CN201911329209A CN111128093B CN 111128093 B CN111128093 B CN 111128093B CN 201911329209 A CN201911329209 A CN 201911329209A CN 111128093 B CN111128093 B CN 111128093B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/22—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of characters or indicia using display control signals derived from coded signals representing the characters or indicia, e.g. with a character-code memory
- G09G5/24—Generation of individual character patterns
- G09G5/26—Generation of individual character patterns for modifying the character dimensions, e.g. double width, double height
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- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T3/00—Geometric image transformation in the plane of the image
- G06T3/40—Scaling the whole image or part thereof
Abstract
The application discloses an image zooming circuit, an image zooming controller and a display device, wherein the image zooming circuit comprises a parameter definition module, a mode control module and a zooming kernel module; the parameter definition module is used for carrying out parameter configuration on image zooming, and the mode control module is used for controlling the zooming kernel module to carry out zooming processing on the input image data and outputting the processed image data according to the parameters configured by the parameter definition module, the type of the input image data and the state of the zooming kernel module. By the method, the image can be zoomed, the image zooming effect can be flexibly configured, and the operation is easy.
Description
Technical Field
The present invention relates to the field of image processing technologies, and in particular, to an image scaling circuit, an image scaling controller, and a display device.
Background
In the field of image processing, image and video reduction and enlargement are common functions, and the purpose is to convert an input image from one resolution to another resolution for output, and simultaneously meet the requirements of real-time input and real-time output of video. The method is widely applied to the field of video playing and image analysis.
Disclosure of Invention
In order to solve the above problems, the present application provides an image scaling circuit, an image scaling controller, and a display device, which can implement scaling of an image, and can flexibly configure the effect of image scaling, and are easy to operate.
The technical scheme adopted by the application is as follows: providing an image scaling circuit, wherein the image scaling circuit comprises a parameter definition module, a mode control module and a scaling kernel module; the parameter definition module is used for carrying out parameter configuration on image zooming, the mode control module is used for determining a resolution parameter source according to the parameter dynamic configuration enabling signal when the parameter dynamic configuration enabling signal configured by the parameter definition module is used for dynamically configuring the enabling signal according to the parameter, acquiring a corresponding resolution parameter according to the resolution parameter source, controlling the zooming kernel module to carry out zooming processing on input image data according to the acquired resolution parameter, the type of the input image data and the state of the zooming kernel module, and outputting the processed image data.
The parameters of the parameter definition module configuration comprise at least one of image format, data source, data bit width, input and output image resolution and whether dynamic configuration is allowed or not.
Wherein the resolution parameter value source comprises a resolution parameter of the input port and a static resolution parameter.
The mode control module is further configured to obtain a resolution parameter of the input port in response to an input parameter update instruction, so as to update the resolution parameter.
The mode control module is also used for responding to an input amplification/reduction selection instruction when in the Memory mode, and controlling an information source data request signal, a kernel data request signal and a data effective signal to select different control modes for output; or the mode control module is also used for regenerating a new kernel data request signal and a new data effective signal according to the output buffer empty state in the Live mode, wherein the data effective signal is a signal obtained after the kernel data request signal is delayed by 2 beats; the Memory mode indicates reading image data from a Memory and inputting the image data, and the Live mode indicates inputting parallel image data.
Wherein the scaling kernel module comprises: the vertical calculation submodule is used for carrying out scaling processing in the vertical direction on input image data; the horizontal calculation submodule is used for carrying out scaling processing in the horizontal direction on input image data; the row calculation control state machine submodule is used for controlling the state of row calculation and generating calculation enabling and control signals to control the work of the vertical calculation submodule and the horizontal calculation submodule; and the output row cache submodule is used for receiving and outputting the image data output by the vertical calculation submodule or the horizontal calculation submodule.
Wherein, the vertical calculation submodule includes: the vertical coordinate conversion module is used for responding to the row calculation enabling signal, accumulating the scaling factors in the vertical direction and calculating the mapping row address and the phase value of the input target image in the original image; the vertical line cache module is used for caching the input image data and reading the image data to be calculated according to the mapping line address; the vertical coefficient generating module is used for reading coefficient data to be calculated according to the phase value; and the vertical multiplication and addition module is used for performing multiplication and addition operation on the image data to be calculated and the coefficient data to be calculated.
Wherein, the level calculation submodule comprises: the horizontal coordinate conversion module is used for responding to the row calculation enabling signal, accumulating the scaling factors in the horizontal direction and calculating the mapping pixel address and the phase value of the input target image in the original image; the horizontal line cache module is used for caching the input image data and reading the image data to be calculated according to the mapping pixel address; the horizontal coefficient generating module is used for reading coefficient data to be calculated according to the phase value; and the horizontal multiplication and addition module is used for performing multiplication and addition operation on the image data to be calculated and the coefficient data to be calculated.
Another technical scheme adopted by the application is as follows: there is provided an image scaling controller comprising an input port, an output port and an image scaling circuit connecting the input port and the output port, wherein the image scaling circuit is an image scaling circuit as described above.
Another technical scheme adopted by the application is as follows: there is provided a display device comprising an image scaling controller as described above.
The image zooming circuit comprises a parameter definition module, a mode control module and a zooming kernel module; the parameter definition module is used for carrying out parameter configuration on image zooming, and the mode control module is used for controlling the zooming kernel module to carry out zooming processing on an input image source and outputting the processed image data according to the parameters configured by the parameter definition module, the type of the input image data and the state of the zooming kernel. By the method, the image or the video is reduced and amplified, different types and effects of images can be zoomed differently by a parameter configurable mode, and the method has the characteristics of flexible configuration, convenient operation, program portability and the like.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts. Wherein:
FIG. 1 is a schematic diagram of an embodiment of an image scaling controller provided in the present application;
FIG. 2 is a schematic structural diagram of a kernel module provided in the present application;
FIG. 3 is a schematic diagram of a vertical computing submodule provided in the present application;
FIG. 4 is a schematic diagram of the structure of the horizontal computing submodule provided in the present application;
FIG. 5 is another schematic structural diagram of a kernel module provided in the present application;
FIG. 6 is a control flow diagram of a row computation control state machine submodule provided in the present application;
fig. 7 is a schematic structural diagram of an embodiment of a display device provided in the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the specific embodiments described herein are merely illustrative of the application and are not limiting of the application. It should be further noted that, for the convenience of description, only some of the structures related to the present application are shown in the drawings, not all of the structures. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The terms "first", "second", etc. in this application are used to distinguish between different objects and not to describe a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.
Referring to fig. 1, fig. 1 is a schematic structural diagram of an embodiment of an image scaling controller provided in the present application, where the image scaling controller 10 includes a parameter definition module 11, a mode control module 12, and a scaling kernel module 13.
The parameter definition module 11 is configured to perform parameter configuration for image scaling, and the mode control module 12 is configured to control the scaling kernel module 13 to perform scaling processing on the input image data according to the parameter configured by the parameter definition module 11, the type of the input image data, and the state of the scaling kernel module 13, and output the processed image data.
In the present embodiment, the image scaling may also be applied to continuous image scaling, i.e., scaling of video. Wherein, scaling the image refers to scaling the resolution of the image. For example, the resolution of the input video data of the video input interface is Xin × Yin, and after the image scaling of the embodiment, the resolution of the output video data of the video output interface is Xout × Yout.
Optionally, in an embodiment, the parameters of the parameter definition module 11 block configuration include at least one of an image format, a data source, a data bit width, an input/output image resolution, and whether dynamic configuration is allowed.
For example, specific parameter items may include the following:
optionally, in an embodiment, the mode control module 12 is configured to determine a source of the resolution parameter value when the parameter dynamic configuration enable signal of the parameter definition module is acquired; wherein the resolution parameter value source comprises a resolution parameter of the input port and a static resolution parameter.
The mode control module is further configured to obtain a resolution parameter of the input port in response to an input I _ param _ update (parameter update instruction), so as to update the resolution parameter, so as to prevent a phenomenon of screen splash when the image is zoomed due to different resolution data.
Optionally, in an embodiment, the mode control module is further configured to control the O _ vin _ de _ req (source data request signal), the O _ vout _ de _ req (core data request signal), and the O _ vout _ de (data valid signal) signals to select different control modes for output in response to an input I _ up _ down _ sel (zoom in/out select instruction) signal when the Memory mode is in the Memory mode; or the mode control module is further used for regenerating a new O _ vout _ de _ req signal and an O _ vout _ de signal according to the output buffer empty state when in the Live mode, wherein the O _ vout _ de signal is a signal delayed by 2 beats.
Referring to fig. 2, fig. 2 is a schematic structural diagram of the scaling kernel module provided in the present application, and in an alternative embodiment, the scaling kernel module 13 includes a row calculation control state machine submodule 131, a vertical calculation submodule 132, a horizontal calculation submodule 133, and an output row cache submodule 134.
The vertical calculation sub-module 132 is configured to perform scaling processing in the vertical direction on the input image data; the horizontal calculation submodule 133 is configured to perform scaling processing in the horizontal direction on the input image data; the row calculation control state machine submodule 131 is used for controlling the state of row calculation and generating calculation enable and control signals to control the operation of the vertical calculation submodule 132 and the horizontal calculation submodule 133; the output row buffer sub-module 134 is configured to receive and output the image data output by the vertical calculation sub-module 132 or the horizontal calculation sub-module 133.
Specifically, as shown in fig. 3, fig. 3 is a schematic structural diagram of a vertical computation submodule provided in the present application, where the vertical computation submodule 132 includes a vertical coordinate conversion module 1321, a vertical line buffer module 1322, a vertical coefficient generation module 1323, and a vertical multiply-add module 1324.
The vertical coordinate conversion module 1321 is configured to accumulate the scaling factors in the vertical direction in response to the row calculation enable signal (generated by the row calculation control state machine sub-module), and calculate the mapping row address and the phase value of the input target image in the original image; the vertical line cache module 1322 is configured to cache input image data, and read image data to be calculated according to a mapping line address; the vertical coefficient generation module 1323 is configured to read coefficient data to be calculated according to the phase value; the vertical multiply-add module 1324 is configured to perform a multiply-add operation on the image data to be calculated and the coefficient data to be calculated.
Specifically, the method comprises the following steps:
1) when the I _ vin _ vs pulse signal comes, the I _ vin _ vs pulse signal indicates that one frame of image starts, and under the trigger of a line calculation enabling signal, the vertical coordinate conversion module accumulates the vertical direction scaling factor I _ ver _ skfactor to calculate the mapping line address and phase value of the target image in the original image. The row address is sent to the vertical row cache module to obtain the data to be calculated, and the phase value is sent to the vertical coefficient generation module to obtain the coefficient to be calculated.
2) The vertical line cache module caches input video data into a line buffer (memory), simultaneously records write-in line addresses, reads image data to be calculated according to mapping line addresses output by the vertical coordinate conversion module, and sends the data into the vertical multiplication and addition module for calculation. And meanwhile, buffer empty and full state information is generated according to the write address and the read address, and address counting enabling is controlled.
3) The vertical coefficient generation module caches the scaling coefficients pre-calculated by different interpolation algorithms through a Read Only Memory (ROM), and then reads coefficient data to be calculated according to the phase value output by the vertical coordinate conversion module, and the data is sent to the vertical multiplication and addition module for calculation.
4) And the vertical multiplication and addition module multiplies and adds the image data output by the vertical line cache module and the coefficient data output by the vertical coefficient generation module to complete vertical direction data calculation, and the calculated data is sent to the horizontal calculation submodule.
Specifically, as shown in fig. 4, fig. 4 is a schematic structural diagram of a horizontal calculation submodule provided in the present application, where the horizontal calculation submodule 133 includes a horizontal coordinate conversion module 1331, a horizontal line buffer module 1332, a horizontal coefficient generation module 1333, and a horizontal multiply-add module 1334.
The horizontal coordinate conversion module 1331 is configured to accumulate the scaling factors in the horizontal direction in response to the row calculation enable signal, and calculate a mapping pixel address and a phase value of the input target image in the original image; the horizontal line cache module 1332 is configured to cache input image data and read image data to be calculated according to a mapping pixel address; the horizontal coefficient generation module 1333 is used for reading the coefficient data to be calculated according to the phase value; the horizontal multiply-add module 1334 is configured to perform a multiply-add operation on the image data to be calculated and the coefficient data to be calculated.
Specifically, the method comprises the following steps:
1) and under the trigger of a row calculation enabling signal, accumulating the horizontal direction scaling factor I _ hor _ skfactor by the horizontal coordinate conversion module, and calculating the mapping pixel address and the phase value of the target image in the original image. The pixel address is sent to the horizontal pixel buffer module to obtain the data to be calculated, and the phase value is sent to the horizontal coefficient generation module to obtain the coefficient to be calculated.
2) The horizontal pixel buffer module buffers pixel data calculated and output by the vertical calculation sub-module through an FIFO (first in first out) (memory), reads image data to be calculated according to a mapping pixel address output by the horizontal coordinate conversion module, and the data is sent to the horizontal multiplication and addition module for calculation. And meanwhile, buffer empty and full state information is generated according to the write address and the read address, and address counting enabling is controlled.
3) The horizontal coefficient generation module caches scaling coefficients pre-calculated by different interpolation algorithms through a ROM, and reads coefficient data to be calculated according to a phase value output by the horizontal coordinate conversion module, and the data is sent to the horizontal multiplication and addition module for calculation.
4) The horizontal multiplication and addition module multiplies and adds the image data output by the horizontal line cache module and the coefficient data output by the horizontal coefficient generation module to complete horizontal direction data calculation, and the calculated data can be sent to the output line cache submodule.
With reference to fig. 5 and fig. 6, fig. 5 is another schematic structural diagram of the scaling kernel module provided in the present application, and fig. 6 is a schematic control flow diagram of a row computation control state machine submodule provided in the present application, where the control method includes:
1) after the power-on is finished or a frame begins to reset, the module firstly enters an idle state;
2) judging whether the row data of the vertical computing sub-module is ready to be finished, if so, entering a working state, and if not, maintaining the current state;
3) judging whether one line of calculation is finished, if so, keeping the current state, and otherwise, judging whether the one line of calculation is finished;
4) judging whether the waiting time is finished, if so, entering a finished state, and otherwise, maintaining the current state;
5) and judging whether the output buffer is not full and one frame is not finished, if so, entering an idle state to prepare for starting a new line of calculation, and if not, maintaining the current state.
With continued reference to fig. 6, the output line buffer sub-module 134 receives the data calculated and output by the level calculation sub-module 133, and buffers the data into the output line buffer in order to ensure that the data output by each line of the image is continuous. And generating buffer empty and full state information according to the write address and the read address, and controlling to output a data enable signal.
Different from the prior art, the image scaling circuit provided by the embodiment includes a parameter definition module, a mode control module and a scaling kernel module; the parameter definition module is used for carrying out parameter configuration on image zooming, and the mode control module is used for controlling the zooming kernel module to carry out zooming processing on an input image source and outputting the processed image data according to the parameters configured by the parameter definition module, the type of the input image data and the state of the zooming kernel. By the method, the image or the video is reduced and amplified, different types and effects of images can be zoomed differently by a parameter configurable mode, and the method has the characteristics of flexible configuration, convenient operation, program portability and the like.
Referring to fig. 7, fig. 7 is a schematic structural diagram of an embodiment of a display device 70 provided in the present application, which includes an input port 71, an image scaling controller 72, and a display screen 73.
The input port 71 is configured to receive external image data or video data, the image scaling controller 72 is connected to the input port 71, and is configured to scale the input image data or video data and send the processed image data or video data to the display screen 72, and the display screen 73 is configured to display the scaled image or video.
In the several embodiments provided in the present application, it should be understood that the disclosed method and apparatus may be implemented in other manners. For example, the above-described device embodiments are merely illustrative, and for example, the division of the modules or units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The above description is only for the purpose of illustrating embodiments of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made according to the content of the present specification and the accompanying drawings, or which are directly or indirectly applied to other related technical fields, are also included in the scope of the present application.
Claims (9)
1. An image scaling circuit is characterized by comprising a parameter definition module, a mode control module and a scaling kernel module;
the parameter definition module is used for carrying out parameter configuration on image zooming, the mode control module is used for determining a resolution parameter value source when a parameter dynamic configuration enabling signal of the parameter definition module is obtained, obtaining a corresponding resolution parameter according to the resolution parameter value source, controlling the zooming kernel module to carry out zooming processing on the input image data according to the obtained resolution parameter, the type of the input image data and the state of the zooming kernel module, and outputting the processed image data;
wherein the resolution parameter value source comprises a resolution parameter of the input port and a static resolution parameter.
2. The image scaling circuit of claim 1,
the parameters of the parameter definition module configuration comprise at least one of image format, data source, data bit width, input and output image resolution and whether dynamic configuration is allowed or not.
3. The image scaling circuit of claim 1,
the mode control module is further used for responding to an input parameter updating instruction, and acquiring the resolution parameter of the input port so as to update the resolution parameter.
4. The image scaling circuit of claim 1,
the mode control module is also used for responding to an input amplification/reduction selection instruction when in the Memory mode, and controlling an information source data request signal, an inner core data request signal and a data effective signal to select different control modes for output; or
The mode control module is further used for regenerating a new kernel data request signal and a new data effective signal according to the output cache empty state in the Live mode, wherein the data effective signal is a signal obtained after the kernel data request signal is delayed by 2 beats;
wherein the Memory mode represents reading image data input from storage, and the Live mode represents parallel image data input.
5. The image scaling circuit of claim 1,
the scaling kernel module comprises:
the vertical calculation submodule is used for carrying out scaling processing in the vertical direction on input image data;
the horizontal calculation submodule is used for carrying out scaling processing in the horizontal direction on input image data;
a row computation control state machine submodule for controlling the state of row computation and generating computation enable and control signals to control the operation of the vertical computation submodule and the horizontal computation submodule;
and the output row cache submodule is used for receiving and outputting the image data output by the vertical calculation submodule or the horizontal calculation submodule.
6. The image scaling circuit of claim 5,
the vertical computation submodule includes:
the vertical coordinate conversion module is used for responding to the row calculation enabling signal, accumulating the scaling factors in the vertical direction and calculating the mapping row address and the phase value of the input target image in the original image;
the vertical line cache module is used for caching the input image data and reading the image data to be calculated according to the mapping line address;
the vertical coefficient generating module is used for reading coefficient data to be calculated according to the phase value;
and the vertical multiplication and addition module is used for carrying out multiplication and addition operation on the image data to be calculated and the coefficient data to be calculated.
7. The image scaling circuit of claim 5,
the level calculation sub-module includes:
the horizontal coordinate conversion module is used for responding to the row calculation enabling signal, accumulating the scaling factors in the horizontal direction and calculating the mapping pixel address and the phase value of the input target image in the original image;
the horizontal line cache module is used for caching the input image data and reading the image data to be calculated according to the mapping pixel address;
the horizontal coefficient generating module is used for reading coefficient data to be calculated according to the phase value;
and the horizontal multiplication and addition module is used for carrying out multiplication and addition operation on the image data to be calculated and the coefficient data to be calculated.
8. An image scaling controller, characterized in that the image scaling controller comprises an input port, an output port and an image scaling circuit connecting the input port and the output port, wherein the image scaling circuit is an image scaling circuit according to any of claims 1-7.
9. A display device characterized in that it comprises an image scaling controller according to claim 8.
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| JP4014495B2 (en) * | 2002-11-29 | 2007-11-28 | 松下電器産業株式会社 | Video display device |
| CN1293514C (en) * | 2004-07-08 | 2007-01-03 | 北京中星微电子有限公司 | Pantograph treatment system of digital picture |
| JP2007067917A (en) * | 2005-08-31 | 2007-03-15 | Matsushita Electric Ind Co Ltd | Image data processing apparatus |
| JP4157568B2 (en) * | 2006-04-11 | 2008-10-01 | 株式会社東芝 | Method and apparatus for increasing image resolution |
| CN201075280Y (en) * | 2007-08-03 | 2008-06-18 | 深圳艾科创新微电子有限公司 | Display digital picture real time zoom integrated circuit |
| CN100576881C (en) * | 2007-12-26 | 2009-12-30 | 西安交通大学 | A kind of self-adapting video image zooming engine based on polyphase filter technology |
| CN102065253B (en) * | 2009-11-17 | 2013-02-20 | 无锡华润矽科微电子有限公司 | Software and hardware coordinated image horizontal zooming method and device |
| US8847968B2 (en) * | 2011-07-12 | 2014-09-30 | Qualcomm Incorporated | Displaying static images |
| US9245497B2 (en) * | 2012-11-01 | 2016-01-26 | Google Technology Holdings LLC | Systems and methods for configuring the display resolution of an electronic device based on distance and user presbyopia |
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