CN111128069A - Self-luminous display device and pixel internal and external compensation compatible circuit - Google Patents

Self-luminous display device and pixel internal and external compensation compatible circuit Download PDF

Info

Publication number
CN111128069A
CN111128069A CN201911164601.5A CN201911164601A CN111128069A CN 111128069 A CN111128069 A CN 111128069A CN 201911164601 A CN201911164601 A CN 201911164601A CN 111128069 A CN111128069 A CN 111128069A
Authority
CN
China
Prior art keywords
tft
driving
switch
light
time period
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201911164601.5A
Other languages
Chinese (zh)
Inventor
黄洪涛
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nanjing CEC Panda LCD Technology Co Ltd
Original Assignee
Nanjing CEC Panda LCD Technology Co Ltd
Nanjing CEC Panda FPD Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nanjing CEC Panda LCD Technology Co Ltd, Nanjing CEC Panda FPD Technology Co Ltd filed Critical Nanjing CEC Panda LCD Technology Co Ltd
Priority to CN201911164601.5A priority Critical patent/CN111128069A/en
Publication of CN111128069A publication Critical patent/CN111128069A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element

Abstract

The invention provides a pixel internal and external compensation compatible circuit, which is connected with a light-emitting element; the light-emitting element is positioned between a first power supply and a second power supply, and the compatible circuit is connected with a driving chip through a signal multiplexing line, and the driving chip is provided with a switch, a digital-to-analog converter and an analog-to-digital converter which can be connected with the switch; the compatible circuit further includes a first driving TFT between the first power supply and the light emitting element; a first switching TFT between the first driving TFT and the signal multiplexing line; a second switching TFT between the first driving TFT and the first power supply; a storage capacitor between the first driving TFT and the second power supply; a third switching TFT between the first driving TFT and the storage capacitor, and a fourth switching TFT between the first driving TFT and the light emitting unit. The invention has the capability of internal compensation and external compensation, and improves the flexibility and compensation range of pixel compensation.

Description

Self-luminous display device and pixel internal and external compensation compatible circuit
Technical Field
The invention relates to the technical field of display panels, in particular to a self-luminous display device and a pixel internal and external compensation compatible circuit.
Background
In recent years, display devices are increasingly developed toward thinning, lightening and flexibility, and self-luminous displays include organic electroluminescent OLEDs, quantum dot electroluminescent QLEDs, and Micro electroluminescent Micro-LEDs, which have natural advantages in these respects.
In a light-emitting element for a self-luminous display, the luminance of light emitted is in a positive correlation with both applied voltage and current. The relationship between the light emission luminance and the voltage changes under the influence of factors such as the ambient temperature and the operating time. Therefore, it is difficult to control the uniformity and stability of the luminance of the self-luminous display by using the voltage-driven light emitting element. In contrast, the brightness of a light-emitting device is substantially proportional to the applied current, and is not susceptible to interference from other factors. Therefore, the self-light emitting display generally adopts a current driving type design.
The current for driving the light emitting element is provided by the TFT backplane, including LTPS TFT and oxide semiconductor TFT. However, the characteristics of the TFT (including threshold voltage Vth and mobility) are likely to be deviated or shifted, which causes deviation or shift of the driving current and affects display uniformity and lifetime. Therefore, a compensation TFT characteristic deviation or drift circuit is usually provided in a pixel circuit for self-luminous display to improve display uniformity and lifetime.
The pixel compensation circuit is typically composed of a current control mode and a voltage control mode. The current control mode can simultaneously compensate the threshold voltage and the mobility of the TFT; the voltage control mode can generally only compensate for the threshold voltage of the TFT. However, the current control mode has the following two problems: (1) the control current is weak current, and the design requirement on a drive IC is high; (2) due to the influence of parasitic capacitance, the pixel compensation circuit in the current control mode needs a longer setting time to achieve the compensation effect. Therefore, the current pixel compensation circuit mostly adopts a voltage control mode.
Fig. 1 shows a conventional uncompensated pixel driving circuit, which includes a switching TFT1, a driving TFT2 and a storage capacitor 3, wherein the switching TFT1 is controlled by a Scan signal Scan to input a data signal Vdata to a gate-path terminal of the driving TFT2, and the driving TFT2 is controlled by a voltage of the gate-path terminal to output a driving current under the action of a power supply ELVDD, and the current flows through a light emitting element 5 to emit light. The storage capacitor 3 is connected to the gate path terminal of the driving TFT2 and the power source ELVDD, and is used to maintain the voltage at the gate path terminal of the driving TFT2 and prevent it from varying due to leakage in one refresh cycle.
The uncompensated pixel circuit does not compensate for the characteristics of the TFT, and the current flowing through the light emitting element may vary due to variations and drifts in the characteristics of the driving TFT, resulting in display uniformity and lifetime problems.
Fig. 2 shows a conventional voltage-controlled pixel compensation circuit, which includes 5 TFTs and 2 capacitors. The 110TFT is a driving TFT and supplies current to the light-emitting element, and the magnitude of the current is controlled by the grid voltage of the light-emitting element; 111TFT is a switching TFT for data voltage input, and is used for switching control of data voltage input; 112TFT is another switching TFT for switching control of input of a reference voltage; the 113TFT is another switch TFT for controlling the gate and drain of the driving TFT to be shorted so that the 110TFT forms a diode connection mode for extracting the threshold voltage Vth of the 110 TFT; the 114TFT is another switching TFT for switching light emission of the light emitting element while performing Vth extraction operation in cooperation with the 113 TFT.
The pixel compensation circuit can charge the gate of the 110TFT at t 0-t 1 through the cooperation of the 113TFT and the 114TFT, and extract the threshold voltage Vth of the 110TFT through the discharge of the 110TFT at t 1-t 2. At time t 3-t 4, the data voltage is input to point A and coupled to the gate of the 110TFT by capacitive coupling of 121. Thereby implementing the Vth compensation process of the 110 TFT.
However, the pixel compensation circuit needs 2 capacitors, wherein 121 capacitor is used for coupling the data voltage, and 122 capacitor is used for storing the pixel voltage to prevent the leakage. In order to achieve better coupling and voltage holding effects, the sizes of 2 capacitors need to be designed to be enough, and under the design of higher pixel density, the capacitors occupy larger layout space, so that the improvement of the pixel density is limited.
Disclosure of Invention
The invention aims to provide a pixel internal and external compensation compatible circuit which has internal compensation and external compensation capabilities and improves the flexibility and compensation range of pixel compensation.
The invention provides a pixel internal and external compensation compatible circuit, which is connected with a light-emitting element; the light-emitting element is positioned between the first power supply and the second power supply, the compatible circuit is connected with the driving chip through a signal multiplexing line, and the driving chip is provided with a switch, a digital-to-analog converter and an analog-to-digital converter which can be connected with the switch; the compatible circuit further includes a first driving TFT between the first power supply and the light emitting element; a first switching TFT between the first driving TFT and the signal multiplexing line; a second switching TFT between the first driving TFT and the first power supply; a storage capacitor between the first driving TFT and the second power supply; a third switching TFT between the first driving TFT and the storage capacitor and a fourth switching TFT between the first driving TFT and the light emitting unit;
when the driving chip is connected to the digital-to-analog converter through the switch, the driving chip provides data voltage or reference voltage through a signal multiplexing line to carry out internal compensation on the compatible circuit, and under the internal compensation mode, the compatible circuit adopts a diode connection mode to extract the threshold voltage of the first driving TFT and carries out compensation on the threshold voltage of the first driving TFT from the inside of the compatible circuit;
when the driving chip is switched among a plurality of states through the switch, the driving chip carries out external compensation on the compatible circuit through the signal multiplexing line, under an external compensation mode, the threshold voltage of the first driving TFT is detected from the outside of the compatible circuit, and the driving chip carries out compensation on the data voltage of the compatible circuit according to the detected threshold voltage.
Preferably, a path terminal of the first driving TFT is connected to the first pole of the storage capacitor and the first path terminal of the third switching TFT, a first path terminal of the first driving TFT is connected to a first path terminal of the fourth switching TFT and the first path terminal of the first switching TFT, and a second path terminal of the first driving TFT is connected to a second path terminal of the third switching TFT and the first path terminal of the second switching TFT; the channel end of the first switch TFT is connected with the scanning line, and the second channel end of the first switch TFT is connected with the signal multiplexing line; the path end of the second switch TFT is connected with a second light-emitting control signal, and the second path end of the second switch TFT is connected with a first power supply; the channel end of the third switch TFT is connected with a scanning control signal sent by a scanning line; a path end of the fourth switch TFT is connected with the first light-emitting control signal, and a second path end of the fourth switch TFT is connected with the anode of the light-emitting unit; the second pole of the storage capacitor is connected with a constant power supply, wherein the constant power supply is a first power supply or a second power supply or a reference voltage.
Preferably, a path terminal of the first driving TFT is connected to the first pole of the storage capacitor and the first path terminal of the third switching TFT, a first path terminal of the first driving TFT is connected to a first path terminal of the fourth switching TFT and the first path terminal of the first switching TFT, and a second path terminal of the first driving TFT is connected to a second path terminal of the third switching TFT and the first path terminal of the second switching TFT; the channel end of the first switch TFT is connected with a second scanning signal, and the second channel end of the first switch TFT is connected with a signal multiplexing line; the channel end of the second switch TFT is connected with a light-emitting control signal, and the second channel end of the second switch TFT is connected with a first power supply; the channel end of the third switch TFT is connected with the first scanning signal; the channel end of the fourth switch TFT is connected with the light-emitting control signal, and the second channel end of the fourth switch TFT is connected with the anode of the light-emitting unit; the second pole of the storage capacitor is connected with a constant power supply, wherein the constant voltage power supply is a first power supply.
Preferably, a path terminal of the first driving TFT is connected to the first pole of the storage capacitor and the first path terminal of the third switching TFT, a first path terminal of the first driving TFT is connected to a first path terminal of the fourth switching TFT and the first path terminal of the first switching TFT, and a second path terminal of the first driving TFT is connected to a second path terminal of the third switching TFT and the first path terminal of the second switching TFT; the channel end of the first switch TFT is connected with a second scanning signal, and the second channel end of the first switch TFT is connected with a signal multiplexing line; a path end of the second switch TFT is connected with the first light-emitting control signal, and a second path end of the second switch TFT is connected with the first power supply; the channel end of the third switch TFT is connected with the first scanning signal; a path end of the fourth switch TFT is connected with the second light-emitting control signal, and a second path end of the fourth switch TFT is connected with the anode of the light-emitting unit; the second pole of the storage capacitor is connected with a constant power supply, wherein the constant voltage power supply is a first power supply.
Preferably, there are consecutive first, second, third and fourth periods in the internal compensation mode; the first time period is a reset period, and a first power supply voltage is input to the access end of the first driving TFT after the first time period; the second time period is a threshold voltage extraction stage of the first driving TFT; the third time period is a stage that the voltage of the passage end of the first driving TFT is locked; the fourth time period is a light emitting period of the light emitting element.
Preferably, there are consecutive first, second, third and fourth periods in the internal compensation mode;
in a first time period, a scanning signal of a scanning line and a second light-emitting control signal are input with high level, a first light-emitting control signal is input with low level, a first switch TFT is turned on, a fourth switch TFT is turned off, and data voltage is input into a first pass end of a first drive TFT; meanwhile, the third switch TFT and the second switch TFT are also in an open state, and a first power supply voltage is input to the channel end of the first driving TFT;
inputting a high level by a scanning signal of a scanning line in a second time period, inputting a low level by a first light-emitting control signal and a second light-emitting control signal, closing a second switch TFT, at the moment, enabling a first driving TFT to be in an open state, connecting a pass end of the first driving TFT with a second pass end to form a diode connection mode, discharging voltage of the pass end of the first driving TFT to the first switch TFT through the first driving TFT until the voltage between a grid electrode and a drain electrode of the first driving TFT is reduced to a threshold voltage, closing the first driving TFT, stopping discharging, and successfully extracting the threshold voltage of the first driving TFT to the pass end of the first driving TFT and storing the threshold voltage by a storage capacitor;
inputting a high level by the first light-emitting control signal in a third time period, and inputting a low level by the scanning signal of the scanning line and the second light-emitting control signal, wherein at the moment, the third switch TFT is closed, the voltage of the passage end of the first driving TFT is locked, and the voltage difference between two ends of the storage capacitor is also locked;
in the fourth period, the first light-emitting control signal and the second light-emitting control signal are input with high level, the scanning signal of the scanning line is input with low level, at this time, the second switch TFT is turned on, a conductive path is formed between the first power supply and the second power supply, and current flows through the light-emitting element to emit light.
Preferably, there are consecutive first, second, third and fourth periods in the internal compensation mode;
the first scanning signal and the light-emitting control signal of the scanning line are input with high level, the second scanning signal of the scanning line is input with low level, at the moment, the first switch TFT is closed, the second switch TFT, the third switch TFT and the fourth switch TFT are opened, and the first power supply voltage is input to the pass end of the first drive TFT to charge the first drive TFT;
inputting a high level into a first scanning signal and a second scanning signal of a scanning line in a second time period, inputting a low level into a light-emitting control signal, closing a second switch TFT and a fourth switch TFT at the time, enabling a first driving TFT to be in an open state, connecting a pass end and a second pass end of the first driving TFT together to form a diode connection mode, discharging voltage of the pass end of the first driving TFT to the first switch TFT through the first driving TFT until the voltage between a grid electrode and a drain electrode of the first driving TFT is reduced to a threshold voltage, closing the first driving TFT, stopping discharging, and successfully extracting the threshold voltage of the first driving TFT to the pass end of the first driving TFT and storing the threshold voltage by a storage capacitor;
inputting a first scanning signal and a light-emitting control signal of a scanning line in a third time period into a low level, at the moment, closing a third switch TFT and a fourth switch TFT, locking the voltage of a channel end of a first driving TFT, and locking the voltage difference between two ends of a storage capacitor;
when the light emitting control signal is inputted with a high level in a fourth period, the first switching TFT and the third switching TFT are turned off, the second switching TFT is turned on, the voltage of the second path terminal of the first driving TFT is the voltage of the light emitting element, a conductive path is formed between the first power supply and the second power supply, and current flows through the light emitting element to emit light.
Preferably, there are consecutive first, second, third and fourth periods in the internal compensation mode;
in a first time period, a first scanning signal and a second light-emitting control signal of a scanning line input high level, a second scanning signal and a first light-emitting control signal of the scanning line input low level, a first switch TFT and a fourth switch TFT are closed, a second switch TFT and a third switch TFT are opened, and a first power supply voltage is input to a pass end of a first drive TFT to charge the first drive TFT;
inputting a high level into a first scanning signal and a second scanning signal of a scanning line in a second time period, inputting a low level into a first light-emitting control signal and a second light-emitting control signal, at the moment, closing a second switch TFT and a fourth switch TFT, enabling the third switch TFT, the first switch TFT and a first driving TFT to be in an open state, connecting a pass end and a second pass end of the first driving TFT together to form a connection mode of a diode, discharging the voltage of the pass end of the first driving TFT to the first switch TFT through the first driving TFT until the first driving TFT is closed when the voltage between a grid electrode and a drain electrode of the first driving TFT is reduced to a threshold voltage, stopping discharging, and successfully extracting the threshold voltage of the first driving TFT to the pass end of the first driving TFT and storing the threshold voltage by a storage capacitor;
inputting a high level into a second scanning signal and a first light-emitting control signal of the scanning line in a third time period, and inputting a low level into a first scanning signal and a second light-emitting control signal of the scanning line, wherein at the moment, the second switch TFT and the third switch TFT are closed, the voltage of the passage end of the first drive TFT is locked, and the voltage difference between two ends of the storage capacitor is also locked;
and in a fourth time period, the first light-emitting control signal and the second light-emitting control signal are input with high level, the first switch TFT and the third switch TFT are closed, the second switch TFT is opened, the voltage of the second channel end of the first drive TFT is the voltage of the light-emitting element, a conductive channel is formed between the first power supply and the second power supply, and current flows through the light-emitting element to emit light.
Preferably, there are a first time period, a second time period and a third time period in succession in the external compensation mode;
the data voltage is input into a low level in a first time period, a switch of the pixel internal and external compensation compatible circuit connects the signal multiplexing line to the digital-to-analog converter, and the driving chip provides a reference voltage to the signal multiplexing line;
disconnecting the signal multiplexing line from the digital-to-analog converter by a switch of the driving chip in a second time period, and charging the signal multiplexing line and gradually increasing the voltage of the signal multiplexing line by the driving chip;
the third time period is a detection stage of the threshold voltage, the switch of the driving chip connects the signal multiplexing line to the analog-to-digital converter, and the driving chip detects the voltage of the signal multiplexing line through the analog-to-digital converter;
in the first, second, and third periods, the scan signal and the second light emission control signal of the scan line are input at a high level, and the first light emission control signal is input at a low level.
Preferably, the first period of time is a reset phase; the second time period is a threshold voltage extraction stage; the third time period is a detection phase.
The pixel internal and external compensation compatible circuit can reduce the number of pixel driving circuit elements and improve PPI; the driving signals are simple, only one group of grid scanning signals and one group of light-emitting control signals are needed, and the Data lines or the sensing multiplexing lines are combined into one signal line; the invention has the capability of internal compensation and external compensation, and improves the flexibility and compensation range of pixel compensation.
Drawings
FIG. 1 shows a conventional uncompensated pixel driving circuit;
FIG. 2 shows a conventional voltage-controlled pixel compensation circuit;
FIG. 3 is a schematic diagram of a first embodiment of a pixel internal-external compensation compatible circuit according to the present invention;
FIG. 4 is a schematic diagram of the pixel internal and external compensation compatible circuit of the present invention under an internal compensation mode;
FIG. 5 is a waveform diagram of a driving signal in the internal compensation mode shown in FIG. 4;
FIG. 6 is a schematic diagram of the driving of FIG. 5 during a first time period;
FIG. 7 is a schematic diagram of the driving of FIG. 5 during a second time period;
FIG. 8 is a schematic diagram of the driving of FIG. 5 during a third time period;
FIG. 9 is a schematic diagram of the driving of FIG. 5 during a fourth period of time;
FIG. 10 is a schematic diagram of the pixel internal and external compensation compatible circuit in the external compensation mode according to the present invention;
FIG. 11 is a waveform diagram of driving signals in the external compensation mode shown in FIG. 10;
FIG. 12 is a diagram illustrating the waveform of FIG. 11 showing the detection of the threshold voltage Vth of the first driving TFT;
FIG. 13 is a schematic view of the driving of FIG. 11 during a first time period;
FIG. 14 is a schematic diagram of the driving of FIG. 11 during a second time period;
FIG. 15 is a schematic diagram of the driving of FIG. 11 during a third time period;
FIG. 16 is a diagram illustrating a second embodiment of a pixel internal/external compensation compatible circuit according to the present invention;
FIG. 17 is a waveform diagram of driving signals in the internal compensation mode shown in FIG. 16;
FIG. 18 is a schematic view of the driving of FIG. 16 during a first time period;
FIG. 19 is a schematic view of the driving of FIG. 16 during a second time period;
FIG. 20 is a schematic view of the driving of FIG. 16 during a third time period;
FIG. 21 is a schematic diagram of the driving of FIG. 16 during a fourth time period;
FIG. 22 is a diagram illustrating a third embodiment of a pixel internal/external compensation compatible circuit according to the present invention;
FIG. 23 is a waveform diagram of driving signals in the internal compensation mode shown in FIG. 22;
FIG. 24 is a schematic view of the driving of FIG. 22 during a first time period;
FIG. 25 is a schematic view of the driving of FIG. 22 during a second time period;
FIG. 26 is a schematic view of the driving of FIG. 22 during a third time period;
FIG. 27 is a schematic diagram illustrating the driving of FIG. 22 during a fourth period of time;
FIG. 28 is a diagram showing simulation results of the driving current variation of the pixel internal and external compensation compatible circuit shown in FIG. 4 under different data voltages Vdata in the internal compensation mode;
fig. 29 is a diagram showing a simulation result when the threshold voltage Vth of the in-compensation mode first driving TFT of the pixel in-out compensation compatible circuit shown in fig. 4 is changed.
Detailed Description
The present invention is further illustrated by the following figures and specific examples, which are to be understood as illustrative only and not as limiting the scope of the invention, which is to be given the full breadth of the appended claims and any and all equivalent modifications thereof which may occur to those skilled in the art upon reading the present specification.
For the sake of simplicity, the drawings only schematically show the parts relevant to the present invention, and they do not represent the actual structure as a product. In addition, in order to make the drawings concise and understandable, components having the same structure or function in some of the drawings are only schematically illustrated or only labeled. In this document, "one" means not only "only one" but also a case of "more than one".
Fig. 3 is a schematic structural diagram of a pixel internal and external compensation compatible circuit according to the present invention, which can perform both pixel internal compensation and pixel external compensation, in which a Data line Data and a sensing multiplexing line Sense are combined into a signal multiplexing line 50, the signal multiplexing line 50 is connected to a driver IC40, the driver IC40 is provided with a switch 41, and a digital-to-analog converter DAC42 and an analog-to-digital converter ADC 43 that can be connected to the switch 41, and when the switch 41 is connected to the digital-to-analog converter DAC42, a first switch TFT 12 is connected to the digital-to-analog converter DAC 42; when the switch 41 is connected to the analog-to-digital converter ADC 43, the first switch TFT 12 is connected to the analog-to-digital converter ADC 43.
The pixel internal and external compensation compatible circuit is used for compensating the self-luminous display device, and is connected with the luminous element 30, wherein the luminous element 30 is positioned between a first power supply ELVDD and a second power supply ELVSS, and the luminous element 30 is controlled by a first luminous control signal EM1 and a second luminous control signal EM 2.
The first power ELVDD is a positive power terminal, and the second power ELVSS is a negative power terminal.
The pixel internal and external compensation compatible circuit comprises: a first driving TFT11 between the first power source and the light emitting element 30, the first driving TFT11 being connected in series between the first power source and the light emitting element 30; a first switching TFT 12 between the first driving TFT11 and the driving chip IC 40; a second switching TFT13 located between the first driving TFT11 and the first power supply; a storage capacitor 20 between the first driving TFT11 and the second power supply; a third switching TFT14 between the first driving TFT11 and the storage capacitor 20, and a fourth switching TFT15 between the first driving TFT11 and the light emitting unit 30.
It should be noted that each of the TFTs according to the following embodiments includes a control terminal, a first via terminal and a second via terminal, the control terminal is a gate, one of the via terminals is a source, and the other via terminal is a drain. When the voltages received by the control terminal, the first path terminal and the second path terminal meet the opening condition of the TFT, the source electrode and the drain electrode are connected through the semiconductor layer, and the TFT is in an opening state at the moment, otherwise, the TFT is in a closing state.
The control end of the first driving TFT11 is used as a point G, and the control end of the first driving TFT11 is connected to the first pole of the storage capacitor 20 and the first path end of the third switching TFT 14; a first path end of the first driving TFT11 is used as a point B, and the first path end of the first driving TFT11 is connected with a first path end of the fourth switching TFT15 and a first path end of the first switching TFT 12; the second path terminal of the first driving TFT11 is set as a point a, and the second path terminal of the first driving TFT11 is connected to the second path terminal of the third switching TFT14 and the first path terminal of the second switching TFT 13.
The control end of the first switch TFT 12 is connected with the scanning line, the second path end of the first switch TFT 12 is connected with the signal multiplexing line 50, and then is connected with the switch 41 of the driving chip IC40 through the signal multiplexing line 50; a control terminal of the second switching TFT13 is connected to the second emission control signal EM2, and a second path terminal of the second switching TFT13 is connected to the first power source ELVDD; the control end of the third switch TFT14 is connected with a scanning control signal sent by a scanning line; a control end of the fourth switch TFT15 is connected to the first emission control signal EM1, and a second path end of the fourth switch TFT15 is connected to the anode of the light emitting unit 30; the second pole of the storage capacitor 20 is connected to a constant power source, which is the first power ELVDD or the second power ELVSS or the reference voltage Vref.
When the driving chip IC40 is connected to the DAC42 through the switch 41, the driving chip IC40 provides the data voltage Vdata or the reference voltage Vref to the compatible circuit through the signal multiplexing line 50 for internal compensation, in the internal compensation mode, the pixel internal and external compensation compatible circuit adopts a diode connection mode to extract the threshold voltage Vth of the first driving TFT11 and compensate the driving voltage of the first driving TFT11 from the inside of the pixel internal and external compensation compatible circuit, and by extracting and compensating the threshold voltage Vth of the first driving TFT11, the current in the light emitting phase T4 is not affected by the threshold voltage Vth of the first driving TFT11, and the compensation effect of the threshold voltage Vth is achieved.
When the driving chip IC40 is switched among a plurality of states through the switch 41, the driving chip IC40 externally compensates the compatible circuit through the signal multiplexing line 50, in the external compensation mode, the threshold voltage Vth of the first driving TFT11 is detected from the outside of the pixel internal and external compensation compatible circuit, and the driving chip IC40 compensates the data voltage Vdata of the pixel internal and external compensation compatible circuit according to the detected threshold voltage Vth, so that the influence of the unevenness and drift of the threshold voltage Vth on the quality and the service life of the display picture is avoided in an external compensation mode.
Fig. 4 is a schematic diagram of the pixel internal and external compensation compatible circuit in the internal compensation mode, and fig. 5 is a waveform diagram of the driving signal in the internal compensation mode shown in fig. 4. The internal compensation mode has a first time period (specifically, during T1), a second time period (specifically, during T2), a third time period (specifically, during T3), and a fourth time period (specifically, during T4) that are consecutive, the first time period (specifically, during T1), the second time period (specifically, during T2), and the third time period (specifically, during T3) are the same in time, and the fourth time period (specifically, during T4) is the duration of the light emitting time of the light emitting unit 30.
Wherein the Scan signal Scan and the second emission control signal EM2 of the Scan line are inputted with a high level, and the first emission control signal EM1 is inputted with a low level during a first period (specifically, during T1); the Scan signal Scan of the Scan line is input with a high level, and the first and second emission control signals EM1 and EM2 are input with a low level during a second period (specifically, during T2); the first emission control signal EM1 inputs a high level, and the Scan signal Scan of the Scan line and the second emission control signal EM2 input a low level during a third period (specifically, during T3); during a fourth period (specifically, during T4), the first emission control signal EM1 and the second emission control signal EM2 are input with a high level, and the Scan signal Scan of the Scan line is input with a low level;
in the internal compensation mode, the switch 41 of the driver chip IC40 connects the signal multiplexing line 50 to the digital-to-analog converter DAC42, and the driver chip IC40 supplies the data voltage Vdata.
Specifically, the first power voltage ELVDD is input to the control terminal G of the first driving TFT11 during a first period (specifically, during T1) which is a reset period (specifically, during T1). As shown in fig. 6, the Scan signal Scan of the Scan line is inputted with a high level, the first emission control signal EM1 is inputted with a low level, at this time, the first switching TFT 12 is turned on, the fourth switching TFT15 is turned off, and the data voltage Vdata is inputted to the point B; meanwhile, the third switching TFT14 and the second switching TFT13 are also in an on state, and the control terminal G of the first driving TFT11 is inputted with the first power voltage ELVDD.
The second period (specifically, during T2) is the threshold voltage Vth extraction phase of the first driving TFT 11. As shown in fig. 7, the second emission control signal EM2 is input with a low level, the second switching TFT13 is turned off, the first driving TFT11 is turned on, the control terminal G of the first driving TFT11 and the second path terminal a are connected together to form a diode connection, the voltage at the control terminal G of the first driving TFT11 is discharged to the first switching TFT 12 through the first driving TFT11, and the first driving TFT11 is turned off until the voltage Vgs between the gate and the drain of the first driving TFT11 is reduced to the threshold voltage Vth, and the discharge is stopped, where the voltage at the point G is (Vdata + Vth). At this point, the threshold voltage Vth of the first driving TFT11 is successfully extracted to the point G and held by the storage capacitor 20.
The third period (specifically, during T3) is the phase in which the voltage Vg at the control terminal G of the first driving TFT11 is locked. As shown in fig. 8, when the Scan signal Scan of the Scan line is inputted with a low level and the first emission control signal EM1 is inputted with a high level, the third switching TFT14 is turned off, the G-point voltage Vg is latched, and the voltage difference across the storage capacitor 20 is also latched.
The fourth period of time (specifically, during T4) is a light emitting period of the light emitting element 30. As shown in fig. 9, the second emission control signal EM2 is inputted with a high level, the second switching TFT13 is turned on, a conductive path is formed between the first power source and the second power source, and a current flows through the light emitting element 30 to emit light.
In the light emitting stage, the current flowing through the light emitting element 30 is controlled by the first driving TFT 11. Since the voltage at the second path terminal of the first driving TFT11 is ELVDD, the first driving TFT11 operates in a saturation region with an operating current of 1/2K (Vgs-Vth)2, that is, 1/2K (Vdata + Vth-ELVSS-Voled-Vth)2 ═ 1/2K (Vdata-ELVSS-Voled) 2. By this current formula, it can be found that the driving current flowing through the light emitting element 30 is related only to the data voltage Vdata, the first power supply voltage ELVSS, and the operating voltage Voled of the light emitting element 30, and is not related to the threshold voltage Vth of the TFT. Since the threshold voltage Vth of the first driving TFT11 is extracted in the second period of time (specifically, during T2), the current of the lighting period T4 is not affected by the threshold voltage Vth of the first driving TFT11, and the compensation effect of the threshold voltage Vth is achieved.
After the threshold voltage Vth compensation, the luminous brightness is not affected by the deviation of the threshold voltage Vth caused by the uniformity of the process, so that the luminous brightness of the display area is more uniform, and better image quality performance is realized. Meanwhile, since the threshold voltage Vth is compensated, even if the threshold voltage Vth of the first driving TFT11 drifts after a long time T4 operation, the luminance is not significantly affected, and the operating life and reliability of the self-luminous display device are improved.
Fig. 10 is a schematic diagram of the pixel internal and external compensation compatible circuit in the external compensation mode according to the present invention, and fig. 11 is a waveform diagram of the driving signal in the external compensation mode shown in fig. 10.
In the external compensation mode, as shown in fig. 12, the driving waveform and the circuit operation for detecting the threshold voltage Vth of the first driving TFT11 are performed.
In the external compensation mode, the switch 41 of the driver IC40 connected to the signal multiplexing line 50 will switch between a plurality of states, either to the DAC42 or to the ADC 43.
The external compensation mode has a first time period (specifically, during T1), a second time period (specifically, during T2) and a third time period (specifically, during T3) which are continuous, the first time period (specifically, during T1) and the third time period (specifically, during T3) are the same in time, and the second time period (specifically, during T2) is greater than the first time period (specifically, during T1) and the third time period (specifically, during T3).
Wherein, the signal multiplexing line 50 inputs the reference voltage Vref for resetting in a first time period (specifically, during T1); from the second period (specifically, during T2) to the third period (specifically, during T2), the signal multiplexing circuit 50 is slowly input to a high level by the pixel compensation circuit.
In the first period (specifically, during T1), the second period (specifically, during T2), and the third period (specifically, during T3), the Scan signal Scan and the second emission control signal EM2 of the Scan line are input with a high level, and the first emission control signal EM1 is input with a low level.
That is, during the Vth detection period, the first emission control signal EM1 is in an off state, and the second emission control signal EM1 and the Scan control signal Scan are in an on state. This real fourth switching TFT15 is turned off and the other TFTs are turned on.
The first time period (specifically during T1) is the reset period, as shown in fig. 13, the switch 41 of the driver IC40 connects the signal multiplexing line 50 to the DAC42, the driver IC40 provides the reference voltage Vref to the signal multiplexing line 50, and the voltages of the signal multiplexing line 50 and the point B are both the reference voltage Vref.
The second time period (specifically, during T2) is the threshold voltage Vth extraction phase, as shown in fig. 14, the switch 41 of the driver chip IC40 disconnects the signal multiplexing line 50 from the digital-to-analog converter DAC42, and the pixel compensation circuit charges the point B and the signal multiplexing line 50 and gradually increases the voltage thereof; when the voltage Vgs between the gate and the drain of the first driving TFT11 is equal to the threshold voltage Vth, the first driving TFT11 will be turned off, the node B and the signal multiplexing line 50 are no longer charged, and the second switching TFT13 and the third switching TFT14 are both in an on state, so VG is equal to ELVDD, and then Vgs is VG-VB is equal to ELVDD-VB and Vth, and thus VB is known as ELVDD-Vth. At the end of the second period (specifically, during T2), the voltages of the point B and the signal multiplexing line 50 both rise to the (ELVDD-Vth) voltage.
The third time period (specifically, during T3) is the Vth detection phase, as shown in fig. 15, the switch 41 of the driver IC40 connects the signal multiplexing line 50 to the analog-to-digital converter ADC 43, the driver IC40 detects the voltage (ELVDD-Vth) of the signal multiplexing line 50 through the analog-to-digital converter ADC 43, and the threshold voltage Vth of the first driving TFT11 is detected because ELVDD is the voltage of the first power supply and is a known constant voltage.
After the threshold voltage Vth is detected, the driving chip IC40 compensates the data voltage Vdata of each pixel according to the detected Vth result during normal display driving, so as to avoid the influence of the non-uniform threshold voltage Vth and the drift on the display quality and the lifetime in an external compensation manner.
Fig. 16 shows a second embodiment of the present invention, which is different from the first embodiment: only one light emission control signal EM is set, the light emitting element 30 is controlled by the light emission control signal EM, and the control end of the second switching TFT13 and the control end of the fourth switching TFT15 are both connected to the light emission control signal EM; the Scan signal of the Scan line has a first Scan signal Scan1 and a second Scan signal San2, the control terminal of the third switching TFT14 is connected to the first Scan signal Scan1, and the first switching TFT 12 is connected to the second Scan signal Scan 2; a second path terminal of the fourth switching TFT15 is connected to the anode of the light emitting unit 30; the second pole of the storage capacitor 20 is connected to a constant power source, which is the first power source ELVDD.
Fig. 17 is a waveform diagram of driving signals in the internal compensation mode shown in fig. 16. In the internal compensation mode, the switch 41 of the driver chip IC40 connects the signal multiplexing line 50 to the digital-to-analog converter DAC42, and the driver chip IC40 supplies the data voltage Vdata.
The internal compensation mode has a first time period (specifically, during T1), a second time period (specifically, during T2), a third time period (specifically, during T3), and a fourth time period (specifically, during T4) that are consecutive, the first time period (specifically, during T1), the second time period (specifically, during T2), and the third time period (specifically, during T3) are the same in time, and the fourth time period (specifically, during T4) is the duration of the light emitting time of the light emitting unit 30.
Wherein the first Scan signal Scan1 and the emission control signal EM of the Scan line are inputted with a high level and the second Scan signal Scan2 of the Scan line is inputted with a low level in a first period (specifically, during T1); the first Scan signal Scan1 and the second Scan signal Scan2 of the Scan line are inputted with a high level and the emission control signal EM is inputted with a low level in a second period (specifically, during T2); in a third period (specifically, during T3), the second Scan signal Scan2 of the Scan line is input with a high level, and the first Scan signal Scan1 of the Scan line and the emission control signal EM are input with a low level; in the fourth period (specifically, during T4), the emission control signal EM is input with a high level, and the first Scan signal Scan1 and the second Scan signal Scan2 of the Scan line are input with a low level.
Specifically, the first power voltage ELVDD is input to the control terminal G of the first driving TFT11 during a first period (specifically, during T1) which is a reset period (specifically, during T1). As shown in fig. 18, the first Scan signal Scan1 and the emission control signal EM of the Scan line are inputted with a high level, the second Scan signal Scan2 of the Scan line is inputted with a low level, at this time, the first switching TFT 12 is turned off, the third switching TFT14 and the fourth switching TFT15 are turned on, and the first power voltage ELVDD is inputted to the G point (i.e., the control terminal of the first driving TFT 11), thereby realizing charging of the first driving TFT 11.
The second period (specifically, during T2) is the threshold voltage Vth extraction phase of the first driving TFT 11. As shown in fig. 19, the first Scan signal Scan1 and the second Scan signal Scan2 of the Scan line are inputted with a high level, the emission control signal EM is inputted with a low level, at this time, the second switch TFT13 and the fourth switch TFT15 are turned off, the first driving TFT11 is in an on state, the control terminal G of the first driving TFT11 and the second via terminal a are connected together to form a diode connection, the voltage at the control terminal G of the first driving TFT11 is discharged to the first switch TFT 12 through the first driving TFT11 until the first driving TFT11 is turned off when the voltage Vgs between the gate and the drain of the first driving TFT11 is reduced to the threshold voltage Vth, and the discharge is stopped, at this time, the voltage at the G is (Vdata + Vth). At this point, the threshold voltage Vth of the first driving TFT11 is successfully extracted to the point G and held by the storage capacitor 20.
The third period (specifically, during T3) is the phase in which the voltage Vg at the control terminal G of the first driving TFT11 is locked. As shown in fig. 20, the first Scan signal Scan1 and the emission control signal EM of the Scan line are inputted with low levels, at which time the third switching TFT14 and the fourth switching TFT15 are turned off, the G-point voltage Vg is latched and is (Vdata + Vth), and the voltage difference across the storage capacitor 20 is also latched at the same time.
The fourth period of time (specifically, during T4) is a light emitting period of the light emitting element 30. As shown in fig. 21, the light emission control signal EM inputs a high level, the first and third switching TFTs 12 and 14 are turned off, the second switching TFT13 is turned on, the voltage Vg at the control terminal G of the first driving TFT11 is Vdata + Vth, the voltage Vb at the second path terminal B of the first driving TFT11 is the voltage Voled + ELVSS of the light emitting element 30, and the voltage Vgs between the gate and drain of the first driving TFT11 is Vdata + Vth-Voled-ELVSS; a conductive path is formed between the first power source and the second power source, and a current flows through the light emitting element 30 to emit light.
Fig. 22 shows a third embodiment of the present invention, which is different from the first embodiment: the Scan signal of the Scan line has a first Scan signal Scan1 and a second Scan signal San2, the control terminal of the third switching TFT14 is connected to the first Scan signal Scan1, and the first switching TFT 12 is connected to the second Scan signal Scan 2.
Fig. 23 is a waveform diagram of driving signals in the internal compensation mode shown in fig. 22. In the internal compensation mode, the switch 41 of the driver chip IC40 connects the signal multiplexing line 50 to the digital-to-analog converter DAC42, and the driver chip IC40 supplies the data voltage Vdata.
The internal compensation mode has a first time period (specifically, during T1), a second time period (specifically, during T2), a third time period (specifically, during T3), and a fourth time period (specifically, during T4) that are consecutive, the first time period (specifically, during T1), the second time period (specifically, during T2), and the third time period (specifically, during T3) are the same in time, and the fourth time period (specifically, during T4) is the duration of the light emitting time of the light emitting unit 30.
Wherein the first Scan signal Scan1 and the second emission control signal EM2 of the Scan line input a high level, and the second Scan signal Scan2 and the first emission control signal EM1 of the Scan line input a low level during a first period (specifically, during T1); the first and second Scan signals Scan1 and Scan2 of the Scan line input a high level, and the first and second emission control signals EM1 and EM2 input a low level during a second period (specifically, during T2); the first Scan signal Scan1 and the second emission control signal EM2 of the Scan line input a low level, and the second Scan signal Scan2 and the first emission control signal EM1 of the Scan line input a high level during a third period (specifically, during T3); in the fourth period (specifically, during T4), the first and second emission control signals EM1 and EM2 are inputted with a high level, and the first and second Scan signals Scan1 and Scan signals Scan2 of the Scan line are inputted with a low level.
Specifically, the first power voltage ELVDD is input to the control terminal G of the first driving TFT11 during a first period (specifically, during T1) which is a reset period (specifically, during T1). As shown in fig. 24, the first Scan signal Scan1 and the second emission control signal EM2 of the Scan line are inputted with a high level, and the second Scan signal Scan2 of the Scan line is inputted with a low level, at which time, the first switching TFT 12 and the fourth switching TFT15 are turned off, the second switching TFT13 and the third switching TFT14 are turned on, and the first power voltage ELVDD is inputted to the G point (i.e., the control terminal of the first driving TFT 11), thereby realizing charging of the first driving TFT 11.
The second period (specifically, during T2) is the threshold voltage Vth extraction phase of the first driving TFT 11. As shown in fig. 25, the first Scan signal Scan1 and the second Scan signal Scan2 of the Scan line are inputted with a high level, the first emission control signal EM1 and the second emission control signal EM2 are inputted with a low level, at this time, the second switching TFT13 and the fourth switching TFT15 are turned off, the third switching TFT14, the first switching TFT 12 and the first driving TFT11 are in an on state, the control terminal G point and the second terminal a point of the first driving TFT11 are connected together to form a diode connection, the voltage at the control terminal G point of the first driving TFT11 is discharged to the first switching TFT 12 through the first driving TFT11 until the first driving TFT11 is turned off when the voltage Vgs between the gate and the drain of the first driving TFT11 is lowered to the threshold voltage Vth, and the discharge is stopped, at this time, the voltage at the point B is Vdata, and the voltage at the point G is (Vdata + Vdata). At this point, the threshold voltage Vth of the first driving TFT11 is successfully extracted to the point G and held by the storage capacitor 20.
The third period (specifically, during T3) is the phase in which the voltage Vg at the control terminal G of the first driving TFT11 is locked. As shown in fig. 26, the second Scan signal Scan2 and the first emission control signal EM1 of the Scan line are inputted with a high level, the first Scan signal Scan1 and the second emission control signal EM2 of the Scan line are inputted with a low level, at this time, the second switching TFT13 and the third switching TFT14 are turned off, the G-point voltage Vg is latched and is (Vdata + Vth), and the voltage difference across the storage capacitor 20 is also latched at the same time.
The fourth period of time (specifically, during T4) is a light emitting period of the light emitting element 30. As shown in fig. 27, the first and second emission control signals EM1 and EM2 are inputted with a high level, the first and third switching TFTs 12 and 14 are turned off, the second switching TFT13 is turned on, the voltage Vg at the control terminal G of the first driving TFT11 is Vdata + Vth, the voltage Vb at the second path terminal B of the first driving TFT11 is the voltage Voled + ELVSS of the light emitting element 30, and the voltage Vgs between the gate and drain of the first driving TFT11 is Vdata + Vth-Voled-ELVSS; a conductive path is formed between the first power source and the second power source, and a current flows through the light emitting element 30 to emit light.
The external compensation patterns of the second, third and fourth embodiments are the same as those of the first embodiment, and the description thereof will not be repeated.
Fig. 28 and fig. 29 are circuit simulation results in the internal compensation mode based on the first embodiment. After the pixel internal and external compensation compatible circuit is adopted, fig. 28 shows that the driving current of the pixel circuit can be normally controlled by the data voltage Vdata as the simulation result of the driving current change under different data voltages Vdata. Fig. 29 shows the variation of the drive current at different threshold voltages Vth when the threshold voltage Vth of the first drive TFT11 is varied, and it can be seen that the drive current at each gray level maintains relatively good stability without significant current decay over a wide range of the variation of the threshold voltage Vth. Only when a higher gray scale and a larger threshold voltage Vth shift occur simultaneously, a significant drop in drive current occurs.
The pixel internal and external compensation compatible circuit can reduce the number of pixel driving circuit elements and improve PPI; the driving signals are simple, only one group of grid scanning signals and one group of light-emitting control signals are needed, and the Data lines or the sensing multiplexing lines are combined into one signal line; the invention has the capability of internal compensation and external compensation, and improves the flexibility and compensation range of pixel compensation.
Although the preferred embodiments of the present invention have been described in detail, the present invention is not limited to the details of the foregoing embodiments, and various equivalent changes (such as number, shape, position, etc.) may be made to the technical solution of the present invention within the technical spirit of the present invention, and these equivalent changes are all within the protection scope of the present invention.

Claims (10)

1. A pixel internal and external compensation compatible circuit is connected with a light emitting element; the light-emitting element is positioned between a first power supply and a second power supply, and the compatible circuit is connected with a driving chip through a signal multiplexing line, and the driving chip is provided with a switch, a digital-to-analog converter and an analog-to-digital converter which can be connected with the switch; the compatible circuit further includes a first driving TFT between the first power supply and the light emitting element; a first switching TFT between the first driving TFT and the signal multiplexing line; a second switching TFT between the first driving TFT and the first power supply; a storage capacitor between the first driving TFT and the second power supply; a third switching TFT between the first driving TFT and the storage capacitor and a fourth switching TFT between the first driving TFT and the light emitting unit;
when the driving chip is connected to the digital-to-analog converter through the switch, the driving chip provides data voltage or reference voltage through a signal multiplexing line to carry out internal compensation on the compatible circuit, and under the internal compensation mode, the compatible circuit adopts a diode connection mode to extract the threshold voltage of the first driving TFT and carries out compensation on the threshold voltage of the first driving TFT from the inside of the compatible circuit;
when the driving chip is switched among a plurality of states through the switch, the driving chip carries out external compensation on the compatible circuit through the signal multiplexing line, under an external compensation mode, the threshold voltage of the first driving TFT is detected from the outside of the compatible circuit, and the driving chip carries out compensation on the data voltage of the compatible circuit according to the detected threshold voltage.
2. The in-pixel compensation compatible circuit according to claim 1, wherein: the channel end of the first driving TFT is connected with the first pole of the storage capacitor and the first channel end of the third switching TFT, the first channel end of the first driving TFT is connected with the first channel end of the fourth switching TFT and the first channel end of the first switching TFT, and the second channel end of the first driving TFT is connected with the second channel end of the third switching TFT and the first channel end of the second switching TFT; the channel end of the first switch TFT is connected with the scanning line, and the second channel end of the first switch TFT is connected with the signal multiplexing line; the path end of the second switch TFT is connected with a second light-emitting control signal, and the second path end of the second switch TFT is connected with a first power supply; the channel end of the third switch TFT is connected with a scanning control signal sent by a scanning line; a path end of the fourth switch TFT is connected with the first light-emitting control signal, and a second path end of the fourth switch TFT is connected with the anode of the light-emitting unit; the second pole of the storage capacitor is connected with a constant power supply, wherein the constant power supply is a first power supply or a second power supply or a reference voltage.
3. The in-pixel compensation compatible circuit according to claim 1, wherein: the channel end of the first driving TFT is connected with the first pole of the storage capacitor and the first channel end of the third switching TFT, the first channel end of the first driving TFT is connected with the first channel end of the fourth switching TFT and the first channel end of the first switching TFT, and the second channel end of the first driving TFT is connected with the second channel end of the third switching TFT and the first channel end of the second switching TFT; the channel end of the first switch TFT is connected with a second scanning signal, and the second channel end of the first switch TFT is connected with a signal multiplexing line; the channel end of the second switch TFT is connected with a light-emitting control signal, and the second channel end of the second switch TFT is connected with a first power supply; the channel end of the third switch TFT is connected with the first scanning signal; the channel end of the fourth switch TFT is connected with the light-emitting control signal, and the second channel end of the fourth switch TFT is connected with the anode of the light-emitting unit; the second pole of the storage capacitor is connected with a constant power supply, wherein the constant voltage power supply is a first power supply.
4. The in-pixel compensation compatible circuit according to claim 1, wherein: the channel end of the first driving TFT is connected with the first pole of the storage capacitor and the first channel end of the third switching TFT, the first channel end of the first driving TFT is connected with the first channel end of the fourth switching TFT and the first channel end of the first switching TFT, and the second channel end of the first driving TFT is connected with the second channel end of the third switching TFT and the first channel end of the second switching TFT; the channel end of the first switch TFT is connected with a second scanning signal, and the second channel end of the first switch TFT is connected with a signal multiplexing line; a path end of the second switch TFT is connected with the first light-emitting control signal, and a second path end of the second switch TFT is connected with the first power supply; the channel end of the third switch TFT is connected with the first scanning signal; a path end of the fourth switch TFT is connected with the second light-emitting control signal, and a second path end of the fourth switch TFT is connected with the anode of the light-emitting unit; the second pole of the storage capacitor is connected with a constant power supply, wherein the constant voltage power supply is a first power supply.
5. The in-pixel and out-pixel compensation compatible circuit according to claim 2, 3 or 4, wherein: the method comprises the steps of having a first time period, a second time period, a third time period and a fourth time period which are continuous in an internal compensation mode; the first time period is a reset period, and a first power supply voltage is input to the access end of the first driving TFT after the first time period; the second time period is a threshold voltage extraction stage of the first driving TFT; the third time period is a stage that the voltage of the passage end of the first driving TFT is locked; the fourth time period is a light emitting period of the light emitting element.
6. The in-pixel compensation compatible circuit according to claim 2, wherein: the method comprises the steps of having a first time period, a second time period, a third time period and a fourth time period which are continuous in an internal compensation mode;
in a first time period, a scanning signal of a scanning line and a second light-emitting control signal are input with high level, a first light-emitting control signal is input with low level, a first switch TFT is turned on, a fourth switch TFT is turned off, and data voltage is input into a first pass end of a first drive TFT; meanwhile, the third switch TFT and the second switch TFT are also in an open state, and a first power supply voltage is input to the channel end of the first driving TFT;
inputting a high level by a scanning signal of a scanning line in a second time period, inputting a low level by a first light-emitting control signal and a second light-emitting control signal, closing a second switch TFT, at the moment, enabling a first driving TFT to be in an open state, connecting a pass end of the first driving TFT with a second pass end to form a diode connection mode, discharging voltage of the pass end of the first driving TFT to the first switch TFT through the first driving TFT until the voltage between a grid electrode and a drain electrode of the first driving TFT is reduced to a threshold voltage, closing the first driving TFT, stopping discharging, and successfully extracting the threshold voltage of the first driving TFT to the pass end of the first driving TFT and storing the threshold voltage by a storage capacitor;
inputting a high level by the first light-emitting control signal in a third time period, and inputting a low level by the scanning signal of the scanning line and the second light-emitting control signal, wherein at the moment, the third switch TFT is closed, the voltage of the passage end of the first driving TFT is locked, and the voltage difference between two ends of the storage capacitor is also locked;
in the fourth period, the first light-emitting control signal and the second light-emitting control signal are input with high level, the scanning signal of the scanning line is input with low level, at this time, the second switch TFT is turned on, a conductive path is formed between the first power supply and the second power supply, and current flows through the light-emitting element to emit light.
7. The in-pixel compensation compatible circuit according to claim 3, wherein: the method comprises the steps of having a first time period, a second time period, a third time period and a fourth time period which are continuous in an internal compensation mode;
the first scanning signal and the light-emitting control signal of the scanning line are input with high level, the second scanning signal of the scanning line is input with low level, at the moment, the first switch TFT is closed, the second switch TFT, the third switch TFT and the fourth switch TFT are opened, and the first power supply voltage is input to the pass end of the first drive TFT to charge the first drive TFT;
inputting a high level into a first scanning signal and a second scanning signal of a scanning line in a second time period, inputting a low level into a light-emitting control signal, closing a second switch TFT and a fourth switch TFT at the time, enabling a first driving TFT to be in an open state, connecting a pass end and a second pass end of the first driving TFT together to form a diode connection mode, discharging voltage of the pass end of the first driving TFT to the first switch TFT through the first driving TFT until the voltage between a grid electrode and a drain electrode of the first driving TFT is reduced to a threshold voltage, closing the first driving TFT, stopping discharging, and successfully extracting the threshold voltage of the first driving TFT to the pass end of the first driving TFT and storing the threshold voltage by a storage capacitor;
inputting a first scanning signal and a light-emitting control signal of a scanning line in a third time period into a low level, at the moment, closing a third switch TFT and a fourth switch TFT, locking the voltage of a channel end of a first driving TFT, and locking the voltage difference between two ends of a storage capacitor;
when the light emitting control signal is inputted with a high level in a fourth period, the first switching TFT and the third switching TFT are turned off, the second switching TFT is turned on, the voltage of the second path terminal of the first driving TFT is the voltage of the light emitting element, a conductive path is formed between the first power supply and the second power supply, and current flows through the light emitting element to emit light.
8. The in-pixel compensation compatible circuit according to claim 4, wherein: the method comprises the steps of having a first time period, a second time period, a third time period and a fourth time period which are continuous in an internal compensation mode;
in a first time period, a first scanning signal and a second light-emitting control signal of a scanning line input high level, a second scanning signal and a first light-emitting control signal of the scanning line input low level, a first switch TFT and a fourth switch TFT are closed, a second switch TFT and a third switch TFT are opened, and a first power supply voltage is input to a pass end of a first drive TFT to charge the first drive TFT;
inputting a high level into a first scanning signal and a second scanning signal of a scanning line in a second time period, inputting a low level into a first light-emitting control signal and a second light-emitting control signal, at the moment, closing a second switch TFT and a fourth switch TFT, enabling the third switch TFT, the first switch TFT and a first driving TFT to be in an open state, connecting a pass end and a second pass end of the first driving TFT together to form a connection mode of a diode, discharging the voltage of the pass end of the first driving TFT to the first switch TFT through the first driving TFT until the first driving TFT is closed when the voltage between a grid electrode and a drain electrode of the first driving TFT is reduced to a threshold voltage, stopping discharging, and successfully extracting the threshold voltage of the first driving TFT to the pass end of the first driving TFT and storing the threshold voltage by a storage capacitor;
inputting a high level into a second scanning signal and a first light-emitting control signal of the scanning line in a third time period, and inputting a low level into a first scanning signal and a second light-emitting control signal of the scanning line, wherein at the moment, the second switch TFT and the third switch TFT are closed, the voltage of the passage end of the first drive TFT is locked, and the voltage difference between two ends of the storage capacitor is also locked;
and in a fourth time period, the first light-emitting control signal and the second light-emitting control signal are input with high level, the first switch TFT and the third switch TFT are closed, the second switch TFT is opened, the voltage of the second channel end of the first drive TFT is the voltage of the light-emitting element, a conductive channel is formed between the first power supply and the second power supply, and current flows through the light-emitting element to emit light.
9. The in-pixel and out-pixel compensation compatible circuit according to claim 2, 3 or 4, wherein: the external compensation mode is provided with a first time period, a second time period and a third time period which are continuous;
the data voltage is input into a low level in a first time period, a switch of the pixel internal and external compensation compatible circuit connects the signal multiplexing line to the digital-to-analog converter, and the driving chip provides a reference voltage to the signal multiplexing line;
disconnecting the signal multiplexing line from the digital-to-analog converter by a switch of the driving chip in a second time period, and charging the signal multiplexing line and gradually increasing the voltage of the signal multiplexing line by the driving chip;
the third time period is a detection stage of the threshold voltage, the switch of the driving chip connects the signal multiplexing line to the analog-to-digital converter, and the driving chip detects the voltage of the signal multiplexing line through the analog-to-digital converter;
in the first, second, and third periods, the scan signal and the second light emission control signal of the scan line are input at a high level, and the first light emission control signal is input at a low level.
10. The in-pixel compensation compatible circuit according to claim 9, wherein: the first time period is a reset phase; the second time period is a threshold voltage extraction stage; the third time period is a detection phase.
CN201911164601.5A 2019-11-25 2019-11-25 Self-luminous display device and pixel internal and external compensation compatible circuit Pending CN111128069A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201911164601.5A CN111128069A (en) 2019-11-25 2019-11-25 Self-luminous display device and pixel internal and external compensation compatible circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201911164601.5A CN111128069A (en) 2019-11-25 2019-11-25 Self-luminous display device and pixel internal and external compensation compatible circuit

Publications (1)

Publication Number Publication Date
CN111128069A true CN111128069A (en) 2020-05-08

Family

ID=70496569

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201911164601.5A Pending CN111128069A (en) 2019-11-25 2019-11-25 Self-luminous display device and pixel internal and external compensation compatible circuit

Country Status (1)

Country Link
CN (1) CN111128069A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112201207A (en) * 2020-09-30 2021-01-08 合肥维信诺科技有限公司 Driving method of pixel circuit, pixel circuit and display device
CN112365836A (en) * 2020-11-09 2021-02-12 深圳市华星光电半导体显示技术有限公司 Gray scale compensation method and device for driving TFT, display panel and display device thereof
CN115313872A (en) * 2022-09-05 2022-11-08 芯洲科技（北京）有限公司 Electronic device for supplying power and power supply system
WO2023231677A1 (en) * 2022-05-30 2023-12-07 成都辰显光电有限公司 Pixel circuit and driving method therefor, and display device

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102725786A (en) * 2009-11-30 2012-10-10 伊格尼斯创新公司 System and methods for aging compensation in AMOLED displays
CN104064149A (en) * 2014-07-07 2014-09-24 深圳市华星光电技术有限公司 Pixel circuit, display panel with pixel circuit and displayers
US20160240122A1 (en) * 2014-06-27 2016-08-18 Lg Display Co., Ltd. Organic light emitting display for sensing electrical characteristics of driving element
CN106328061A (en) * 2016-10-14 2017-01-11 深圳市华星光电技术有限公司 OLED pixel mixing and compensating circuit and method
CN106910468A (en) * 2017-04-28 2017-06-30 上海天马有机发光显示技术有限公司 The driving method of display panel, display device and image element circuit
CN107622754A (en) * 2017-09-22 2018-01-23 京东方科技集团股份有限公司 Image element circuit and its control method, display base plate, display device
CN107657923A (en) * 2017-11-15 2018-02-02 合肥鑫晟光电科技有限公司 The detection method of image element circuit, the driving method of display panel, display device and image element circuit
CN107799062A (en) * 2017-11-27 2018-03-13 合肥鑫晟光电科技有限公司 A kind of image element circuit and its driving method, display device
WO2018152893A1 (en) * 2017-02-24 2018-08-30 深圳市华星光电半导体显示技术有限公司 Oled pixel drive circuit and oled display device
CN110235193A (en) * 2019-04-30 2019-09-13 京东方科技集团股份有限公司 Pixel circuit and its driving method, display device and its driving method

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102725786A (en) * 2009-11-30 2012-10-10 伊格尼斯创新公司 System and methods for aging compensation in AMOLED displays
US20160240122A1 (en) * 2014-06-27 2016-08-18 Lg Display Co., Ltd. Organic light emitting display for sensing electrical characteristics of driving element
CN104064149A (en) * 2014-07-07 2014-09-24 深圳市华星光电技术有限公司 Pixel circuit, display panel with pixel circuit and displayers
CN106328061A (en) * 2016-10-14 2017-01-11 深圳市华星光电技术有限公司 OLED pixel mixing and compensating circuit and method
WO2018152893A1 (en) * 2017-02-24 2018-08-30 深圳市华星光电半导体显示技术有限公司 Oled pixel drive circuit and oled display device
CN106910468A (en) * 2017-04-28 2017-06-30 上海天马有机发光显示技术有限公司 The driving method of display panel, display device and image element circuit
CN107622754A (en) * 2017-09-22 2018-01-23 京东方科技集团股份有限公司 Image element circuit and its control method, display base plate, display device
CN107657923A (en) * 2017-11-15 2018-02-02 合肥鑫晟光电科技有限公司 The detection method of image element circuit, the driving method of display panel, display device and image element circuit
CN107799062A (en) * 2017-11-27 2018-03-13 合肥鑫晟光电科技有限公司 A kind of image element circuit and its driving method, display device
CN110235193A (en) * 2019-04-30 2019-09-13 京东方科技集团股份有限公司 Pixel circuit and its driving method, display device and its driving method

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112201207A (en) * 2020-09-30 2021-01-08 合肥维信诺科技有限公司 Driving method of pixel circuit, pixel circuit and display device
CN112201207B (en) * 2020-09-30 2021-11-12 合肥维信诺科技有限公司 Driving method of pixel circuit, pixel circuit and display device
CN112365836A (en) * 2020-11-09 2021-02-12 深圳市华星光电半导体显示技术有限公司 Gray scale compensation method and device for driving TFT, display panel and display device thereof
CN112365836B (en) * 2020-11-09 2021-09-24 深圳市华星光电半导体显示技术有限公司 Gray scale compensation method and device for driving TFT, display panel and display device thereof
WO2023231677A1 (en) * 2022-05-30 2023-12-07 成都辰显光电有限公司 Pixel circuit and driving method therefor, and display device
CN115313872A (en) * 2022-09-05 2022-11-08 芯洲科技（北京）有限公司 Electronic device for supplying power and power supply system

Similar Documents

Publication Publication Date Title
CN113838421B (en) Pixel circuit, driving method thereof and display panel
US9111491B2 (en) Organic light emitting display device and method for driving the same
US9390652B2 (en) Organic light emitting display device and driving method thereof
CN110890056A (en) Self-luminous display device and in-pixel compensation circuit
US9589505B2 (en) OLED pixel circuit, driving method of the same, and display device
KR100931469B1 (en) Pixel and organic light emitting display device using same
CN109461410B (en) Organic light emitting diode display device
CN111128069A (en) Self-luminous display device and pixel internal and external compensation compatible circuit
US10621916B2 (en) Driving circuit and driving method thereof, and display device
EP3462437A1 (en) Organic light emitting display device and method for driving the same
KR101765778B1 (en) Organic Light Emitting Display Device
US10755643B2 (en) Display device and driving method thereof
CN107393478B (en) Pixel internal compensation circuit and driving method
JP2008040451A (en) Pixel and organic electroluminescence display device using same
CN103123773A (en) AMOLED (active matrix/optical light emitting diode) pixel driving circuit
CN110890055A (en) Self-luminous display device and in-pixel compensation circuit
KR20110078387A (en) Organic light emitting device and method of driving the same
KR101719481B1 (en) Organic light emitting device and driving method thereof
CN107978279B (en) Data voltage compensation method and device of pixel circuit and display system
CN113870790B (en) Pixel circuit, driving method thereof, display panel and display device
US11120741B2 (en) Display device and method for driving same
CN113487996A (en) Pixel driving circuit, display panel and display device
KR20170021406A (en) Degradation Sensing Method For Emitting Device Of Organic Light Emitting Display
CN110782842A (en) Self-luminous display device and in-pixel compensation circuit
CN111599314A (en) Self-luminous display device and in-pixel compensation circuit

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
TA01 Transfer of patent application right
TA01 Transfer of patent application right

Effective date of registration: 20200911

Address after: No.7 Tianyou Road, Qixia District, Nanjing City, Jiangsu Province

Applicant after: NANJING CEC PANDA LCD TECHNOLOGY Co.,Ltd.

Address before: Nanjing Crystal Valley Road in Qixia District of Nanjing City Tianyou 210033 Jiangsu province No. 7

Applicant before: NANJING CEC PANDA FPD TECHNOLOGY Co.,Ltd.

Applicant before: NANJING CEC PANDA LCD TECHNOLOGY Co.,Ltd.

Applicant before: Nanjing East China Electronic Information Technology Co.,Ltd.

RJ01 Rejection of invention patent application after publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20200508