CN111106082A

CN111106082A - Through silicon via interconnection structure and preparation method thereof

Info

Publication number: CN111106082A
Application number: CN201811270746.9A
Authority: CN
Inventors: 不公告发明人
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2018-10-29
Filing date: 2018-10-29
Publication date: 2020-05-05

Abstract

The invention relates to the technical field of semiconductors, and provides a through silicon via interconnection structure and a preparation method thereof, wherein the through silicon via interconnection structure comprises a multilayer substrate and a connecting wire; each layer of matrix of the multilayer matrix is provided with a plurality of silicon through holes, and the silicon through holes are partially communicated by sequentially staggering and stacking the matrix of each layer; the connecting wires are arranged in the silicon through holes so as to be communicated with corresponding circuits on the multilayer substrate. According to the invention, through the staggered arrangement of the substrates, through-silicon vias on the substrates of all layers are connected in a staggered manner to meet the requirement of through-silicon via (TSV) jumper, and the TSV jumper can be manufactured without using RDL; the through silicon via interconnection structure has good yield, and can reduce production time and production cost.

Description

Through silicon via interconnection structure and preparation method thereof

Technical Field

The invention relates to the technical field of semiconductors, in particular to a through silicon via interconnection structure and a preparation method thereof.

Background

Through Silicon Vias (TSVThrough Silicon Vias) are often used in saving valuable layout space or increasing the efficiency of interconnect lines. A through-silicon-via is a vertical conductive via that can completely penetrate a substrate or wafer made of silicon material.

The conventional through silicon via shift is formed by wire winding, and is generally achieved by using an RDL (Re-distribution layer).

But the manufacturing process is complicated, the manufacturing process takes too long, the cost is too high, and the yield is low.

Therefore, there is a need to develop a new through silicon via interconnect structure and a method for fabricating the same.

The above information of the invention of this background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not constitute prior art that is already known to a person of ordinary skill in the art.

Disclosure of Invention

The invention aims to overcome the defects of too long time consumption, too high cost and low yield in the prior art, and provides a through silicon via interconnection structure which is good in quality and can reduce the production time consumption and the production cost, and a preparation method thereof.

Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.

According to one aspect of the present disclosure, a through silicon via interconnect structure includes:

the multilayer substrate is provided with a plurality of silicon through holes, and the silicon through holes are partially communicated by sequentially staggering and stacking the substrates;

and the connecting wires are arranged in the silicon through holes so as to communicate with corresponding circuits on the multilayer substrate.

In an exemplary embodiment of the present disclosure, the substrate is one of a wafer and a chip.

In an exemplary embodiment of the present disclosure, the through-silicon via interconnect structure further includes:

and the dislocation alignment marks are arranged on each layer of the substrate.

In an exemplary embodiment of the present disclosure, the misalignment alignment marks are provided in two.

In an exemplary embodiment of the disclosure, a distance between two of the misalignment alignment marks is the same as a misalignment distance of two adjacent layers of the substrate.

In an exemplary embodiment of the present disclosure, the misalignment distance is 10 μm or more and 60 μm or less.

the substrate base body is provided with a plurality of connecting conductors, and the substrate base body and the plurality of layers of base bodies are arranged in a staggered mode to enable the connecting conductors to be correspondingly communicated with the connecting wires.

In an exemplary embodiment of the present disclosure, the substrate base is a wafer or a chip.

and the slide glass is arranged on one surface of the substrate base body, which is far away from the base body.

According to an aspect of the present disclosure, there is provided a method for manufacturing a through silicon via interconnection structure, including:

providing a multi-layer substrate, and forming a plurality of through silicon vias on each layer of the substrate;

forming a connecting lead in the through-silicon-via;

and sequentially bonding the multiple layers of the substrates in a staggered manner to ensure that the connecting wires are connected in a staggered manner so as to communicate with corresponding circuits on the multiple layers of the substrates.

providing a multi-layer substrate, and bonding the multi-layer substrate in a staggered manner in sequence;

forming a plurality of through-silicon vias on the plurality of layers of the substrate, wherein the through-silicon vias penetrate through one layer of the substrate, two layers of the substrate or a plurality of layers of the substrate;

and forming connecting leads in the through-silicon vias, wherein the connecting leads are communicated with corresponding circuits on the multilayer substrate.

In an exemplary embodiment of the present disclosure, a misalignment alignment mark is formed on the substrate, and a plurality of substrates are misaligned and bonded according to the misalignment alignment mark.

In an exemplary embodiment of the present disclosure, the preparation method further includes:

providing a substrate base on which a plurality of connection conductors are formed;

and arranging the substrate base body and the plurality of layers of base bodies in a staggered manner to enable the connecting conductors to be correspondingly communicated with the connecting leads.

In an exemplary embodiment of the present disclosure, a carrier sheet is provided, and the carrier sheet is disposed on a side of the substrate base body away from the base body.

According to the technical scheme, the invention has at least one of the following advantages and positive effects:

the through silicon via interconnection structure and the preparation method thereof can comprise a multilayer substrate and a connecting lead; a plurality of silicon through holes are formed in each layer of base body, and the base bodies are sequentially arranged in a staggered and stacked mode to enable the silicon through holes to be partially communicated; the connecting wires are arranged in the silicon through holes so as to be communicated with corresponding circuits on the multilayer substrate. On one hand, the Through Silicon Via (TSV) jumper wire on each layer of substrate is connected in a staggered mode through the staggered arrangement of the substrates, the TSV jumper wire can be manufactured without using RDL, the manufacturing speed of a semiconductor device is increased, on the other hand, due to the fact that the TSV is not manufactured with the RDL, multiple times of RDL yellow light is reduced, the yield of the produced semiconductor device is high, and meanwhile production time and production cost are reduced.

Drawings

The above and other features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.

FIG. 1 is a schematic diagram of a through silicon via interconnect structure in the related art;

FIG. 2 is a schematic diagram of a through silicon via interconnect structure in one embodiment of the invention;

FIG. 3 is a schematic diagram of a through silicon via interconnect structure in another embodiment of the invention;

FIG. 4 is a schematic structural view of the substrate base of FIG. 2;

FIG. 5 is a schematic view of the structure of the substrate;

FIG. 6 is a schematic diagram of a structure after a carrier is formed on the basis of FIG. 5;

FIG. 7 is a schematic structural view of the silicon substrate after being milled on the basis of FIG. 6;

FIG. 8 is a schematic view of the misalignment alignment marks of the present invention;

FIG. 9 is a block diagram of the present invention after the substrate is attached to the substrate base;

FIG. 10 is a schematic view of the structure of FIG. 8 with the carrier removed;

FIG. 11 is a schematic flow chart of a method of fabricating a through silicon via interconnect structure;

FIG. 12 is a schematic flow chart of another method for fabricating a through silicon via interconnect structure;

FIG. 13 is a schematic diagram of a through-silicon-via interconnect structure after placement of a carrier;

fig. 14 is a schematic diagram of a through-silicon-via interconnect structure when the substrate is a chip.

The reference numerals of the main elements in the figures are explained as follows:

1. a rewiring layer; 2. perforating silicon; 3. a connecting conductor; 4. a first material layer; 5. a substrate; 6. a substrate base; 7. a substrate; 701. a chip; 8. a top carrier; 9. a first misalignment alignment mark; 10. a second misalignment alignment mark; 11. connecting a lead; 12. carrying a slide; n, dislocation distance; m, spacing.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed description will be omitted.

Referring to fig. 1, a schematic diagram of a tsv interconnection structure in the related art is shown, in the related art, the tsv displacement is formed by winding a metal wire, generally requiring RDL (redistribution layer 1), which is complex in manufacturing process, requiring more time, and having higher cost and lower yield.

The invention provides a through silicon via interconnection structure, which can comprise a multilayer matrix 7 and a substrate matrix 6, and is shown in a schematic diagram of the through silicon via interconnection structure in the invention with reference to fig. 2; a plurality of silicon through holes 2 are formed in each layer of matrix 7, and the silicon through holes 2 are communicated in a staggered manner due to the staggered arrangement of the matrix 7 in each layer; connecting wires 11 are provided in the through-silicon vias 2 to connect corresponding circuits on the multi-layer substrate.

In the present exemplary embodiment, the material of the connection wire 11 may include copper, polysilicon, tungsten metal, and other related integrated circuit conductive materials; the through silicon via 2(TSV) outer layer insulating material may include silicon oxide, silicon nitride, and the like, as related integrated circuit insulating materials.

In the present example embodiment, referring to fig. 4 and 5, the tsv interconnect structure may include a substrate base 6 and a base 7, the substrate base 6 may include a base plate 5 and a first material layer 4, a plurality of connection conductors 3 are disposed on an upper surface of the first material layer 4, a material of the base plate may be silicon, that is, the base plate 5 is a silicon substrate; in another embodiment, the substrate may be made of a semiconductor or an insulator; such as glass. And is not particularly limited in the present exemplary embodiment.

In the present example embodiment, referring to fig. 4, the base 7 may include a substrate 5, a first material layer 4, a connection conductor 3, and a plurality of through-silicon-vias 2; the substrate 5 may be a silicon substrate; the through-silicon-via 2 penetrates the substrate 7.

In the present exemplary embodiment, as shown in fig. 4 and 5, the base 7 may be an upper wafer, each layer of the base 7 may be provided with a plurality of connecting conductors 3, and the plurality of connecting conductors 3 on the base may be divided into two regions, a left region and a right region. The left side region is provided with four connecting conductors 3, the four connecting conductors 3 are uniformly distributed, the right side region is also provided with four connecting conductors 3, and the four connecting conductors 3 are uniformly distributed. The spacing between two adjacent connecting conductors 3 in each region is the same, and a larger spacing exists between the two regions. In another example embodiment, the number of the connection conductors 3 per region may be three, five or more. No particular limitation is imposed in the present exemplary embodiment.

Referring to fig. 5, the connection conductor 3 is formed in the first material layer 4 without protruding from the first material layer 4. The through silicon via 2 and the connecting conductor 3 may be vertically disposed, and correspondingly, the connecting lead 11 and the connecting conductor 3 are also vertically disposed, so that the substrates 7 of each layer are sequentially arranged in a staggered manner to make the through silicon via 2 communicate in a staggered manner. Of course, the through-silicon via 2 and the connection conductor 3 may not be vertically arranged, and the through-silicon via 2 may be arranged to be staggered and connected by sequentially staggering the layers of the substrate 7, which is not particularly limited in the present exemplary embodiment.

In an exemplary embodiment, referring to fig. 8, a schematic diagram of misalignment alignment marks according to the present invention, the tsv interconnect structure may further include two misalignment alignment marks disposed at the same position on each layer of the substrate 7, and the first and second misalignment alignment marks 9 and 10; more may be provided, and this embodiment is not particularly limited. In another embodiment, only one misalignment mark may be provided at a certain misalignment distance from the side edge of the substrate, and it is only necessary to align the side edge of the other substrate with the misalignment mark when performing the misalignment bonding. In another embodiment, the misalignment alignment mark may not be provided, and the multilayer substrates may be misaligned by a predetermined misalignment distance N under the control of a computer during the misalignment bonding.

Referring to fig. 8, the distance M between the first misalignment alignment mark 9 and the second misalignment alignment mark 10 is the same as the misalignment distance N of the two adjacent substrates 7, so that the misalignment of the two adjacent substrates 7 is only required to be misaligned with the alignment mark, for example, the first misalignment alignment mark 9 of the substrate 7 is aligned with the second misalignment alignment mark 10 of the substrate 6. The provision of the misalignment alignment mark can make it more accurate when bonding the multilayer substrate 7.

In the present exemplary embodiment, the misalignment distance N may be 10 μm or more and 60 μm or less; the distance M between the corresponding first misalignment alignment mark 9 and the second misalignment alignment mark 10 may be greater than or equal to 10 μ M and less than or equal to 60 μ M.

In this exemplary embodiment, referring to fig. 8, the first misalignment alignment mark 9 may be a cross-shaped structure, the second misalignment alignment mark 10 may also be a cross-shaped structure, and the two misalignment alignment marks may be triangular in shape, and when performing alignment, the corresponding corners may be misaligned with each other; of course, the shape of the misalignment alignment mark may be a rectangle, a pentagon, a hexagon, or the like, and is not particularly limited in this embodiment.

In the present exemplary embodiment, referring to fig. 2, the tsv interconnect structure may be composed of four layers of substrates, or may be composed of more layers of substrates, the number of layers of substrates is not specifically limited in this embodiment, and the substrates in the layers are arranged in a staggered manner, which may be shifted to the right by the same offset distance N from bottom to top. The through-silicon vias 2 of the respective layers of the substrate 7 can be connected to each other in a staggered manner, and the connecting wires 11 provided in the through-silicon vias 2 can also be connected to each other in a staggered manner. The first material layer 4 of each layer of the substrate 7 is provided with a connecting conductor 3. The connection conductors 3 make the electrical connection between the layers of the substrate 7 more reliable.

Referring to fig. 2, through-silicon via 2 is opened in multilayer substrate 7 after the bonding, and through-silicon via 2 is opened from the center of connection conductor 3 to penetrate multilayer substrate 7. In some regions, the through-silicon vias 2 penetrate through one layer of the substrate 7, in some regions the through-silicon vias 2 penetrate through two layers of the substrate 7, and in some regions the through-silicon vias 2 penetrate through a plurality of layers of the substrate 7. For example, in fig. 2 the uppermost through-silicon-via 2 closest to the rightmost side only penetrates one layer of the substrate 7. The leftmost side of each layer of the substrate 7 is provided with a connecting conductor 4 which is not connected with the connecting lead 11 arranged in the through-silicon-via 2, and the structure can play a better heat dissipation role to a certain extent.

Of course, in another embodiment, referring to fig. 3, the offset pattern may be set to be offset to the left and right, for example, the second layer substrate is offset to the right with respect to the substrate 6, the third layer substrate is offset to the left with respect to the second layer substrate, i.e., the odd layers are aligned with each other, and the even layers are also aligned with each other. Through-silicon-vias 2 are formed through the multilayer matrix 7. On the one hand, the matrix 7 takes up less area in the presence of more layers; on the other hand, the vertical arrangement is adopted, so that the structure is stable and is not easy to collapse.

Referring to fig. 13, the through-silicon-via displacement structure may further include a carrier 12, the carrier 12 having a substrate base 6 formed thereon, and a base 7 formed on the substrate base 6; the material of the carrier sheet 12 can be a semiconductor or an insulator; such as glass, silicon plates, etc.

In another exemplary embodiment of the present invention, referring to fig. 14, the substrate 7 in the through-silicon via interconnect structure may also be a chip 701; forming a chip 701 on a substrate base 6; the chip 701 and the substrate base 6 are sequentially arranged in a staggered and stacked mode to form a through silicon via interconnection structure. The chip 701 may include a substrate 5, a first material layer 4, a connection conductor 3, and a through-silicon-via 2; the substrate 5, the first material layer 4, the connection conductor 3 and the through-silicon-via 2 have already been described in detail above, and therefore no further description is given here.

Of course, in this embodiment, the tsv interconnection structure may also include a carrier 12, where the carrier 12 forms the substrate base 6, and the chip 701 is formed on the substrate base 6; the material of the carrier sheet 12 can be a semiconductor or an insulator; such as glass, silicon plates, etc.

Furthermore, the invention also provides a preparation method corresponding to the through silicon via interconnection structure; referring to fig. 11, the preparation method may include the steps of:

step S110, providing a multi-layer substrate, and forming a plurality of through-silicon vias 2 on each layer of the substrate.

Step S120, forming a connection wire 11 in the through-silicon via 2.

And step S130, sequentially bonding the multiple layers of the substrates in a staggered manner, so that the connecting wires 11 are connected in a staggered manner to communicate with corresponding circuits on the multiple layers of the substrates.

The following describes the steps of the method for fabricating the through-silicon via interconnect structure in detail:

in step S110, a multi-layer substrate is provided, and a plurality of through-silicon vias are formed in each layer of the substrate.

In step S120, a connection wire 11 is formed within the through-silicon via 2.

In the present exemplary embodiment, referring to fig. 5, a connection wire 11 is disposed in the through-silicon via 2, and the through-silicon via 2 is bonded to the wire, and the material of the connection wire 11 may include a conductive material of an integrated circuit such as copper and tungsten metal.

Referring to fig. 5, the base 7 may include a substrate 5, a first material layer 4, a connection conductor 3, and a plurality of through-silicon-vias 2; the substrate 5 may be a silicon substrate, and the through-silicon-via 2 penetrates the base body.

In step S130, the multiple layers of the substrates are sequentially bonded in a staggered manner, so that the connecting wires 11 are connected in a staggered manner to connect corresponding circuits on the multiple layers of the substrates.

First, as shown in fig. 6, the top carrier 8 is formed on the base 7 by bonding in order to prevent warpage due to the thinness of the base when the base is subsequently ground, the bonding being temporary bonding.

Then, referring to fig. 7, the back surface of the substrate 5 is thinned to expose the connection leads 11, so that the incompletely opened through-silicon vias described above are completely opened. The base 7 is Chip-bonded or Hybrid-bonded to the substrate base 6, and the first misalignment alignment mark 9 of the base is aligned with the second misalignment alignment mark of the substrate base 6, so that the connection lead 11 provided on the base 7 can be connected to the connection conductor 3 provided on the substrate base 6.

Finally, as shown in fig. 9, the top carrier 8 is debonded to expose the top connection conductors 3 of the base 7. The debonding method includes chemical debonding, mechanical debonding, UV debonding, etc.

In the present exemplary embodiment, as shown in fig. 2, the steps in the above-described embodiment are performed multiple times, a through-silicon-via 2 structure with a multilayer structure may be formed, and the through-silicon-via 2 structure may be composed of four layers of substrates, two layers or three layers, or more layers of substrates, and is not particularly limited in this embodiment.

In the present exemplary embodiment, the substrates 7 of the respective layers are arranged in a staggered manner, and the staggered manner may be that the substrates are sequentially shifted to the right by the same staggered distance N from bottom to top. The through-silicon vias 2 of the respective layers of the substrate 7 can be connected to each other in a staggered manner, and the connecting wires 11 provided in the through-silicon vias 2 can also be connected to each other in a staggered manner. The upper surface of each layer of the substrate 7 is provided with a connecting conductor 3. The connection conductors 3 make it possible to make the electrical connection between the layers of the substrate 7 safer.

Of course, in another embodiment, referring to fig. 3, the offset pattern may be set to be offset to the left and right, for example, the second layer substrate is offset to the right with respect to the substrate 6, the third layer substrate is offset to the left with respect to the second layer substrate, i.e., the odd layers are aligned with each other, and the even layers are also aligned with each other. The design occupies less area in the presence of a plurality of layers of matrixes 7, is vertically arranged, is not easy to collapse and has a stable structure.

In an exemplary embodiment, referring to fig. 8, a schematic diagram of misalignment alignment marks according to the present invention, the through-silicon-via 2 structure may further include misalignment alignment marks disposed at the same position on each layer of the substrate 7, and the misalignment alignment marks may be two, namely, a first misalignment alignment mark 9 and a second misalignment alignment mark 10; more may be provided, and this embodiment is not particularly limited. In another embodiment, only one misalignment alignment mark may be provided at a certain misalignment distance N from the side edge of the substrate, and when performing the misalignment bonding, only the side edge of the other substrate needs to be aligned with the misalignment alignment mark. In another embodiment, the misalignment alignment mark may not be provided, and a computer may be used to control the misalignment bonding of the multilayer substrates so that a predetermined misalignment distance is generated between the multilayer substrates.

In the present exemplary embodiment, as shown in fig. 8, the first misalignment alignment mark 9 may be a cross-shaped structure, and the second misalignment alignment mark 10 may also be a cross-shaped structure; the two staggered alignment marks can be triangular, and corresponding angles can be staggered and aligned with each other when alignment is carried out; of course, the shape of the misalignment alignment mark may be a rectangle, a pentagon, a hexagon, or the like, and is not particularly limited in this embodiment. In the present exemplary embodiment, the distance M between the first misalignment alignment mark 9 and the second misalignment alignment mark 10 is the same as the misalignment distance N of the two adjacent substrates 7, so that it is only necessary to align the misalignment pair alignment marks of the two adjacent substrates 7 in a misalignment manner when positioning, for example, the first misalignment alignment mark 9 of the substrate 7 is aligned with the second misalignment alignment mark 10 of the substrate 6. The provision of the misalignment pair alignment marks makes it possible to make the bonding of the multilayer substrate 7 more accurate.

The dislocation distance N can be more than or equal to 10 μm and less than or equal to 60 μm; the distance M between the corresponding first misalignment alignment mark 9 and the second misalignment alignment mark 10 may be greater than or equal to 10 μ M and less than or equal to 60 μ M.

Referring to fig. 4 and 5, a plurality of connection conductors 3 are provided on the base 7, and the connection conductors 3 are formed in the first material layer 4 so as not to protrude from the first material layer 4. The plurality of connection conductors 3 on the base body may be divided into two regions, a left region and a right region. The left side region is provided with four connecting conductors 3, the four connecting conductors 3 are uniformly distributed, the right side region is also provided with four connecting conductors 3, and the four connecting conductors 3 are uniformly distributed. The spacing between two adjacent connecting conductors 3 in each region is the same, and a larger spacing exists between the two regions. In another example embodiment, the number of the connection conductors 3 per region may be three, five or more. No particular limitation is imposed in the present exemplary embodiment.

The base 7 is Chip-bonded or Hybrid-bonded to the substrate base 6, and the first misalignment alignment mark 9 of the base 7 is aligned with the second misalignment alignment mark of the substrate base 6, so that the connection wire 11 provided on the base 7 can be connected to the connection conductor 3 provided on the substrate base 6.

Referring to fig. 13, the through-silicon-via displacement structure may further include a carrier sheet 12, first forming a substrate base 6 on the carrier sheet 12, and forming a base 7 on the substrate base 6; the material of the carrier sheet 12 can be a semiconductor or an insulator; such as glass, silicon plates, etc. The method of forming the base 7 on the substrate base 6 has been described in detail above and therefore will not be described in detail here.

In the present exemplary embodiment, the through silicon via 2(TSV) plasma etching and copper filling processes are performed, and then the multi-layer substrate 7 is bonded together using Chip bonding or Hybrid bonding. In another embodiment, the TSV interconnect structure may be fabricated by bonding a plurality of substrates 7, and then performing a TSV 2(TSV) plasma etching and copper filling process. Therefore, another method for manufacturing the through silicon via interconnection structure can be proposed. Another method of fabricating a through silicon via interconnect structure is described below. Referring to fig. 12, the preparation method may include the steps of:

step S210, providing a multilayer substrate, and sequentially bonding the multilayer substrate in a staggered manner.

Step S220, forming a plurality of through-silicon vias 2 on the plurality of layers of the substrate, wherein the through-silicon vias 2 penetrate through one layer of the substrate, two layers of the substrate, or a plurality of layers of the substrate.

Step S230, forming a connection wire 11 in the through-silicon via 2, where the connection wire 11 is connected to a corresponding circuit on the multilayer substrate.

The steps of the method for fabricating the through-silicon via interconnect structure are described in detail below.

In step S210, a multi-layer substrate is provided, and the multi-layer substrate is sequentially bonded in a staggered manner.

In the present exemplary embodiment, the through-silicon-via interconnect structure further includes a substrate base 6; referring to fig. 3, the substrate base 6 may include a base plate 5 and a first material layer 4, and the first material layer 4 is provided with a plurality of connection conductors 3 thereon.

In the present exemplary embodiment, the multilayer substrate 7 may be a multilayer upper wafer, and in another embodiment, the multilayer substrate may also be a multilayer chip 701 or a multilayer chip 701 mixed with an upper wafer. Each layer of the substrate 7 is provided with the connecting conductors 3, as shown in fig. 3, the plurality of connecting conductors 3 provided on the substrate 7 may be divided into two regions, i.e., a left region and a right region, the interval between two adjacent connecting conductors 3 in each region is the same, and a larger interval exists between the two regions.

In the present exemplary embodiment, the multilayer base 7 is bonded to the substrate base 6 by forming a misalignment stack structure using the misalignment alignment marks, and bonding the substrate base to the substrate base. So that the connection conductors 3 on the multilayer base body 7 are misaligned. The offset mode can be that the offset is sequentially shifted to the right from bottom to top by the same offset distance N.

Of course, in another embodiment, the offset may be arranged to be offset to the left and right, for example, the second layer is offset to the right relative to the first layer, and the third layer is offset to the left relative to the second layer, i.e. the odd layers are aligned with each other, and the even layers are also aligned with each other. The design occupies less area in the presence of a plurality of layers of matrixes 7, is vertically arranged, is not easy to collapse and has a stable structure.

In the present exemplary embodiment, as shown in fig. 2, through-silicon via 2 is opened in multi-layer substrate 7 after the bonding, and through-silicon via 2 is opened from the center of connection conductor 3 to penetrate multi-layer substrate 7. In some regions, the through-silicon vias 2 penetrate through one layer of the substrate 7, in some regions the through-silicon vias 2 penetrate through two layers of the substrate 7, and in some regions the through-silicon vias 2 penetrate through a plurality of layers of the substrate 7. For example, in fig. 2, the uppermost through-silicon-via 2 closest to the rightmost side only penetrates one layer of the substrate 7. The leftmost side of each layer of the substrate is provided with a connecting conductor 4 which is not connected with the connecting lead 11 arranged in the through-silicon-via 2, and the structure can play a better heat dissipation role to a certain extent.

In the present exemplary embodiment, the connection wire 11 is provided within the through-silicon via 2 formed as described above so that the circuits of the multilayer circuit are connected.

The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments, and the features discussed in connection with the embodiments are interchangeable, if possible. In the above description, numerous specific details are provided to give a thorough understanding of embodiments of the invention. One skilled in the relevant art will recognize, however, that the invention may be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the invention.

Although relative terms, such as "upper" and "lower," may be used in this specification to describe one element of an icon relative to another, these terms are used in this specification for convenience only, e.g., in accordance with the orientation of the examples described in the figures. It will be appreciated that if the device of the icon were turned upside down, the element described as "upper" would become the element "lower". Other relative terms, such as "high", "low", "top", "bottom", and the like, are also intended to have similar meanings. When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via another structure.

In this specification, the terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements/components/etc.; the terms "comprising," "including," and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. other than the listed elements/components/etc.; the terms "first," "second," and "third," etc. are used merely as labels, and are not limiting on the number of their objects.

It is to be understood that the invention is not limited in its application to the details of construction and the arrangement of components set forth in the description. The invention is capable of other embodiments and of being practiced and carried out in various ways. The foregoing variations and modifications fall within the scope of the present invention. It will be understood that the invention of the present specification and defined invention extends to all alternative combinations of two or more of the individual features mentioned or evident from the text and/or drawings. All of these different combinations constitute alternative aspects of the present invention. The embodiments described in this specification illustrate the best mode known for carrying out the invention and will enable those skilled in the art to utilize the invention.

Claims

1. A through silicon via interconnect structure, comprising:

2. The through-silicon-via interconnect structure of claim 1, wherein the substrate is one of a wafer and a chip.

3. The through-silicon-via interconnect structure of claim 1, further comprising:

4. The through-silicon-via interconnect structure of claim 3, wherein the misalignment alignment marks are provided in two.

5. The through-silicon-via interconnect structure of claim 4, wherein a spacing between two of the misalignment alignment marks is the same as a misalignment distance of two adjacent layers of the substrate.

6. The through-silicon-via interconnect structure of claim 5, wherein the misalignment distance is greater than or equal to 10 μ ι η and less than or equal to 60 μ ι η.

7. The through-silicon-via interconnect structure of claim 1, further comprising:

8. The through-silicon-via interconnect structure of claim 7, wherein the substrate base is a wafer or a chip.

9. The through-silicon-via interconnect structure of claim 8, further comprising:

10. A method for fabricating a through silicon via interconnect structure, comprising:

forming a connecting lead in the through-silicon-via;

11. A method for fabricating a through silicon via interconnect structure, comprising:

12. The method of claim 10 or 11, wherein the substrate is one of a wafer and a chip.

13. The method of manufacturing a through-silicon-via interconnect structure according to claim 10 or 11, wherein a misalignment alignment mark is formed on the substrate, and a plurality of the substrates are misaligned and bonded according to the misalignment alignment mark.

14. The method of claim 13, wherein two misalignment alignment marks are provided.

15. The method of claim 14, wherein a pitch between two misalignment alignment marks is the same as a misalignment distance between two adjacent layers of the substrate.

16. The method of claim 14, wherein the offset distance is greater than or equal to 10 μm and less than or equal to 60 μm.

17. The method of claim 10 or 11, further comprising:

18. The method of claim 17, wherein the substrate base is a wafer or a chip.

19. The method of claim 17, wherein a carrier is provided and is disposed on a side of the substrate base away from the base.