CN111104101A - Carry chain structure with slice cavity and test method - Google Patents
Carry chain structure with slice cavity and test method Download PDFInfo
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- CN111104101A CN111104101A CN201911081079.4A CN201911081079A CN111104101A CN 111104101 A CN111104101 A CN 111104101A CN 201911081079 A CN201911081079 A CN 201911081079A CN 111104101 A CN111104101 A CN 111104101A
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Abstract
The embodiment of the invention provides a method for constructing an FPGA carry chain with a slice hole, which is characterized by comprising the following steps: judging the current position as slice or cavity; judging the previous position as slice or cavity; according to the conditions of the current position and the previous position, carrying out new construction of a carry chain or cascade connection or neither new construction nor cascade connection; traversing all positions according to the method; and a method for testing a carry chain constructed by the method, comprising: the carry chain penetrates through a plurality of slices, each slice comprises a segment, each segment comprises a plurality of primitives, and in the step 1, the correctness of the primitives is judged; step 2, judging the correctness of the connection relation between every two adjacent primitives; and the step 1 and the step 2 adopt the test cases to judge the correctness.
Description
Technical Field
The invention belongs to the field of FPGA (field programmable gate array) testing, and particularly relates to a carry chain structure with a slice cavity and a testing method.
Background
The Xilinx FPGA internally comprises configurable logic and is composed of a large number of slices, each slice comprises a carry chain segment, FIG. 1 is a schematic diagram of the carry chain segment and a peripheral related circuit thereof, each carry chain segment comprises a plurality of carry primitives, each primitive pair is carry logic of one bit, the carry segments shown in FIG. 1 totally comprise two carry primitives, and the number of the carry primitives contained in the carry segments depends on the specific model of the FPGA. The carry chains in multiple slices can be connected together to form a longer carry chain to meet the requirement of multi-bit addition operation, see fig. 2. The carry chain test is one item of FPGA test. The slices of a part of the FPGAs of Xilinx are arranged in series as shown in fig. 2. The slices of the other part of the FPGA are arranged discontinuously, and contain a plurality of "holes", as shown in fig. 3. Continuous and discontinuous here means whether the coordinates are continuous or not.
Disclosure of Invention
The invention aims to provide a method for constructing an FPGA carry chain with a slice hole, which is characterized by comprising the following steps:
judging the current position as slice or cavity;
judging the previous position as slice or cavity;
according to the conditions of the current position and the previous position, carrying out new construction of a carry chain or cascade connection or neither new construction nor cascade connection;
all positions are traversed according to the method described above.
Preferably, when the current position is slice and the previous position is a hole, a new carry chain is executed.
Preferably, when the current location is slice and the previous location is slice, the cascade connection is performed.
Preferably, when the current position is a hole and the previous position is a slice or a hole, neither new construction nor concatenation is performed.
The invention also provides a test method of the carry chain, the carry chain construction method with slice holes is characterized in that the carry chain penetrates through a plurality of slices, each slice comprises a segment, each segment comprises a plurality of elements, wherein, in the step 1, the correctness of the elements is judged; step 2, judging the correctness of the connection relation between every two adjacent primitives; and the step 1 and the step 2 adopt the test cases to judge the correctness.
Preferably, the method for determining the correctness of the primitive in step 1 is as follows: the element and the LUT form a one-bit adder with carry, wherein the LUT is a truth table of exclusive-OR logic, and the input value is given according to the truth table to judge whether the actual output of the adder meets the expected output of the truth table of the one-bit carry adder; if so, the primitive is correct.
Preferably, the method for judging the correctness of the connection relationship between every two adjacent primitives in step 2 is as follows: if the carry output of the previous primitive is equal to the carry input of the next primitive in real time and accords with the truth table of the connecting line segment of the two one-bit adders, the connection relation of every two adjacent primitives is correct.
Preferably, one or more test cases are used to override the one-bit carry adder truth table and the connection segment truth table of the two one-bit adders.
Preferably, when the inputs of the addition end and the carry end of the adder are both 1 and 0 or when the inputs of the addition end and the carry end of the adder are both 0 and 1, the FPGA is configured to disconnect the primitives, a single-primitive test is adopted, and a plurality of test cases are required.
Preferably, the FPGA is configured to connect two primitives adjacent to each other on the carry chain, and the addition input end of the current primitive is 0, and the carry end is 1, and the addition input end of the primitive adjacent to the current primitive is 1, and the carry end is 0, then a test case is used to test the carry chain.
The beneficial effects of the invention include:
and the complex carry chain test is converted into the test of the connection relation between the carry primitive and the primitive. Under the condition of higher test efficiency, the test coverage rate of the carry chain is ensured to reach 100 percent.
Drawings
FIG. 1 is a diagram of a carry chain segment according to an embodiment of the present invention;
FIG. 2 is a slice array diagram without voids according to an embodiment of the present invention;
FIG. 3 is a slice array diagram with voids according to an embodiment of the present invention;
FIG. 4 shows two one-bit adder connection structures according to an embodiment of the present invention;
FIG. 5 is a one-bit adder according to an embodiment of the present invention;
FIG. 6 shows two one-bit adder connection modes according to an embodiment of the present invention;
FIG. 7 is a block diagram of a test module according to an embodiment of the present invention;
FIG. 8 is a diagram of a test method employing multiple test cases according to an embodiment of the present invention;
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
The embodiment of the invention provides a method for constructing an FPGA carry chain with a slice hole, which is characterized by comprising the following steps:
judging the current position as slice or cavity;
judging the previous position as slice or cavity;
according to the conditions of the current position and the previous position, carrying out new construction of a carry chain or cascade connection or neither new construction nor cascade connection;
all positions are traversed according to the method described above.
According to an embodiment of the present invention, when the current position is slice and the previous position is a hole, a new carry chain is executed.
According to one embodiment of the present invention, when the current location is slice and the previous location is slice, the cascade is executed.
According to one embodiment of the present invention, when the current location is a hole, the previous location is slice or a hole, neither new creation nor concatenation is performed.
The method is explained in detail below. The FPGA internally comprises configurable logic and is composed of a large number of slices, each slice comprises a carry chain segment, fig. 1 is a schematic diagram of a carry chain segment and a peripheral related circuit thereof, each carry chain segment comprises a plurality of carry primitives, each primitive pair is carry logic of one bit, the carry segments shown in fig. 1 totally comprise two carry primitives, and the number of the carry primitives contained in the carry segments depends on the specific model of the FPGA. The carry chains in multiple slices can be connected together to form a longer carry chain to meet the requirement of multi-bit addition operation, see fig. 2. The carry chain test is one item of FPGA test. The slices of a part of the FPGAs of Xilinx are arranged in series as shown in fig. 2. The slices of the other part of the FPGA are arranged discontinuously, and contain a plurality of "holes", as shown in fig. 3. Continuous and discontinuous here means whether the coordinates are continuous or not.
As shown in fig. 1, the schematic diagram of the carry chain in a single Slice and its peripheral related circuits is shown, and the schematic diagram includes 1 carry chain segment and 2 LUTs, where an LUT is a lookup table, the lookup table of the Xilinx FPGA is a multi-way input, 1-way output, and the number of input ways is related to a specific model. A two-input LUT may implement a 2-input no-carry adder with a truth table, see table 1, which is the truth table for the xor operation. A and B are input of the no-carry adder, and S is output, namely the sum of A and B. In general, the Xilinx FPGA LUT has more than two inputs and still can implement a 2-input adder, as shown in table 2, a 6-input adder, a, B, C, D, E, F as inputs, S as outputs, X represents any value between 0 and 1, and table 2 can be reduced to table 1.
Table 1: no-carry binary input adder truth table
Table 2: truth table of no-carry binary input adder formed by 6-input LUT
The test of the carry chain can be carried out by the addition operation of the multi-bit carry chain, note that: the subtraction operation can be normalized to an addition operation, with A-B equal to A + (the complement of B). A bit-with-carry addition operation may be implemented by forming the LUT of the non-carry adder and a carry primitive as shown in fig. 4.
Fig. 4 can be divided into two identical modules, whose true values are shown in table 3 according to the principle, and the algorithm is as follows:
1) in any case, the sum S of A and B is the XOR of A and B.
2) For the output COUT to the high bit, when (a is 0 and B is 0) or (a is 1 and B is 1), the channel 0 of the multiplexer MUX is turned on, COUT is B, and when B is 0, COUT is 0. COUT is 1 when B is 1, rows 1, 4, 7, 8 of the truth table are verified, when (a is 1 and B is 0) or (a is 0 and B is 1), the exclusive or of a and B is 1, channel 1 of the multiplexer MUX is turned on, i.e., COUT is CIN, when CIN is 0, COUT is 0 and CIN is 1, COUT is 1, rows 2,3, 5,6 of the truth table are verified.
Table 3 is the truth table of the 1-bit adder with carry. A and B are two inputs of the adder, S is the sum of A and B, CIN is the carry of the low order bit to the adder, COUT is the carry of the high order bit of the adder, which can be abstracted as FIG. 5. It can be concluded that the two-block configuration of fig. 4 is a two-1-bit adder with carry. Since the output COUT of one of the adders is connected to the input of the other adder, fig. 4 shows an adder with a two-bit carry-in function, which can be abstracted as fig. 6.
And by analogy, the carry chain formed by a plurality of adders can be converted into the test of the multi-bit adder. The testing of the multi-bit adder covers the following.
1) Each one-bit adder is tested for correctness, i.e., the 3-input 2-output truth table for that adder is verified, see table 3.
2) The connection between the preceding adder and the following adder is tested for correctness, i.e. whether the carry output cout (x) of the preceding adder is equal to the carry input CIN (x +1) of the following adder, and its truth table is shown in table 4.
The logic of the above decomposition method is to verify a system, and if the system can decompose several subsystems, the task can be decomposed to verify all subsystems and all connections between the subsystems.
Table 3: truth table of one-bit-band carry adder
Table 4: truth table of connecting line segment of two one-bit adders
| COUT(x) | CIN(x+1) |
| 0 | 0 |
| 1 | 1 |
The purpose of the above decomposition is to clarify all the items to be verified, without leaving omissions. When performing the verification of tables 3 and 4, it is not required to write different test cases to verify tables 3 and 4, respectively, as long as all the items of tables 3 and 4 can be covered to illustrate the integrity of the test.
The embodiment of the invention also provides a method for testing the carry chain constructed by the construction method, which is characterized in that the carry chain penetrates through a plurality of slices, each slice comprises a segment, and each segment comprises a plurality of primitives, wherein, in the step 1, the correctness of the primitives is judged; step 2, judging the correctness of the connection relation between every two adjacent primitives; and the step 1 and the step 2 adopt the test cases to judge the correctness.
According to an embodiment of the present invention, the method for determining correctness of the primitive in step 1 is as follows: the element and the LUT form a one-bit adder with carry, wherein the LUT is a truth table of exclusive-OR logic, and the input value is given according to the truth table to judge whether the actual output of the adder meets the expected output of the truth table of the one-bit carry adder; if so, the primitive is correct.
The method for judging the correctness of the connection relationship between every two adjacent primitives in the step 2 comprises the following steps: if the carry output of the previous primitive is equal to the carry input of the next primitive in real time and accords with the truth table of the connecting line segment of the two one-bit adders, the connection relation of every two adjacent primitives is correct.
The method includes covering a one-bit carry adder truth table and a connection line segment truth table of two one-bit adders with one or more test cases.
When the input of the addition end of the adder is 1 and the input of the carry end is 0 or when the input of the addition end of the adder is 0 and the input of the carry end is 1, the FPGA is configured to ensure that the primitives are not connected, single-primitive testing is adopted, and a plurality of test cases are needed.
And configuring the FPGA to connect two adjacent primitives on the carry chain, wherein the addition input ends of the current primitive are 0 and the carry end is 1, the addition input ends of the adjacent primitives are 1 and the carry end is 0, and then testing the carry chain by adopting a test case.
The following description will be made with reference to specific examples.
The testing method framework adopts the figure 7, and 3 large modules, a tested module, an excitation module and an evaluation module are constructed in the FPGA. The excitation module excites the module to be tested, and the evaluation module evaluates the output of the module to be tested and judges whether the test is passed or not. The excitation module and the evaluation module are constructed by slice, and the tested module is a slice carry chain. The same resource can not be both a tested module and other modules, and in order to ensure that the test is not missed, all carry chains must be tested by two configuration files, a part of slices are configured into carry chains by the first group of configuration, and other slices are configured into an excitation module and an evaluation module. And configuring another part of slice as a carry chain in the second group of configurations, and using the rest as an excitation module and an evaluation module. The coordinates of the measured carry chain may be specified by a position constraint.
The coverage of the truth table may employ a combination of chain and non-chain patterns, and both chain patterns.
In the combination of the chain mode and the non-chain mode, two cases are introduced.
The first case is to compile two test cases, the first one using the module under test as shown in FIG. 8, verifying Table 3 for all independent 1-bit adders. The second test case defines the module under test according to fig. 6, verifies that any two rows that can cause COUT to have values of 0 and 1, that is, any one row in table 5, rows 1,2, and 3 satisfies the condition that COUT is 0, and then any one row in table 5, rows 4,5, and 6 satisfies the condition that COUT is 1, which proves that both carry 0 and 1 can be transferred to the higher-order adder, that is, table 4 is covered.
Table 5: test case 1 input and expected output of a module under test
The second case is that two test cases are compiled, in the first test case, the defined tested resource is an n-bit carry adder, and n is a positive integer. This module has a total of 2n +1 inputs. The input end specifically comprises 1) n digits A; 2) n number of bits B; 3) the carry of the least significant bit is input to CIN 0. Verifying table 5 corresponds to verifying 1) each one-bit band-advance adder truth table 3 at lines 1 through 6. 2) The cascade relationship between each adjacent bit. I.e. the entire table 4. But the above tests do not include the tests of lines 7 and 8 of table 3.
To test rows 7 and 8 of table 3, which cannot be done with table 6, rows 1 and 2 of verification table 6 do not constitute rows 7 and 8 of verification table 3, table 6 row 1, all verified are a-1, B-1, and CIN-1 for all cells on the chain except for the least significant carry cell (i.e., row 4 of table 3), only for the least significant carry cell are verified are a-1, B-1, and CIN-0 (i.e., row 7 of table 3). Table 6, row 2, all primitives on the chain except the least significant carry primitive are verified as a-0, B-0 and CIN-0 (i.e., row 1 of table 3), and only for the least significant carry primitive is verified as a-0, B-0 and CIN-1 (i.e., row 8 of table 3).
Table 6: verification method not covering items 7 and 8 of table 3
Rows 7 and 8 of Table 3, in the second test case, the module under test is defined as a plurality of independent one-bit adders, such as FIG. 8, verifying rows 7 and 8 of Table 3.
The method of the chain mode is as follows: only one test case is written. The defined tested resource is an n-bit carry adder, and n is a positive integer. This module has a total of 2n +1 inputs. The input end specifically comprises 1) n digits A; 2) n number of bits B; 3) the carry of the least significant bit is input to CIN 0.
Given the inputs specified in tables 5 and 7 for a, B, and CIN0, respectively, it is verified whether the output of the module is the expected output, if so, the test case 1 test passes, otherwise, it does not. Verifying table 5, may cover rows 1 through 6 and the entire table 4 of table 3,
testing rows 7 and 8 of table 3 may be performed by verifying table 7. Line 1 of table 7 verifies line 8 of table 3 for all odd bits (bits 1, 3, 5 …, where bit 1 is the least significant bit) and line 7 of table 3 for all even bits (bits 2, 4, 6 …, where bit 2 is the next least significant bit). Line 2 of table 7 verifies line 7 of table 3 for all odd bits and line 8 of table 3 for all even bits.
Table 7: verification method capable of covering items 7 and 8 of table 3
And (3) defining a plurality of chains to be tested and processing the holes:
a large amount of resources exist in the FPGA, and multiple chains need to be tested simultaneously.
If the range of Slice in FPGA is integer between [0, xMax ] in x axis, and integer between [0, yMax ] in y axis. And the xMax and the yMax are integers which are the maximum values that can be obtained by slice on the x axis and the y axis respectively.
For the Slice hole phenomenon shown in FIG. 3, the strands must be broken, i.e., there are two strands in columns 2 and 3 and only 1 strand in columns 1, 4 and 5 of FIG. 3. In a specific implementation manner, a function f (x, y) is defined, wherein x is the abscissa of slice, and y is the ordinate of slice. When f (x, y) is 0, it indicates that there is no Slice at this position, i.e. there is no carry chain, and when the value of x or y is out of the range specified by the FPGA, f (x, y) is 0. For example, x-coordinate f (-1, -1) ═ 0. After the hole location information is obtained, f (x, y) can be defined. The method for defining a very hole process for a plurality of chains under test is as follows. The function f (x, y) is defined in a hardware description language, and the function value is calculated in an FPGA synthesis tool.
Starting from 0 or 1, taking the value of x as 2 step by step until reaching xMax, and executing the following steps for each value of x:
{
and y is taken as a value from 0 to 2 in a stepping mode until reaching yMax, and the following steps are executed for each value of y:
{
and if f (x, y-1) is 0 and f (x, y) is 1, establishing a carry chain by taking (x, y) of the coordinates as a carry segment of slice.
Otherwise, cascading the slice carry segment with the coordinate (x, y) to the slice carry segment with the coordinate (x, y-1).
}
}
As shown above, carry chains covering different positions are configured in two groups, and the column where the carry chain to be tested is located in the first group of configurations is a single-number column, so that x takes a value from 1. In the second set of configurations the column in which the carry chain to be tested is located is a double series, so that x starts at 0.
The invention has the beneficial effects that:
and the complex carry chain test is converted into the test of the connection relation between the carry primitive and the primitive. Under the condition of higher test efficiency, the test coverage rate of the carry chain is ensured to reach 100 percent.
It will be apparent to those skilled in the art that various changes and modifications may be made in the invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (10)
1. A method for constructing an FPGA carry chain with slice holes is characterized by comprising the following steps:
judging the current position as slice or cavity;
judging the previous position as slice or cavity;
according to the conditions of the current position and the previous position, carrying out new construction of a carry chain or cascade connection or neither new construction nor cascade connection;
all positions are traversed according to the method described above.
2. The method of claim 1, wherein when the current location is slice and the previous location is a hole, a new carry chain is performed.
3. The method of claim 1, wherein the concatenation is performed when a current location is slice and a previous location is slice.
4. The method of claim 1, wherein neither new nor concatenation is performed when a current location is a hole, a previous location is a slice, or a hole.
5. A method for testing a carry chain constructed by the construction method of any one of claims 1 to 4, wherein the carry chain with slice holes runs through a plurality of slices, each slice comprises a segment, each segment comprises a plurality of primitives, and in the step 1, the correctness of the primitives is judged; step 2, judging the correctness of the connection relation between every two adjacent primitives; and the step 1 and the step 2 adopt the test cases to judge the correctness.
6. The constructing method according to claim 5, wherein the method of judging the correctness of the primitive in the step 1 is: the element and the LUT form a one-bit adder with carry, wherein the LUT is a truth table of exclusive-OR logic, and the input value is given according to the truth table to judge whether the actual output of the adder meets the expected output of the truth table of the one-bit carry adder; if so, the primitive is correct.
7. The construction method according to claim 6, wherein the method of judging the correctness of the connection relationship between every two adjacent primitives in the step 2 is as follows: if the carry output of the previous primitive is equal to the carry input of the next primitive in real time and accords with the truth table of the connecting line segment of the two one-bit adders, the connection relation of every two adjacent primitives is correct.
8. The method of claim 7, wherein one or more test cases are used to override a one-bit carry adder truth table and a connection segment truth table for two one-bit adders.
9. The method of claim 8, wherein when the adder inputs are both 1 and the carry inputs are 0 or when the adder inputs are both 0 and the carry inputs are 1, the FPGA is configured to leave primitives unconnected and multiple test cases are required using single-primitive testing.
10. The method of claim 8, wherein the FPGA is configured to connect two primitives adjacent to each other on the carry chain, and the add input terminal of the current primitive is 0 and the carry terminal is 1, and the add input terminal of the primitive adjacent to the current primitive is 1 and the carry terminal is 0, then the carry chain is tested using one test case.
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| US5349250A (en) * | 1993-09-02 | 1994-09-20 | Xilinx, Inc. | Logic structure and circuit for fast carry |
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