CN111103732A

CN111103732A - Display panel mother board

Info

Publication number: CN111103732A
Application number: CN202010040306.5A
Authority: CN
Inventors: 曹武
Original assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Current assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date: 2020-01-15
Filing date: 2020-01-15
Publication date: 2020-05-05
Anticipated expiration: 2040-01-15
Also published as: CN111103732B

Abstract

The application provides a display panel master, this display panel master includes: the array substrate mother board is provided with a shielding electrode and a pixel electrode; the array substrate master plate further comprises a first alignment terminal, a second alignment terminal and a potential conversion circuit, the first alignment terminal is connected with the pixel electrode, the second alignment terminal is connected with the color film common electrode, meanwhile, the second alignment terminal is connected with the shielding electrode through the potential conversion circuit, and when the alignment is carried out, the potential conversion circuit enables a potential signal of the shielding electrode to be located between potential signals of the color film common electrode and the pixel electrode, so that a pretilt angle is formed for liquid crystal at the edge of the shielding electrode, and the problem that liquid crystal at the edge of the shielding electrode is limited in penetration is effectively relieved.

Description

Display panel mother board

Technical Field

The application relates to the field of display, in particular to a display panel master mask.

Background

In the traditional panel adopting a shielding electrode design, the common electrode is adopted to replace a black matrix for shading, so that the deviation problem of a color film substrate and an array substrate can be solved, and the panel is widely applied to the field of display. In the prior art, in the alignment process of a display panel master, all common electrodes are provided with uniform high positions, so that in the liquid crystal alignment, liquid crystals cannot form a pretilt angle, dark stripes can be formed in the display process, and the liquid crystal penetration rate is reduced.

Therefore, in the alignment process of the conventional display panel, the problem of limited liquid crystal penetration at the edge of the shielding electrode exists, and the problem is urgently needed to be alleviated.

Content of application

The embodiment of the application provides a display panel mother set, so as to alleviate the problem that the liquid crystal penetration at the edge of the existing shielding electrode is limited.

The application provides a display panel master, including: the color film substrate master comprises a plurality of color film substrates, and a color film common electrode is formed on each color film substrate; the array substrate mother set is arranged opposite to the color film substrate mother set and comprises a plurality of array substrates, and shielding electrodes and pixel electrodes are formed on the array substrates; a plurality of frames, the array substrate and the color film substrate enclose an accommodating space; the liquid crystal box is arranged between the color film substrate and the array substrate; in the cutting area, the array substrate mother board is further formed on a first alignment terminal, a second alignment terminal and a potential conversion circuit, the first alignment terminal is directly connected to the pixel electrode, the second alignment terminal is directly connected to the color film common electrode, and the second alignment terminal is connected to the shielding electrode through the potential conversion circuit; when the alignment is performed, the first alignment terminal is used for inputting a first potential signal to the pixel electrode, the second alignment terminal is used for inputting a second potential signal to the color film common electrode and the potential conversion circuit, the potential conversion circuit is used for converting the second potential signal into a third potential signal and then inputting the third potential signal to the shielding electrode, and the magnitude of the third potential signal is between the first potential signal and the second potential signal.

In some embodiments, the potential conversion circuit is provided with at least one TFT.

In some embodiments, the drain electrode of the TFT is connected to the shielding electrode, and the source electrode and the gate electrode of the TFT are connected to the color filter common electrode.

In some embodiments, the TFT is at least one of a low temperature polysilicon TFT and a metal oxide semiconductor TFT.

In some embodiments, a resistor is disposed on a path connecting the TFT source and the color film common electrode.

In some embodiments, the shielding electrode includes a first shielding electrode between the first sub-pixel and the second sub-pixel, a second shielding electrode between the second sub-pixel and the third sub-pixel, and a third shielding electrode; the third shielding electrode is positioned between the first sub-pixel and the third sub-pixel; the potential conversion circuit provides third potential signals with different magnitudes for the first shielding electrode, the second shielding electrode and the third shielding electrode respectively.

In some embodiments, a common electrode is further disposed on the array substrate in the display region of the array substrate, and the second alignment terminal is directly connected to the common electrode.

In some embodiments, the array substrate further forms an array common electrode, the array common electrode is connected to the color film common electrode through a conversion electrode, and the second alignment terminal is connected to the color film common electrode through the array common electrode.

In some embodiments, on the array substrate, a first metal layer forms the array common electrode, and a second metal layer forms the shared electrode.

In some embodiments, the switching electrode is disposed on the bezel.

The application provides a display panel master comprising: the array substrate mother board is provided with a shielding electrode and a pixel electrode; the array substrate master plate further comprises a first alignment terminal, a second alignment terminal and a potential conversion circuit, the first alignment terminal is connected with the pixel electrode, the second alignment terminal is connected with the color film common electrode, meanwhile, the second alignment terminal is connected with the shielding electrode through the potential conversion circuit, and when the alignment is carried out, the potential conversion circuit enables a potential signal of the shielding electrode to be located between potential signals of the color film common electrode and the pixel electrode, so that a pretilt angle is formed for liquid crystal at the edge of the shielding electrode, and the problem that liquid crystal at the edge of the shielding electrode is limited in penetration is effectively relieved.

Drawings

The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.

Fig. 1 is a schematic structural diagram of a display panel master provided in an embodiment of the present application.

Fig. 2 is a schematic structural diagram of a pixel unit in an array substrate in a display panel master provided in an embodiment of the present application.

Fig. 3 is a schematic circuit diagram of a pixel unit in an array substrate in a display panel master according to an embodiment of the present application.

Fig. 4 is a schematic view of an alignment circuit in a display panel master provided in an embodiment of the present application.

Fig. 5 is a schematic diagram of a potential conversion circuit in a display panel master provided in an embodiment of the present application.

Fig. 6 is a schematic diagram of voltages applied to the display panel according to the embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the description of the present application, it is to be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present application and for simplicity in description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated in a particular manner, and are not to be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.

In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.

In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise direct contact of the first and second features, or may comprise contact of the first and second features not directly but through another feature in between. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.

The following disclosure provides many different embodiments or examples for implementing different features of the application. In order to simplify the disclosure of the present application, specific example components and arrangements are described below. Of course, they are merely examples and are not intended to limit the present application. Moreover, the present application may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, examples of various specific processes and materials are provided herein, but one of ordinary skill in the art may recognize applications of other processes and/or use of other materials.

Specifically, referring to fig. 1 to 6, in the embodiment of the present application, a display panel mother substrate is provided, and a voltage between a pixel electrode and an array electrode is applied to a shielding electrode by adding a potential conversion circuit, so as to alleviate the problems of low liquid crystal efficiency and limited penetration at the boundary of the shielding electrode.

As shown in fig. 1, the display panel mother set includes an array substrate mother set 100, a color film substrate mother set 200 disposed opposite to the array substrate mother set 100, a frame 400 connecting the array substrate mother set 100 and the color film substrate mother set 200, and a liquid crystal cell 300 disposed between the array substrate mother set 100 and the color film substrate mother set 200; the array substrate master 100 comprises a shielding electrode 110, a pixel electrode 120, an array common electrode 130, a shared electrode 140 and a pixel unit 150; wherein: the shielding electrode 110 includes a first shielding electrode, a second shielding electrode, and a third shielding electrode; the pixel unit 150 includes a first sub-pixel 151, a second sub-pixel 152, and a third sub-pixel 153; the color film substrate master 200 comprises a color film common electrode 210, and the color film common electrode 210 is arranged opposite to the shielding electrode 110 and the pixel electrode 120; the bezel 400 includes a switching electrode 410, and the switching electrode 410 is connected to the common electrode 130.

The array substrate master 100 comprises a substrate, an active layer, a first insulating layer, a first metal layer, a second insulating layer, a second metal layer, an interlayer dielectric layer, a source drain layer, a planarization layer and a pixel electrode layer which are stacked from bottom to top.

The substrate is usually a rigid substrate such as glass, transparent resin, etc., but may also be a flexible substrate such as polyimide, and the structure of the substrate is not limited in this application. The buffer layer is formed on one side of the substrate, and the material of the buffer layer can be inorganic material such as silicon oxide, silicon nitride and the like. The active layer is formed on the buffer layer, and the material of the active layer is a metal oxide, such as Indium Gallium Zinc Oxide (IGZO), but not limited thereto, and may be one or more of Aluminum Zinc Oxide (AZO), Indium Zinc Oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), boron-doped zinc oxide (BZO), and magnesium-doped zinc oxide (MZO). In addition, the active layer may also be a polysilicon material or other materials. The first gate insulating layer is formed on the active layer, and the gate insulating layer may be made of inorganic materials such as silicon oxide and silicon nitride.

The first metal layer is formed on the first insulating layer, and the material of the first metal layer may be molybdenum, aluminum, copper, chromium, tungsten, titanium, tantalum, and alloys containing these materials, and the material thereof is not particularly limited. As shown in fig. 1, the first metal layer is patterned through an etching process to form the array common electrode 130 and the scan lines 160.

The second gate insulating layer is formed on the first metal layer, and may be made of inorganic material such as silicon oxide, silicon nitride, etc., and may be made of the same material or different material from the first gate insulating layer.

The second metal layer is formed on the second insulating layer, and the material of the second metal layer may be molybdenum, aluminum, copper, chromium, tungsten, titanium, tantalum, and alloys containing these materials, and the material thereof is not particularly limited. The second metal layer is patterned to form the common electrode 140, and the overlapping portion of the array common electrode 130 and the common electrode 140 may form a storage capacitor.

The interlayer dielectric layer is formed on the second metal layer, and the interlayer dielectric layer can be made of inorganic materials such as silicon oxide or silicon nitride.

The source and drain layer is formed on the interlayer dielectric layer, and the source and drain layer can be made of molybdenum, aluminum and copper, but not limited to molybdenum, tungsten, titanium, tantalum, alloys containing chromium, tungsten, titanium and tantalum, and the like; and the source and drain electrode layers are patterned by an etching process to form a source electrode and a drain electrode of each thin film transistor, a data line and a shared electrode line.

The planarization layer is formed on the source drain layer and is formed on the source drain layer in a coating mode.

The pixel electrode layer is formed on the planarization layer and is connected with the source and drain layers through the via hole. As shown in fig. 1, the pixel electrode layer is patterned to form a shielding electrode 110 and a pixel electrode 120.

The array substrate further includes a plurality of pixels, and the plurality of pixels are distributed in an array and driven by the scan lines 160 and the data lines to perform display. Each pixel includes a first sub-pixel 151, a second sub-pixel 152, and a third sub-pixel 153, in this application, the first sub-pixel 151 is a red sub-pixel, the second sub-pixel 152 is a green sub-pixel, and the third sub-pixel 173 is a blue sub-pixel. R represents a red sub-pixel, G represents a green sub-pixel, and B represents a blue sub-pixel, and in the same row of pixels, the arrangement of the sub-pixels is "rgbrgb.", respectively, wherein the sub-pixels in each row of pixels are connected to the same scan line 160. The sub-pixels in the same column are of the same kind, and each column of sub-pixels is respectively connected to the data lines adjacent to the left and right of the column of sub-pixels. When each sub-pixel needs to display, the scanning line 150 scans line by line, controls each pixel to be opened line by line, and inputs signals through the data line, so that each column of pixels emits light for display.

In the display area, the frame 400 is arranged on the array substrate master 100 in a surrounding manner, the array substrate master 100 is connected with the color film substrate master 200 through the frame 400, and the frame 400 comprises a conversion frame adhesive; the frame glue is filled with glass fiber, silicon balls, plastic balls, silicon balls and gold balls; the gold ball forms the conversion electrode 410, the base material of the gold ball is a resin ball, a layer of metal nickel is included outside the resin ball, and a layer of metal gold is wrapped to form the gold ball; the gold ball realizes the communication between the color film common electrode and the array common electrode in a transfer printing and silver paste dripping mode.

In the cutting area, the array substrate mother substrate is further formed on a first alignment terminal, a second alignment terminal and a potential conversion circuit, as shown in fig. 1, the first alignment terminal is directly connected to the pixel electrode 120, the second alignment terminal is directly connected to the color film common electrode 210, and is simultaneously connected to the shielding electrode 110 through the potential conversion circuit; when performing alignment, the first alignment terminal is used to input a first potential signal to the pixel electrode 120, the second alignment terminal is used to input a second potential signal to the color film common electrode 210 and the potential conversion circuit, the potential conversion circuit is used to convert the second potential signal into a third potential signal, and then input the third potential signal to the shielding electrode 110, and the magnitude of the third potential signal is between the first potential signal and the second potential signal.

As shown in fig. 2, the array substrate includes a plurality of scan lines 160 and a plurality of data lines 170 perpendicularly crossing each other, a plurality of array common electrode lines 130 disposed adjacent to the plurality of data lines 170, and sub-pixel units 150 defined by the plurality of scan lines 160 and data lines 170, each of the pixel units 150 including a sub-pixel region and a sub-pixel region.

The first sub-pixel 151 includes a main pixel region and an auxiliary pixel region, as shown in fig. 2, the main pixel region is a region above the scan line 160, the auxiliary pixel region is a region below the scan line 160, the pixel electrode 120 includes a main pixel electrode 121 located in the main pixel region and a slave pixel electrode 122 located in the slave pixel region, and the array common electrode 130 includes a first gate common electrode 131 located in the main pixel region and a second gate common electrode 132 located in the slave pixel region; each part of the pixel comprises a main part in a cross shape and a branch part connected with the main part, each part of the pixel electrode 120 is divided into four display domains by the main part, and the two parts of the main pixel area and the auxiliary pixel area comprise eight display domains.

As shown in fig. 3, the main pixel region includes a main thin film transistor T1, a main pixel electrode 121, and a first array common electrode 131. The gate of the main thin film transistor T1 is connected to the scan line 160, the source of the main thin film transistor T1 is connected to the data line 170, and the drain of the main thin film transistor T1 is connected to the main pixel electrode 121.

A first liquid crystal capacitor is formed between the main pixel electrode 121 and the color filter common electrode 210 in the color filter substrate 200.

The slave pixel region includes a slave thin film transistor T2, a shared thin film transistor T3, and a slave pixel electrode 122. The gate of the slave thin film transistor T2 is connected to the scan line 160, the source of the slave thin film transistor T2 is connected to the data line 170, the drain of the slave thin film transistor T2 is connected to the pixel electrode 122 and the source of the shared thin film transistor T3, the gate of the shared thin film transistor T3 is connected to the scan line 160, and the drain of the shared thin film transistor T3 is connected to the array common electrode 130.

A second liquid crystal capacitor is formed between the pixel electrode 122 and the common electrode layer 210 in the color filter substrate.

In the present embodiment, the master pixel region and the slave pixel region each correspond to liquid crystal molecules of four domains. In other embodiments, the master pixel region and the slave pixel region may also each correspond to liquid crystal molecules of a plurality of domains other than four domains.

In the embodiment of the present application, the scan line 160 controls the display of the sub-pixels in the main pixel region and the sub-pixel region through the main thin film transistor T1, the sharing electrode 140 controls the sub-pixels in the sub-pixel region through the sharing thin film transistor T3, the main pixel electrode 121, the sub-pixel electrode 122, and the sharing electrode 140 are connected to the data line 170 through the main thin film transistor T1, the sub-thin film transistor T2, and the sharing transistor T3, and are connected to the electrical signals of the same bit, and at the same time, the sharing electrode 140 leaks the electrical current to the sub-pixels in the main pixel region.

The array common electrode 120 is formed in a first metal layer, the first common electrode 121 is formed in the main pixel region, the second common electrode 122 is formed in the sub-pixel region, and the shielding electrode 110 is formed in a second metal layer for shielding a lateral electric field in the array substrate. In general, a lateral electric field is generated between the pixel electrode 120 and the data line 170, between the pixel electrode 120 and the scan line 160, and between the pixel electrodes 120 of the pixels in the adjacent rows, so that the shielding electrode 110 is required. In addition, a shielding electrode 110 is generally disposed between the common electrode line 140 and the active layer.

In some embodiments, a portion of the overlap between the first metal layer and the second metal layer may form a storage capacitor, wherein the first storage capacitor 191 is formed in the main pixel region, the first electrode plate of the first storage capacitor 191 is formed on the first metal layer, and the second electrode plate of the first storage capacitor 191 is formed on the second metal layer; the second storage capacitor 192 is formed in the sub-pixel region, the first electrode plate of the second storage capacitor 192 is formed on the first metal layer, and the second electrode plate of the first storage capacitor 192 is formed on the second metal layer.

Fig. 4 is a schematic view of an alignment circuit in a display panel master provided in an embodiment of the present application;

as shown in fig. 4, the display panel master is divided into a cutting area a1 and an alignment area a 2; in the alignment area A2, an alignment interface corresponding to the metal probe on the alignment jig is formed; within cutting zone a 1; the array substrate is formed with a first alignment terminal, a second alignment terminal and a potential conversion circuit, the first alignment terminal is directly connected to the pixel electrode 120, the second alignment terminal is directly connected to the color film common electrode 210, and is simultaneously connected to the shielding electrode 110 through the potential conversion circuit; when performing alignment, the first alignment terminal is configured to input a first potential signal to the pixel electrode 120, the second alignment terminal is configured to input a second potential signal to the color film common electrode 210 and the potential conversion circuit, the potential conversion circuit is configured to convert the second potential signal into a third potential signal and input the third potential signal to the shielding electrode 110, and the magnitude of the third potential signal is between the first potential signal and the second potential signal.

Fig. 5 is a potential conversion circuit according to an embodiment of the present application.

In the embodiment of the application, in the alignment area a1, one path of the array common electrode line, the shared electrode line, the color film common electrode line and the potential conversion circuit is converged to be pricked with an equal potential electrical signal on the same gold needle through the second terminal, and the pixel electrode line is connected to the first potential signal through the first terminal; within cutting zone a 2; the shield electrode line is connected to the potential conversion circuit through the driving thin film transistor T4.

In the embodiment of the present application, when the mother panel of the display panel is aligned, the array common electrode lines, the shielding electrode lines and the shared electrode lines are controlled to input the same voltage, and the main thin film transistor T1, the slave thin film transistor T2, the shared thin film transistor T3 and the driving thin film transistor T4 all have the same voltage. Since the driving thin film transistor T4 is provided with a certain large resistance R on the path of connection, the electric signal of the shield electrode connection is between the array common electrode 130 and the pixel electrode 120.

In some embodiments, a resistor R is disposed on a path connecting the source of the driving thin film transistor T4 and the color film common electrode 210; the size of the resistor R can be adjusted according to the requirement.

In some embodiments, the magnitude of the third signal received by the shielding electrode 110 is 70 to 80 percent of the magnitude of the second signal received by the array common electrode.

Fig. 6 is a schematic diagram of voltages applied during a mother panel alignment process of the display panel of the present application, and the alignment process is further described with reference to fig. 6.

As shown in fig. 6, when the display panel master is aligned, a first signal is applied to the pixel electrode 120; when the second signal is applied to the data line 160, the main thin film transistor T1, the slave thin film transistor T2, and the shared thin film transistor T3 are connected to the data line 170, so that the voltages of the color film common electrode 210, the shared electrode 140, and the array common electrode 130 are the same.

In the embodiment of the present application, since the shielding electrode line is connected to the common electrode line through the via hole and the driving thin film transistor T4 and the specific resistor are disposed on the path, the third signal received by the shielding electrode line is smaller than the second signal, and the magnitude of the second potential signal is reduced to 70 to 80 percent, so as to obtain the third potential signal.

In the embodiment of the present application, the pixel electrode is separately connected to a first signal, the first signal is a low voltage, and a third signal is between the first signal and a second signal, and the third potential signal is obtained when the magnitude of the second potential signal is reduced to 70 to 80 percent. When the shielding electrode is connected with the third signal, the liquid crystal deflection effect at the edge of the shielding electrode is the best, and the deflection angle of the liquid crystal is 90 degrees at the moment, so that the penetration rate of the liquid crystal at the edge of the shielding electrode 100 is effectively improved.

In some embodiments, after the liquid crystal is deflected, the liquid crystal needs to be cured, after the curing, the mother plate of the display panel is cut, the collection of the electrode lines is removed, the common electrode 210 and the shielding electrode 110 of the color film substrate are completely independent, and different driving circuits are attached.

According to the above embodiment:

In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

The display panel master provided by the embodiment of the present application is described in detail above, and a specific example is applied in the description to explain the principle and the implementation of the present application, and the description of the above embodiment is only used to help understand the technical solution and the core idea of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.

Claims

1. A display panel master, comprising:

the color film substrate master comprises a plurality of color film substrates, and a color film common electrode is formed on each color film substrate;

the array substrate mother set is arranged opposite to the color film substrate mother set and comprises a plurality of array substrates, and shielding electrodes and pixel electrodes are formed on the array substrates;

a plurality of frames, the array substrate and the color film substrate enclose an accommodating space;

the liquid crystal box is arranged between the color film substrate and the array substrate;

in the cutting area, a first alignment terminal, a second alignment terminal and a potential conversion circuit are further formed on the array substrate, the first alignment terminal is directly connected to the pixel electrode, the second alignment terminal is directly connected to the color film common electrode, and the second alignment terminal is connected to the shielding electrode through the potential conversion circuit; when the alignment is performed, the first alignment terminal is used for inputting a first potential signal to the pixel electrode, the second alignment terminal is used for inputting a second potential signal to the color film common electrode and the potential conversion circuit, the potential conversion circuit is used for converting the second potential signal into a third potential signal and then inputting the third potential signal to the shielding electrode, and the magnitude of the third potential signal is between the first potential signal and the second potential signal.

2. The display panel master of claim 1, wherein the potential conversion circuit is provided with at least one TFT.

3. The display panel master of claim 2, wherein the drain electrode of the TFT is connected to the shielding electrode, and the source electrode and the gate electrode of the TFT are connected to the color film common electrode.

4. The display panel master of claim 2, wherein the TFT is at least one of a low temperature polysilicon TFT and a metal oxide semiconductor TFT.

5. The display panel master of claim 3, wherein a resistor is arranged on a path connecting the TFT source electrode and the color film common electrode.

6. The display panel master of claim 1, the shielding electrode comprising a first shielding electrode, a second shielding electrode, and a third shielding electrode, the first shielding electrode being located between the first sub-pixel and the second sub-pixel, the second shielding electrode being located between the second sub-pixel and the third sub-pixel; the third shielding electrode is positioned between the first sub-pixel and the third sub-pixel; the potential conversion circuit provides third potential signals with different magnitudes for the first shielding electrode, the second shielding electrode and the third shielding electrode respectively.

7. The display panel master of claim 1, wherein the array substrate is further provided with a shared electrode thereon, and the second alignment terminal is directly connected to the shared electrode.

8. The display panel master of claim 7, wherein the array substrate further forms an array common electrode, the array common electrode is connected to the color film common electrode through a conversion electrode, and the second alignment terminal is connected to the color film common electrode through the array common electrode.

9. The display panel master of claim 8, wherein a first metal layer forms the array common electrode and a second metal layer forms the shared electrode on the array substrate.

10. The display panel master of claim 8, wherein the switching electrodes are disposed on the bezel.