CN111091773A

CN111091773A - Display panel and display device

Info

Publication number: CN111091773A
Application number: CN202010024688.2A
Authority: CN
Inventors: 奚苏萍
Original assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Current assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date: 2020-01-10
Filing date: 2020-01-10
Publication date: 2020-05-01

Abstract

The invention provides a display panel and a display device. The display panel comprises pixels, a multi-level gate driving circuit and a level mark. The pixels comprise effective pixels and virtual pixels, and the hierarchy mark is arranged above the virtual pixels.

Description

Display panel and display device

Technical Field

The invention relates to the field of display equipment, in particular to a display panel and a display device.

Background

A Gate Driver On Array (GOA) circuit, i.e., a Gate line scan driving signal is fabricated On an Array substrate to realize a driving method of scanning a Gate line by line.

In the conventional GOA circuit design, the output grid wire can stride over the common wire and then is connected to the display area through the via hole, the number of the corresponding grid wire is conveniently positioned and checked by people in engineering sections, the number and the arrow representing the number of the corresponding grid wire are marked beside the common wire, and the marking mode occupies the space of the common wire. To solve this problem, it is common practice to mark arrows and numbers beside the cut line, so that although space is made available for common routing, the marked numbers are too far from the display area to be useful for positioning people in the engineering section. It is also known to place the marks above the common lines, but this can interfere with the capacitance of the common lines, affecting their stability.

Disclosure of Invention

The invention aims to provide a display panel and a display device, and aims to solve the problems that the hierarchical marks of a GOA circuit in the prior art occupy the space of common electrode wiring, interfere with the capacitance of the common electrode wiring, influence the stability and the like.

To achieve the above object, the present invention provides a display panel having a display area and a non-display area connected to surround the display area. The display panel comprises pixels, a multi-level gate driving circuit and a level mark.

The pixel array is arranged in the display area. The multi-level gate driving circuit is arranged in the non-display area, and the gate driving circuit of each level is electrically connected to the corresponding pixel. The level mark is arranged above the pixel and is used for marking the level of the gate drive circuit.

Furthermore, the display panel further comprises a common electrode driving circuit, and the common electrode driving circuit is arranged in the non-display area and is positioned between the gate driving circuit and the display area.

Further, the pixels comprise virtual pixels and effective pixels, and the virtual pixels are arranged at the edge of the display area. The level mark is arranged above the virtual pixel.

Furthermore, the display panel further comprises a thin film transistor, and the thin film transistor is arranged in the display area and is positioned between two adjacent pixels.

Further, each pixel has a pixel electrode, wherein the pixel electrode of the effective pixel is connected with the thin film transistor.

Furthermore, the gate driving circuit comprises a gate scanning line which is insulated above the common driving circuit and is connected with the gate driving circuit and the thin film transistor.

Further, the level mark is located at the same level as the gate driving circuit.

Further, the level mark is located at the same level as the common electrode driving circuit.

Further, the hierarchical indicia may be one or more of numbers, letters, and symbols.

The invention also provides a display device, which comprises the display panel.

The invention has the advantages that: according to the display panel, the level marks are arranged on the virtual pixels, so that more non-display area spaces are saved while display is not influenced, the common electrode driving circuit is widened, the level marks are prevented from interfering with the storage capacitor of the common electrode driving circuit, and the stability of the common electrode driving circuit is improved.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1 is a front view of a display face in an embodiment of the invention.

The components in the figures are represented as follows:

a display panel 100;

a display area 101; a non-display area 102;

a pixel 10; a virtual pixel 11;

an effective pixel 12; a pixel electrode 13;

a thin film transistor 20; a gate drive circuit 30;

gate scanning lines 31; a common electrode drive circuit 40;

the hierarchy is labeled 50.

Detailed Description

Reference will now be made in detail to embodiments of the present application, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative and are only for the purpose of explaining the present application and are not to be construed as limiting the present application.

In the description of the present application, it is to be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present application and for simplicity in description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated in a particular manner, and are not to be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.

In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.

In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise direct contact of the first and second features, or may comprise contact of the first and second features not directly but through another feature in between. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.

The following disclosure provides many different embodiments or examples for implementing different features of the application. In order to simplify the disclosure of the present application, specific example components and arrangements are described below. Of course, they are merely examples and are not intended to limit the present application. Moreover, the present application may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, examples of various specific processes and materials are provided herein, but one of ordinary skill in the art may recognize applications of other processes and/or use of other materials.

In an embodiment of the present invention, a display panel 100 is provided, as shown in fig. 1, the display panel 100 includes a display area 101 and a non-display area 102 connected around the display area 101. Within the display area 101, the display panel 100 has a number of pixels 10, thin film transistors 20, and level marks 50. In the non-display region 102, the display panel 100 includes a gate driving circuit 30 and a common electrode driving circuit 40.

The pixel 10 array is arranged in the display area 101 of the display panel 100, and includes dummy pixels 11 and effective pixels 12. The effective pixels 12 are arranged in the display area 101 in an array, the effective pixels 12 may include a red sub-pixel 10, a green sub-pixel 10, and a blue sub-pixel 10, and each effective pixel 12 may emit corresponding red light, green light, and blue light during operation, so as to implement color display. The effective pixels 12 are arranged at the edge of the display area 101 of the display panel 100, and the effective pixels 12 are time-division copied by using the persistence of vision of human eyes to reproduce more display information points, so that the definition and the resolution of the display panel 100 are improved.

The pixel 10 further has a pixel electrode 13, the pixel 10 is connected to the thin film transistor 20 through the pixel electrode 13, and the thin film transistor 20 is configured to drive each pixel 10, transmit electric energy into the pixel 10 through the pixel electrode 13, and excite the pixel 10 to emit light. The thin film transistor 20 is disposed between two adjacent pixels 10. The pixel electrode 13 of the effective pixel 12 is electrically connected to all the thin film transistors 20, and the pixel electrode 13 of the dummy pixel 11 is not electrically connected to the thin film transistors 20, so that the dummy pixel 11 does not emit light.

The gate driving circuit 30 is disposed in the non-display region 102 of the display panel 100, and is a multi-level gate driving circuit 30 having a plurality of gate scan lines 31. The common electrode driving circuit 40 is disposed in the non-display region 102 and between the gate driving circuit 30 and the display region 101. The common electrode driving circuit 40 forms a storage capacitor with the pixel electrode 13 through a common electrode trace. The gate scan line 31 crosses the common electrode driving circuit 40 in an insulated manner, and is connected to the thin film transistor 20 in the display area 101 through a connecting hole to provide a gate driving signal for the thin film transistor 20. The level mark 50 is provided on the dummy pixel 11, so that the space in the non-display region 102 can be saved for widening the common electrode driving circuit 40 and increasing the stability of the common electrode driving circuit 40 without affecting the display.

The level mark 50 is provided on the dummy pixel 11 of the display area 101, and the dummy pixel 11 does not have a light emitting display function, and therefore does not affect the display of the display area 101. The level mark 50 is used for marking the level of the gate driving circuit 30, i.e. the level number of the gate scanning lines 31, so as to facilitate the positioning and factory building of workers in subsequent engineering sections. The level marking 50 may be one or more of a number, a letter, and a symbol. As shown in fig. 1, in the embodiment of the present invention, the level mark 50 is "565 →", which means that the gate scan line 31 is the 565 th level gate scan line.

In the embodiment of the present invention, the level mark 50 may be etched and prepared simultaneously with the common electrode driving circuit 40 and located at the same layer as the common electrode driving circuit 40, and the level mark 50 does not need to increase the preparation distance of the display panel 100 and increase the number of processes. In other embodiments of the present invention, the level mark 50 may also be formed by etching at the same time as the gate driving circuit 30, and is located at the same layer as the gate driving circuit 30, and the effect is the same as that in the embodiments of the present invention, which is not described herein in detail.

The embodiment of the present invention further provides a display device, where the display device includes the display panel 100, and the display device may be various electronic products or components with a display function, such as a mobile phone, a notebook computer, a tablet computer, and the like.

In the display panel 100 provided in the embodiment of the present invention, the hierarchical mark 50 is disposed on the virtual pixel 11 of the display area 101, and the hierarchical mark 50 is transferred into the display area 101 from the side of the common electrode driving circuit 40 in the prior art while the display of the display area 101 is not affected, so that a space beside the common electrode driving circuit 40 is saved for thickening the common electrode driving circuit 40, and the stability of the common electrode driving circuit 40 is improved.

Although the invention herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present invention. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims. It should be understood that features described in different dependent claims and herein may be combined in ways different from those described in the original claims. It is also to be understood that features described in connection with individual embodiments may be used in other described embodiments.

Claims

1. A display panel is characterized by comprising a display area and a non-display area connected with the surrounding display area;

the display panel includes:

the pixels are arranged in the display area in an array mode;

the multi-level gate driving circuit is arranged in the non-display area, and the gate driving circuit of each level is electrically connected to the corresponding pixel;

the level mark is used for marking the level of the gate driving circuit and is arranged above the pixel.

2. The display panel of claim 1, further comprising:

and the common electrode driving circuit is arranged in the non-display area and is positioned between the grid electrode driving circuit and the display area.

3. The display panel according to claim 1, wherein the pixels include dummy pixels and effective pixels, the dummy pixels being arranged at edges of the display area; the level mark is arranged above the virtual pixel.

4. The display panel according to claim 3, further comprising a thin film transistor provided in the display region and between two adjacent pixels.

5. The display panel of claim 4, wherein each pixel has a pixel electrode, and wherein the pixel electrode of the active pixel is connected to the thin film transistor.

6. The display panel according to claim 4, wherein the gate driver circuit includes a gate scan line which is provided over the common driver circuit in an insulated manner and connects the gate driver circuit and the thin film transistor.

7. The display panel of claim 1, wherein the level mark is located at the same level as the gate driving circuit.

8. The display panel according to claim 2, wherein the level mark is located at the same level as the common electrode driving circuit.

9. The display panel of claim 1, wherein the hierarchical indicia can be one or more of numbers, letters, and symbols.

10. A display device characterized by comprising the display panel according to any one of claims 1 to 9.