CN111083549B

CN111083549B - Video switching method and device and display control equipment

Info

Publication number: CN111083549B
Application number: CN201811224604.9A
Authority: CN
Inventors: 王新成
Original assignee: Zhejiang Uniview Technologies Co Ltd
Current assignee: Zhejiang Uniview Technologies Co Ltd
Priority date: 2018-10-19
Filing date: 2018-10-19
Publication date: 2021-09-28
Anticipated expiration: 2038-10-19
Also published as: CN111083549A

Abstract

The embodiment of the invention provides a video switching method, a video switching device and a display control device.A main control board of the display control device is used for storing a frame of image and setting a first frame mark on a receiving DSP (digital signal processor) by configuring a non-effective window eliminating parameter on a target first FPGA (field programmable gate array) and a non-effective window opening parameter on a second FPGA, and sending the frame of image with the first frame mark to the target first FPGA and the second FPGA to enable the non-effective window eliminating parameter configured on the target first FPGA and the non-effective window opening parameter configured on the second FPGA to take effect. Therefore, before a new video stream arrives, the last frame of image of the target first window is continuously displayed for the user, and the problem of poor user experience caused by long-time screen blacking in the display scene switching process is solved.

Description

Video switching method and device and display control equipment

Technical Field

The invention relates to the technical field of display, in particular to a video switching method and device and display control equipment.

Background

The video comprehensive platform is widely applied to the fields of security monitoring, commanding, emergency scheduling and the like, and can provide comprehensive application of access, management, storage, large-screen display and the like of monitoring images, conference terminal images and the like.

In the related art, a video integration platform generally employs a display control device to control a video wall including a plurality of physical screens to display. In practical applications, it is referred to the case of switching from one display scene to another, wherein one display scene comprises at least one window for displaying a video stream. During the scene switching, there are the following situations: due to network delay and other reasons, when a window in an old display scene is destroyed and a new window in a new display scene is built, a video stream required to be displayed in the new display scene does not arrive, and at this time, the whole television wall is in a black screen state (also called as "black brushing"). The above situation results in a very poor user experience.

Disclosure of Invention

In order to at least partially overcome the above-mentioned deficiencies in the prior art, the present invention aims to provide a video switching method, which is applied to a main control board of a display control device, wherein the display control device further comprises at least one DSP and at least one FPGA connected to the main control board; the FPGA is connected with at least one physical screen in the splicing display equipment; the method comprises the following steps:

receiving a switching instruction, wherein the switching instruction is used for indicating switching from a first display scene comprising a first window to a second display scene comprising a second window;

determining a second FPGA for controlling the second window, and configuring non-effective windowing parameters for the second window on the second FPGA;

determining a target first window corresponding to the second window in the first display scene;

determining a target first FPGA for controlling the target first window, and configuring non-effective window elimination parameters for the target first window on the target first FPGA;

determining a receiving DSP corresponding to the target first window, and controlling the receiving DSP to stop sending the received video stream to the target first FPGA;

controlling the receiving DSP to acquire a frame of image from the cache region, setting a first frame mark for the frame of image, and acquiring and storing a target image;

and controlling the receiving DSP to respectively send the target image to the target first FPGA and the second FPGA, so that the non-effective window-removing parameters configured on the target first FPGA and the non-effective window-opening parameters configured on the second FPGA take effect.

The invention also aims to provide a video switching device which is applied to a main control board of a display control device, wherein the display control device further comprises at least one DSP and at least one FPGA which are connected with the main control board; the FPGA is connected with at least one physical screen in the splicing display equipment; the device comprises:

a switching instruction receiving module, configured to receive a switching instruction, where the switching instruction is used to instruct to switch from a first display scene including a first window to a second display scene including a second window;

the windowing parameter configuration module is used for determining a second FPGA for controlling the second window and configuring non-effective windowing parameters for the second window on the second FPGA;

a window determination module, configured to determine a target first window corresponding to the second window in the first display scene;

the window elimination parameter configuration module is used for determining a target first FPGA for controlling the target first window and configuring non-effective window elimination parameters for the target first window on the target first FPGA;

the first control module is used for determining a receiving DSP corresponding to the target first window and controlling the receiving DSP to stop sending the received video stream to the target first FPGA;

the second control module is used for controlling the receiving DSP to acquire a frame of image from the cache region, setting a first frame mark for the frame of image, and acquiring and storing a target image;

and the third control module is used for controlling the receiving DSP to respectively send the target image to the target first FPGA and the second FPGA so as to enable the non-effective window-removing parameters configured on the target first FPGA and the non-effective window-opening parameters configured on the second FPGA to be effective.

The invention also aims to provide display control equipment which comprises a main control board, and at least one DSP and at least one FPGA which are connected with the main control board; the FPGA is connected with at least one physical screen in the splicing display equipment;

the main control board switches videos by the method of the embodiment of the invention.

Compared with the prior art, the embodiment of the invention has the beneficial effects that:

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.

Fig. 1 is a schematic structural diagram of a display control apparatus according to an embodiment of the present invention;

fig. 2 is a schematic flowchart of a video switching method according to an embodiment of the present invention;

FIG. 3 is a flowchart illustrating the sub-steps of step S170 in FIG. 2;

fig. 4 is a block diagram of a video switching apparatus according to an embodiment of the present invention;

fig. 5 is a schematic structural diagram of a main control board according to an embodiment of the present invention.

Icon: 10-a display control device; 100-a main control board; 11-a processor; 12-a machine-readable storage medium; 20-a tiled display device; 201. 202, 203-DSP; 210. 220, 230-service board; 250-PCIE switching board; 301. 302, 303-FPGA; 400-video switching means; 401. 402, 403-physical screen; 410-a switch instruction receiving module; 420-windowing parameter configuration module; 430-a window determination module; 440-a window-removal parameter configuration module; 450-a first control module; 460-a second control module; 470-third control module.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.

Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.

Fig. 1 is a schematic structural diagram of a display control apparatus 10 according to an embodiment of the present invention. The display control device 10 includes a main control board 100, and at least one Digital Signal Processor (DSP) and at least one Field-Programmable Gate Array (FPGA) connected to the main control board 100. For example, the at least one DSP may be the DSP201, the DSP202, and the DSP203 shown in fig. 2, and the at least one FPGA may be the FPGA301, the FPGA302, and the FPGA303 shown in fig. 2. Alternatively, the DSPs and the FPGAs in this embodiment may have a one-to-one correspondence relationship, and the DSPs and the FPGAs corresponding to each other may be disposed on the same service board, for example, the DSP201 and the FPGA301 illustrated in fig. 2 are disposed on the service board 210, the DSP202 and the FPGA302 are disposed on the service board 220, and the DSP203 and the FPGA303 are disposed on the service board 230.

It should be noted that, the structure that three DSPs and three FPGAs are shown in fig. 1 is only an illustration, and the embodiment of the present invention does not limit the number of the DSPs and the FPGAs.

The DSP is used for receiving the video stream, decoding, cutting, scaling and the like, and sending the processed video stream to the FPGA. For each video stream to be displayed, the main control board 100 selects a DSP, i.e. a receiving DSP described below, to receive the video stream and process the video stream according to a certain rule. For example, the main control board 100 may select a DSP with a processing capability matching a processing requirement of a video stream to be displayed as a receiving DSP of the video stream according to the processing requirement.

Each FPGA in the display control device 10 is connected to the tiled display device 20. Wherein the tiled display device 20 is tiled from a plurality of physical screens, such as a tv wall that can be nxm (e.g., the combination of 1 x 3 shown in fig. 1), etc. Each FPGA is connected to at least one physical screen of the tiled display device 20, and fig. 1 shows a case where each FPGA is connected to one physical screen.

In practical applications, a user may configure related instructions on the display control device 10 to create a window at a specified position on the tiled display device 20 and display a specified video stream in the created window.

Generally, the related instructions, which include the size and position of the window, the video stream displayed by the window, the image resolution of the displayed content of the window, etc., will be configured on the main control board 100 of the display control device 10, and the main control board 100 issues the related parameters (i.e., the size, the position, the displayed video stream, the image resolution, etc.) of the window to the FPGA according to the related instructions.

Meanwhile, the main control board 100 may also determine the physical screen where the window is located according to the position in the relevant parameter, and further determine the FPGA corresponding to the window according to the mapping relationship between the physical screen and the FPGA. Therefore, the DSP sends the processed video stream to the FPGA, specifically, the DSP sends the processed video stream to the FPGA corresponding to the window under the control of the main control board 100. For example, referring to fig. 1, if the main control board 100 determines that a window is located on the display screen 401 according to the position of the window, it determines that the FPGA corresponding to the window is the FPGA301 according to the mapping relationship, and controls the DSP receiving the video stream corresponding to the window to send the video stream corresponding to the window to the FPGA301, so that the FPGA301 displays the video stream corresponding to the window on the physical screen 401.

Optionally, the DSP may include a DMA (Direct Memory Access) controller. In the DMA mode, the DSP can issue an instruction to the DMA controller, the DMA controller is enabled to process data transmission, and information is fed back to the CPU of the DSP after the data transmission is finished, so that the resource occupation rate of the CPU of the DSP is reduced to a great extent.

The FPGA is configured to configure relevant parameters of a window for displaying a video stream issued by the main control board 100, receive the video stream sent by a certain DSP, and display the video stream in the window on the at least one physical screen connected to the FPGA according to the relevant parameters.

Referring to fig. 1 again, in some embodiments, the display control device 10 further includes a PCIE (Peripheral Component Interconnect Express) switch board 250 connected to the main control board 100. The DSP and the FPGA in the display control device 10 are connected through the PCIE switch board 250.

Referring to fig. 2, a flow chart of a video switching method applied to the main control board 100 according to the present embodiment is shown. The method can solve the problem of poor user experience caused by long-time screen blacking in the display scene switching process. The following describes each step included in the video switching method in detail.

Step S110, receiving a switching instruction, where the switching instruction is used to instruct to switch from a first display scene including a first window to a second display scene including a second window.

In this embodiment, the first display scene is a display layout of a window to be switched currently displayed by the tiled display device 20, and a window used for displaying an old video stream in the display layout of the window to be switched is the first window. The second display scene is a switched window display layout to be displayed by the tiled display device 20, and a window used for displaying a new video stream in the switched window display layout is the second window.

In this embodiment, to improve the user experience, the image frames displayed in the first window of the first display scene are sent to the corresponding second window for display, so as to avoid the entire tiled display device 20 from being blacked out before the new video stream arrives. Specifically, this can be achieved by the following procedure.

Step S120, determining a second FPGA for controlling the second window, and configuring the second window with non-effective windowing parameters on the second FPGA.

According to the foregoing, the main control board 100 may determine the physical screen where the second window is located according to the position of the second window, and then determine the second FPGA corresponding to the second window according to the mapping relationship between the physical screen and the FPGA. For example, after the main control board 100 determines the second FPGA302 corresponding to the second window, the main control board 100 configures a windowing parameter waiting for taking effect for the second window on the second FPGA302, and the windowing parameter taking effect can newly create the second window.

Step S130, determining a target first window corresponding to the second window in the first display scene.

In this embodiment, there is usually more than one first window and one second window, and after the user issues the switching instruction, the main control board 100 needs to determine the corresponding relationship between the newly-created second window and the first window in the first display scene, so as to perform association processing on the second window and the target first window corresponding to the second window in a subsequent process. In a specific embodiment, the main control board 100 may search for a first window having a minimum distance from the second window in the first display scene, and determine the first window as the target first window. Optionally, when the distance is determined, a vertex at the same position (for example, the upper left corner) of the window may be used as a reference point, a target distance between a preset vertex (that is, the reference point) of the first window and the preset vertex of the second window is calculated for the first window in the first display scene, and then the first window with the smallest target distance is selected from the first display scene as the target first window.

Optionally, in this embodiment, in order to ensure that each second window can have a corresponding first window, the number of the first windows and the number of the second windows may be made to be the same. Specifically, when the number of the second windows is smaller than the number of the existing first windows, the redundant first windows are destroyed; and when the number of the second windows is larger than that of the existing first windows, establishing the insufficient first windows.

Step S140, determining a target first FPGA for controlling the target first window, and configuring, on the target first FPGA, a non-effective window elimination parameter for the target first window.

Similarly to step S120, the main control board 100 may determine the physical screen where the target first window is located according to the position of the target first window, and then determine the target first FPGA corresponding to the target first window according to the mapping relationship between the physical screen and the FPGA. After determining the target first FPGA corresponding to the target first window, the main control board 100 configures a window elimination parameter waiting to be validated for the target first window on the target first FPGA, and the validated window elimination parameter can destroy the target first window. The purpose of delaying the validation of the degating parameter is that the old window still needs to display an image before the new window has not been created.

Step S150, determining a receiving DSP corresponding to the target first window, and controlling the receiving DSP to stop sending the received video stream to the target first FPGA.

And after the receiving DSP stops sending the received video stream to the target first FPGA, the target first FPGA does not receive the video stream displayed by the target first window any more, and the last frame image of the video stream displayed by the target first window remained in the image cache region is continuously sent and displayed, so that the content displayed by the target first window stays in the last frame image of the video stream displayed by the target first window.

Step S160, controlling the receiving DSP to obtain a frame of image from the buffer area, setting a first frame flag for the frame of image, obtaining a target image, and storing the target image.

Step S170, controlling the receiving DSP to send the target image to the target first FPGA and the second FPGA, so that the non-effective window-clearing parameter configured on the target first FPGA and the non-effective window-opening parameter configured on the second FPGA take effect.

In this embodiment, when the receiving DSP stops sending the received video stream to the target first FPGA, a plurality of frames of images that are not sent to the target first FPGA (i.e., the next plurality of frames of images of the last frame of image) are also cached in the cache area of the receiving DSP, and any one frame of image is obtained from the plurality of frames of images and stored in the receiving DSP as the target image. The first frame flag may be set for the frame image and then stored, or the first frame flag may be set for the frame image after being stored.

The receiving DSP sends the target image with a first frame mark to the target first FPGA and the second FPGA under the control of the main control board 100, and based on a first frame detection function of the FPGA, the target first FPGA will take effect on the window elimination parameter when detecting the first frame mark, that is, destroy the target first window; the second FPGA will validate the windowing parameter upon detecting the first frame marker, i.e., create the second window, and display the target image in the second window.

Through the process, on one hand, the old window can be destroyed, and simultaneously the new window is newly built; on the other hand, the target image is continuously displayed in the newly created second window until the new video stream is not presented.

Through the process, firstly, the picture displayed by the target first window stays at the last frame of the old video stream, and then the corresponding second window is newly built while the first target window is destroyed. Since the second FPGA receives one frame of image (i.e. the target image) of the old video stream when the second window is newly created (i.e. when the windowing parameter is in effect), the target image is continuously displayed in the second window before the new video stream is sent to the second window. All the first windows in the first display scene and all the second windows in the second display scene exhibit the switching effect according to the corresponding relationship, so that continuous black brushing of the tiled display device 20 is avoided. In the related art, although the time for the brushing black during the display scene switching can be shortened by some measures, the brushing black phenomenon still exists. Therefore, the video switching method provided by the embodiment of the invention can greatly improve the user experience because the black brushing process is completely eliminated.

Optionally, when the display control device 10 further includes the PCIE switch board 250 shown in fig. 1, the receiving DSP may send the target image to the target first FPGA and the second FPGA through the PCIE switch board 250. In detail, step S170 may include the sub-steps shown in fig. 3:

step S310, obtaining a target first video memory address of the video stream corresponding to the target first window in the target first FPGA and a second video memory address of the video stream corresponding to the second window in the second FPGA according to the switching instruction, and issuing the target first video memory address and the second video memory address to the PCIE switch board 250;

step S320, controlling the receiving DSP to send the target image to the PCIE switch board 250;

step S330, controlling the PCIE switch board 250 to send the target image to the PCIE address corresponding to the target first video memory address and the PCIE address corresponding to the second video memory address, respectively.

The PCIE switch board 250 sends the target image to the PCIE address corresponding to the target first video memory address and the PCIE address corresponding to the second video memory address in parallel, so that the target first video memory address of the target first FPGA and the second video memory address of the second FPGA receive the target image at the same time, and the target first FPGA and the second FPGA take the window elimination parameter and the window opening parameter into effect at the same time when detecting the first frame flag in the target image.

Optionally, when the size of the target first window is different from that of the second window, in order to match the size of the target image when displayed in the second window with that of the second window, the target image may be scaled by using an image scaling function of the DSP. In detail, the main control board 100 may control the receiving DSP to scale the target image according to the configuration parameter of the second window included in the switching instruction before controlling the receiving DSP to send the target image to the second FPGA.

Referring to fig. 4, an embodiment of the invention further provides a block diagram of a video switching apparatus 400.

The video switching apparatus 400 is applied to the main control board 100, and includes a switching instruction receiving module 410, a windowing parameter configuration module 420, a window determining module 430, a window eliminating parameter configuration module 440, a first control module 450, a second control module 460, and a third control module 470.

The switching instruction receiving module 410 is configured to receive a switching instruction, where the switching instruction is used to instruct to switch from a first display scene including a first window to a second display scene including a second window.

The windowing parameter configuration module 420 is configured to determine a second FPGA controlling the second window, and configure the non-valid windowing parameter for the second window on the second FPGA.

The window determination module 430 is configured to determine a target first window corresponding to the second window in the first display scene.

The window elimination parameter configuration module 440 is configured to determine a target first FPGA controlling the target first window, and configure, on the target first FPGA, an ineffective window elimination parameter for the target first window.

The first control module 450 is configured to determine a receiving DSP corresponding to the target first window, and control the receiving DSP to stop sending the received video stream to the target first FPGA.

The second control module 460 is configured to control the receiving DSP to obtain a frame of image from the buffer, set a first frame flag for the frame of image, obtain a target image, and store the target image.

The third control module 470 is configured to control the receiving DSP to send the target image to the first target FPGA and the second FPGA, so that the non-effective window-removing parameter configured on the target first FPGA and the non-effective window-opening parameter configured on the second FPGA are effective.

Optionally, the display control device 10 further includes a PCIE switch board 250 connected to the main control board 100, the at least one DSP, and the at least one FPGA;

the third control module 470 includes a video memory address issuing sub-module, a first control sub-module, and a second control sub-module.

The video memory address issuing submodule is configured to control the receiving DSP to send the target image to the PCIE switch board 250.

The first control sub-module is configured to control the receiving DSP to send the target image to the PCIE switch board 250.

The second control sub-module is configured to control the PCIE switch board 250 to obtain a first target PCIE address corresponding to the first target video memory address.

Optionally, the window determining module includes a window determining sub-module, and the window determining sub-module is configured to find a first window having a minimum distance from the second window in the first display scene, and determine the first window as the target first window.

Optionally, the video switching apparatus 400 further includes a fourth control module, where the fourth control module is configured to control the receiving DSP to scale the target image according to the configuration parameter of the second window included in the switching instruction before the receiving DSP sends the target image to the second FPGA.

Referring to fig. 5 again, the main control board 100 further includes a processor 11 and a machine-readable storage medium 12.

The elements of the processor 11 and the machine-readable storage medium 12 are electrically connected to each other directly or indirectly to realize data transmission or interaction. The video switching apparatus 400 includes at least one software functional module, which may be stored in a machine-readable storage medium 12 in the form of software or firmware (firmware) or solidified in an Operating System (OS) of the main control board 100. The processor 11 is used for executing executable modules stored in the machine-readable storage medium 12, such as software functional modules and computer programs included in the video switching apparatus 400.

The machine-readable storage medium 12 may be, but is not limited to, a Random Access Memory (RAM), a Read Only Memory (ROM), a Programmable Read Only Memory (PROM), an erasable ROM (EPROM), an electrically Erasable EEPROM (EEPROM), and the like.

The processor 11 may be an integrated circuit chip having signal processing capabilities. The Processor 11 may also be a general-purpose Processor, such as a Central Processing Unit (CPU), a Network Processor (NP), a microprocessor, etc.; but may also be a Digital Signal Processor (DSP)), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components; the processor 11 may also be any conventional processor that may implement or perform the methods, steps and logic blocks disclosed in the embodiments of the present invention.

It should be understood that the configuration shown in fig. 5 is merely illustrative, and that the main control board 100 may have more or fewer components than shown in fig. 5, or a completely different configuration than shown in fig. 5. Further, the components shown in FIG. 5 may be implemented in software, hardware, or a combination thereof.

In summary, embodiments of the present invention provide a video switching method, an apparatus, and a display control device, where a main control board of the display control device stores a frame of image and sets a first frame flag on a receiving DSP by configuring a non-valid window-canceling parameter on a target first FPGA and a non-valid window-opening parameter on a second FPGA, and sends the frame of image with the first frame flag to the target first FPGA and the second FPGA, so that the non-valid window-canceling parameter configured on the target first FPGA and the non-valid window-opening parameter configured on the second FPGA become valid. Therefore, before a new video stream arrives, the last frame of image of the target first window is continuously displayed for the user, and the problem of poor user experience caused by long-time screen blacking in the display scene switching process is solved.

In the embodiments provided in the present invention, it should be understood that the disclosed apparatus and method can be implemented in other ways. The apparatus and method embodiments described above are illustrative only, as the flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

In addition, the functional modules in the embodiments of the present invention may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, an electronic device, or a network device) to perform all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes. It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings or the orientations or positional relationships that the products of the present invention are conventionally placed in use, and are only used for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," "third," and the like are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.

In the description of the present invention, it should also be noted that, unless otherwise explicitly specified or limited, the terms "disposed," "mounted," "connected," and "connected" are to be construed broadly and may, for example, be fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A video switching method is characterized in that the method is applied to a main control board of a display control device, and the display control device further comprises at least one DSP and at least one FPGA which are connected with the main control board; the FPGA is connected with at least one physical screen in the splicing display equipment; the method comprises the following steps:

2. The video switching method according to claim 1, wherein the display control device further comprises a PCIE switch board connected to the main control board, the at least one DSP, and the at least one FPGA;

the controlling the receiving DSP to send the target image to the target first FPGA and the second FPGA includes:

obtaining a target first video memory address of the video stream corresponding to the target first window in the target first FPGA and a second video memory address of the video stream corresponding to the second window in the second FPGA according to the switching instruction, and issuing the target first video memory address and the second video memory address to the PCIE switching board;

controlling the receiving DSP to send the target image to the PCIE switching board;

and controlling the PCIE switching board to respectively send the target image to a PCIE address corresponding to the target first video memory address and a PCIE address corresponding to the second video memory address.

3. The video switching method according to claim 1 or 2, wherein determining a target first window corresponding to the second window in the first display scene comprises:

and searching a first window with the minimum distance to the second window in the first display scene, and determining the first window as the target first window.

4. The video switching method according to claim 3, wherein searching for the first window having the smallest distance from the second window in the first display scene and determining the first window as the target first window comprises:

calculating a target distance between a preset vertex of a first window and the preset vertex of a second window aiming at the first window in the first display scene;

and selecting a first window with the minimum target distance from the first display scene as the target first window.

5. The video switching method according to claim 1 or 2, wherein the method further comprises:

and controlling the receiving DSP to zoom the target image according to the configuration parameters of the second window included in the switching instruction before the receiving DSP sends the target image to the second FPGA.

6. A video switching device is characterized in that the video switching device is applied to a main control board of a display control device, and the display control device further comprises at least one DSP and at least one FPGA which are connected with the main control board; the FPGA is connected with at least one physical screen in the splicing display equipment; the device comprises:

7. The video switching apparatus according to claim 6, wherein the display control device further comprises a PCIE switch board connected to the main control board, the at least one DSP, and the at least one FPGA;

the third control module includes:

a video memory address issuing sub-module, configured to obtain, according to the switching instruction, a target first video memory address of the video stream corresponding to the target first window in the target first FPGA and a second video memory address of the video stream corresponding to the second window in the second FPGA, and issue the target first video memory address and the second video memory address to the PCIE switch board;

the first control submodule is used for controlling the receiving DSP to send the target image to the PCIE switching board;

and the second control submodule is used for controlling the PCIE switching board to respectively send the target image to the PCIE address corresponding to the target first video memory address and the PCIE address corresponding to the second video memory address.

8. The video switching apparatus according to claim 6 or 7, wherein the window determining module comprises a window determining sub-module configured to:

9. The video switching apparatus according to any one of claims 6 or 7, wherein said apparatus further comprises a fourth control module, said fourth control module is configured to:

10. The display control equipment is characterized by comprising a main control board, and at least one DSP and at least one FPGA which are connected with the main control board; the FPGA is connected with at least one physical screen in the splicing display equipment;

the master control board performs video switching by the method of any one of claims 1-5.