CN111081562A - Chip packaging method and chip packaging structure - Google Patents

Chip packaging method and chip packaging structure Download PDF

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Publication number
CN111081562A
CN111081562A CN201911357759.4A CN201911357759A CN111081562A CN 111081562 A CN111081562 A CN 111081562A CN 201911357759 A CN201911357759 A CN 201911357759A CN 111081562 A CN111081562 A CN 111081562A
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chip
layer
packaged
substrate
film
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Chinese (zh)
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李飞
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China Core Integrated Circuit Ningbo Co Ltd
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China Core Integrated Circuit Ningbo Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/315—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the encapsulation having a cavity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H01L2221/68386—Separation by peeling

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

The invention discloses a chip packaging method and a chip packaging structure. The method comprises the following steps: providing a substrate and a device wafer, wherein a plurality of chips to be packaged are formed on the device wafer; forming a temporary bonding layer on a substrate; forming a thin film cap layer on the temporary bonding layer; forming a supporting layer on the thin film top cover layer, wherein the supporting layer is made of a photosensitive material; a plurality of cavities which correspond to a plurality of chips to be packaged one by one are formed in the supporting layer, the cavities penetrate through the supporting layer and expose the film top cover layer, and the supporting layer around the cavities and the film top cover layer exposed by the cavities form a cover body matched with the chips to be packaged; bonding the surface of one side of the device wafer, which is provided with the chip to be packaged, with the supporting layer, so that each cover body covers an effective functional area of the chip to be packaged; the temporary bonding layer is removed and the substrate is removed. The thickness of the chip to be packaged which is packaged can be effectively reduced.

Description

Chip packaging method and chip packaging structure
Technical Field
The present invention relates to the field of semiconductor device manufacturing, and in particular, to a chip packaging method and a chip packaging structure.
Background
Since the development of analog rf communication technology in the early 90 th century, rf front-end modules have gradually become the core components of communication devices. In all rf front-end modules, the filter has become the most fierce component to grow and have the greatest development prospect. With the rapid development of wireless communication technology, 5G communication protocols are becoming mature, and the market also puts forward more strict standards on various aspects of the performance of radio frequency filters. The performance of the filter is determined by the resonator elements that make up the filter. Among the existing filters, the Film Bulk Acoustic Resonator (FBAR) is one of the most suitable filters for 5G applications due to its small size, low insertion loss, large out-of-band rejection, high quality factor, high operating frequency, large power capacity, and good anti-electrostatic shock capability.
For existing surface acoustic wave filters (SAW) or thin film bulk acoustic wave filters (BAW) and other chips, it is usually necessary to ensure that the functional area of the chip to be packaged cannot contact any substance due to product performance and design functional requirements, i.e. cavity structure design.
With the development of semiconductor technology, semiconductor devices are increasingly being made smaller and thinner. The traditional filter packaging method adopts a silicon cap (Si cap) mode, the lowest (thinnest) overall thickness of a chip to be packaged by the mode can only reach about 200um, and the requirement of a high-end packaging module cannot be met.
Therefore, it is necessary to provide a packaging method capable of further reducing the thickness of the chip.
Disclosure of Invention
The invention aims to provide a chip packaging method and a chip packaging structure, which can further reduce the thickness of a chip to be packaged.
In order to achieve the above object, the present invention provides a chip packaging method, including:
providing a substrate and a device wafer, wherein a plurality of chips to be packaged are formed on the device wafer;
forming a temporary bonding layer on the substrate;
forming a thin film cap layer on the temporary bonding layer;
forming a supporting layer on the thin film top cover layer, wherein the supporting layer is made of a photosensitive material;
forming a plurality of cavities in the supporting layer, wherein the cavities correspond to the plurality of chips to be packaged one by one, the cavities penetrate through the supporting layer and expose the film top cover layer, and the supporting layer around the cavities and the film top cover layer exposed by the cavities form a cover body matched with the chips to be packaged;
bonding the surface of one side of the device wafer, provided with the chip to be packaged, with the supporting layer, so that each cover body covers an effective functional area of the chip to be packaged;
reducing the tack of the temporary bonding layer and removing the substrate.
Optionally, the step of forming a temporary bonding layer on the substrate includes:
and cleaning the substrate, and coating a photo-thermal conversion coating on the upper surface of the substrate to form the temporary bonding layer, wherein the substrate is a light-transmitting substrate.
Optionally, the material of the photothermal conversion coating layer comprises a laser photolysis adhesive material.
Optionally, the thin film cap layer comprises a polymeric material having a tensile strength of 150MPa or greater.
Optionally, the step of forming a thin film cap layer on the temporary bonding layer includes:
and attaching a polyimide film or coating a polyimide coating on the temporary bonding layer to form the film top cover layer.
Optionally, in the step of forming a thin film cap layer on the temporary bonding layer, the method further includes:
heating the polyimide film or the coated polyimide coating to harden the polyimide film or the coated polyimide coating to form the film cap layer.
Optionally, the thickness of the polyimide film or the polyimide coating is 10 μm to 20 μm.
Optionally, forming a supporting layer on the thin film cap layer, where the material of the supporting layer is a photosensitive material, and the step includes:
and attaching a dry film or coating a photoresist coating on the film top cover layer to form the support layer.
Optionally, the dry film or the photoresist coating has a thickness of 20 μm to 30 μm.
Optionally, the step of forming a plurality of cavities in the supporting layer, where the cavities correspond to the plurality of chips to be packaged one by one, includes:
and photoetching the dry film or the photoresist coating according to a preset pattern to form a plurality of cavities corresponding to the plurality of chips to be packaged one by one in the dry film or the photoresist coating.
Optionally, in the step of bonding the side surface of the device wafer, where the chip to be packaged is disposed, to the support layer, the method includes:
when the supporting layer is the dry film, bonding the surface of one side of the device wafer, provided with the chip to be packaged, with the upper surface of the dry film;
and when the supporting layer is the photoresist coating, bonding the surface of the side, provided with the chip to be packaged, of the device wafer with the photoresist coating through a bonding adhesive.
Optionally, before the steps of reducing the viscosity of the temporary bonding layer and removing the substrate, the method further includes:
and sequentially carrying out a back thinning process and an electrical interconnection process on one side of the device wafer, which is far away from the chip to be packaged.
Optionally, in the step of reducing the adhesion of the temporary bonding layer and removing the substrate, the method includes:
the photothermal conversion coating is rendered tack-reducing and the substrate is removed by laser irradiation.
Optionally, after the steps of reducing the viscosity of the temporary bonding layer and removing the substrate, the method further includes:
and carrying out a cutting process on the device wafer to form a plurality of packaged chips, wherein each packaged chip comprises the cover body and the chip to be packaged.
The present invention also provides a chip comprising: the chip packaging structure comprises a chip to be packaged and a cover body covering the chip to be packaged, wherein the cover body covers an effective functional area of the chip to be packaged and forms a cavity with the upper surface of the chip to be packaged;
the cover body comprises a supporting part and a film top cover, the bottom of the supporting part is bonded with the edge of the chip to be packaged, and the top of the supporting part is bonded with the edge of the film top cover;
the material of the supporting part is photosensitive material.
Optionally, the material of the film cap comprises polyimide, and the thickness of the film cap is 10 μm to 20 μm.
Optionally, the supporting portion is made of a dry film or a photoresist, and the thickness of the supporting portion is 20 μm to 30 μm.
Optionally, a temporary bonding layer is bonded to a surface of the film cover opposite to the bonding surface of the support.
The invention has the beneficial effects that:
the temporary bonding layer, the film top cover layer and the supporting layer made of photosensitive materials are sequentially formed on the substrate, a plurality of cavities corresponding to a plurality of chips to be packaged one by one are formed in the supporting layer, a cover body capable of covering an effective functional area of the chip to be packaged is formed on the basis of the supporting layer around the cavity and the film top cover exposed out of the cavity, the supporting layer is made of the photosensitive materials, cavity manufacturing can be completed only by photoetching, accuracy is easy to control, thickness is adjustable, and high-cost dry etching of a dielectric layer is avoided; the film top cover and the supporting layer are better in cohesiveness, thin thickness is achieved without extra processing, wafer packaging yield is improved, the supporting layer made of the film top cover and the photosensitive material can effectively reduce the thickness of the packaged chip, and the requirement of a higher-end packaging module can be met.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic structural diagram of a chip to be packaged and packaged by using a silicon cap;
FIG. 2 is a step diagram of a chip packaging method according to the present invention;
fig. 3 to fig. 13 are schematic structural diagrams corresponding to corresponding steps of a chip packaging method provided in this embodiment;
description of reference numerals:
in fig. 1:
101. a silicon cap; 102. and (5) packaging the chip.
In FIGS. 3 to 13:
201. a substrate; 202. a temporary bonding layer; 203. a thin film cap layer; 204. a support layer; 205. a cavity; 206. a device wafer; 207. a chip to be packaged; 203', a film top cover; 204' and a support.
Detailed Description
As shown in fig. 1, in the conventional chip packaging method, a silicon cap 101 is used for packaging a chip 102 to be packaged, and the thickness of the silicon cap 101 is thick, so that the thinnest whole packaged chip can only reach about 200um, and the selection of a high-end packaging module cannot be met.
In order to solve the above problems, the present invention provides a chip packaging method and a chip. The chip packaging method provided by the invention can effectively reduce the thickness of the packaged chip and can meet the requirements of a higher-end packaging module.
The method for packaging the chip of the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description and drawings, it being understood, however, that the concepts of the present invention may be embodied in many different forms and should not be construed as limited to the specific embodiments set forth herein. The drawings are in simplified form and are not to scale, but are provided for convenience and clarity in describing embodiments of the invention.
The terms "first," "second," and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other sequences than described or illustrated herein. Similarly, if the method described herein comprises a series of steps, the order in which these steps are presented herein is not necessarily the only order in which these steps may be performed, and some of the described steps may be omitted and/or some other steps not described herein may be added to the method. Although elements in one drawing may be readily identified as such in other drawings, the present disclosure does not identify each element as being identical to each other in every drawing for clarity of description.
Fig. 2 is a step diagram of a chip packaging method according to an embodiment of the present invention, and referring to fig. 2, the chip packaging method includes:
step 1: providing a substrate 201 and a device wafer 206, wherein a plurality of chips 207 to be packaged are formed on the device wafer 206;
step 2: forming a temporary bonding layer 202 on a substrate 201;
and step 3: forming a thin film cap layer 203 on the temporary bonding layer 202;
and 4, step 4: forming a support layer 204 on the thin film top cover layer 203, wherein the material of the support layer 204 is a photosensitive material;
and 5: a plurality of cavities 205 corresponding to the plurality of chips 207 to be packaged one by one are formed in the supporting layer 204, the cavities 205 penetrate through the supporting layer 204 and expose the thin film top cover layer 203, and the supporting layer 204 around the cavities 205 and the thin film top cover layer 203 exposed by the cavities 205 form a cover body matched with the chips 207 to be packaged;
step 6: bonding the surface of the device wafer 206, which is provided with the chip 207 to be packaged, with the upper surface of the support layer 204, so that each cover body covers an effective functional area of the chip 207 to be packaged;
and 7: the adhesion 202 of the temporary bonding layer is lowered and the substrate 201 is removed.
Fig. 3 to 13 are schematic structural diagrams corresponding to corresponding steps of a chip packaging method provided in this embodiment, and the chip packaging method provided in this embodiment will be described in detail below with reference to fig. 3 to 13.
Referring to fig. 3 and 8, a substrate 201 and a device wafer 206 are provided, wherein a plurality of chips 207 to be packaged are formed on the device wafer 206, and each chip 207 to be packaged includes a plurality of resonators. The substrate 201 may be any transparent substrate known to those skilled in the art, and the substrate 201 in this embodiment is a glass substrate.
Referring to fig. 4, the surface of a substrate 201 is cleaned, and a light-to-heat conversion coating (LTHC) is coated on the upper surface of the substrate 201 to form a temporary bonding layer 202. The photo-thermal conversion coating has the properties of converting into heat after receiving illumination and losing viscosity by pyrolysis, and can play a role in temporary adhesion. In this embodiment, the material of the photothermal conversion coating includes a laser photolysis adhesive material, that is, only the high temperature generated by laser irradiation can reduce the adhesion of the LTCH. In other embodiments, the temporary bonding layer is a photolyzed or pyrolyzed dry film.
Referring to FIG. 5, the thin film cap layer comprises a polymeric material having a tensile strength of 150MPa or greater. In this embodiment, a Polyimide (PI) material is selected to form the thin film cap layer. Specifically, a Polyimide (PI) coating with a thickness of 10 μm to 20 μm is coated on the upper surface of the temporary bonding layer 202 to form a thin film cap layer 203. Polyimide is one of organic polymer materials with the best comprehensive performance, has the performances of high temperature resistance, high insulation, low thermal expansion coefficient, difficult deformation and the like, can be heated to be hardened (the glass transition temperature is 200 ℃ C. and 300 ℃ C.) after the liquid polyimide is coated on the temporary bonding layer 202, and can form a layer of hard film with higher mechanical strength on the temporary bonding layer 202. In another embodiment of the present invention, a polyimide film with a thickness of 10 μm to 20 μm may be further attached to the upper surface of the temporary bonding layer 202 to form a film cap layer 203, and then the film cap layer is heated and cured (the glass transition temperature is 200 ℃ C. and 300 ℃ C.), which can also achieve the same effect. Because of the high temperature resistance of LTCH, its tack is reduced only by laser irradiation, and thus adhesion to thin film cap layer 203 is maintained during heating of thin film cap layer 203. In other embodiments of the present invention, a mixture of polyimides may also be selected as the material of the thin film cap layer 203, such as a composite material of polyimide/silicon dioxide or polyimide/titanium dioxide. The thickness of the polyimide coating or polyimide film may also be less than 10 μm or greater than 20 μm, such as 5 μm, 30 μm, 40 μm, 50 μm. Design choices are made by those skilled in the art according to actual needs, and are not described in detail herein.
Referring to fig. 6, a dry film having a thickness of 20 μm to 30 μm is attached to the upper surface of the thin film cap layer 203 to form a support layer 204. In another embodiment of the present invention, a photoresist coating layer with a thickness of 20 μm to 30 μm may be further coated on the upper surface of the thin film cap layer 203 using photoresist as the support layer 204. In other embodiments of the present invention, the thickness of the dry film or photoresist may also be less than 20 μm or greater than 30 μm, such as 10 μm, 40 μm, 50 μm. The skilled person can choose the strength of the support layer or the height of the support layer, the size of the cavity, etc. In the specific implementation process, the thicknesses of the thin film top cover layer 203 (polyimide coating or polyimide film) and the support layer 204 (dry film or photoresist) are respectively controlled according to the specific requirements of the cover body design, so as to control the structural strength of the finally formed cover body.
Referring to fig. 7, the dry film or the photoresist coating is subjected to photolithography according to a preset pattern to form a plurality of cavities 205 in the dry film or the photoresist coating, which correspond to the plurality of chips 207 to be packaged one by one. The cavity 205 penetrates through the support layer 204 and exposes the thin film cap layer 203, and the support layer 204 around the cavity 205 and the thin film cap layer 203 exposed by the cavity 205 form a cover body which is matched with the chip 207 to be packaged.
Referring to fig. 9, a side surface of the device wafer 206 having the chips 207 to be packaged is bonded to the upper surface of the supporting layer 204, such that each cover covers an active functional area of one of the chips 207 to be packaged.
In one example, when the supporting layer 204 is a dry film, a side surface of the device wafer 206 provided with the chip 207 to be packaged is bonded to an upper surface of the dry film; in another example, when the supporting layer 204 is a photoresist coating, the surface of the device wafer 206 on the side provided with the chips 207 to be packaged is bonded with the photoresist coating by a bonding adhesive, which may be selected to fix an epoxy around the fibers, or the like.
Referring to fig. 10, after the device wafer 206 is bonded to the support layer 204, a back thinning process and an electrical interconnection process are sequentially performed on a side of the device wafer 206 away from the chip 207 to be packaged. The back side thinning process may adopt a grinding or etching process, and the etching process may be a wet etching process or a dry etching process, wherein a dry etching process is preferably used, and the dry etching process includes but is not limited to Reactive Ion Etching (RIE), ion beam etching, plasma etching or laser cutting. The dry etching may be, for example, Inductively Coupled Plasma (ICP) etching, Reactive Ion Etching (RIE), or the like. Electrical interconnection (bumping), i.e. leading out the electrical property of the chip to be packaged on the back side of the device wafer 206, such as manufacturing Through Silicon Vias (TSVs), exposing the electrical bonding pad of the chip to be packaged on the front side of the device wafer 206, leading the electrical property of the bonding pad to the back side of the device wafer by using a conductive plug or a metal circuit, and manufacturing metal redistribution on the back side, and manufacturing copper-tin or gold bumps on the redistribution to realize the electrical connection between the chip and the outside.
Referring to fig. 11, the photothermal conversion coating (laser photolytic adhesive material) is pyrolyzed by laser and the substrate 201 is removed. And then, pasting a film on the thinned surface of the device wafer, wherein a cutting film (double-sided adhesive tape) is selected as the material of the film so as to reinforce the thinned device wafer and prevent the thinned device wafer from breaking, so that the subsequent cutting process is facilitated.
Referring to fig. 12 and 13, after the steps of lowering the adhesion 202 of the temporary bonding layer and removing the substrate 201, a dicing process (a dicing street is shown by a dotted line in fig. 12) is performed on the device wafer 206 to form a plurality of packaged chips, each of which includes a cover and a chip 207 to be packaged.
Referring to fig. 13, the present invention further provides a chip package structure, including: the chip packaging structure comprises a chip 207 to be packaged and a cover body covering the chip 207 to be packaged, wherein the cover body covers an effective functional area of the chip 207 to be packaged and forms a cavity with the upper surface of the chip 207 to be packaged;
the cover body comprises a supporting part 204' and a film top cover 203', the bottom of the supporting part 204' is bonded with the edge of the chip 207 to be packaged, and the top of the supporting part 204' is bonded with the lower surface of the film top cover 203 ';
the material of the support portion 204' is a photosensitive material.
In this embodiment, the material of the film cover 203 'includes polyimide, and the thickness of the film cover 203' is 10 μm to 20 μm. The supporting portion 204 'is made of dry film or photoresist, and the thickness of the supporting portion 204' is 20 μm to 30 μm. And a temporary bonding layer is bonded on the surface of the film top cover opposite to the bonding surface of the support part. In some embodiments, the temporary bonding layer, when fabricated, provides adhesion to the substrate used for support to facilitate processing. After the substrate is removed, the temporary bonding layer is detached from the substrate and remains on the thin film cap. The temporary bonding layer can increase the supporting strength of the film top cover to a certain extent. In some embodiments, the temporary bonding layer may be a photothermal conversion coating, a photolyzed or pyrolyzed dry film, or the like.
In summary, a thin layer of polyimide or dry film can be covered on the surface of the cavity of the chip 207 to be packaged by adopting a temporary bonding mode, so that the overall thickness of the packaged chip is effectively reduced, and the chip is sealed and protected. In addition, the PI film top cover layer 203 and the photosensitive material support layer 204 are directly formed on the glass substrate, so that the pollution to the chip 207 to be packaged on the device wafer is avoided, and the developing residue tolerance of the dry film or the photoresist is high. Meanwhile, the polyimide, the dry film or the photoresist adopted by the invention has relatively low cost, the cost can be reduced, the thicknesses of the polyimide and the photoresist can be controlled according to actual requirements, and the strength of the cover body is further controlled, so that the process requirements of subsequent injection molding and the like are met.
It should be noted that, in the present specification, all the embodiments are described in a related manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the structural embodiment, since it is substantially similar to the method embodiment, the description is relatively simple, and for the relevant points, reference may be made to the partial description of the method embodiment.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.

Claims (18)

1. A method for packaging a chip, comprising:
providing a substrate and a device wafer, wherein a plurality of chips to be packaged are formed on the device wafer;
forming a temporary bonding layer on the substrate;
forming a thin film cap layer on the temporary bonding layer;
forming a supporting layer on the thin film top cover layer, wherein the supporting layer is made of a photosensitive material;
forming a plurality of cavities in the supporting layer, wherein the cavities correspond to the plurality of chips to be packaged one by one, the cavities penetrate through the supporting layer and expose the film top cover layer, and the supporting layer around the cavities and the film top cover layer exposed by the cavities form a cover body matched with the chips to be packaged;
bonding the surface of one side of the device wafer, provided with the chip to be packaged, with the supporting layer, so that each cover body covers an effective functional area of the chip to be packaged;
reducing the tack of the temporary bonding layer and removing the substrate.
2. The method for packaging the chip according to claim 1, wherein the step of forming the temporary bonding layer on the substrate comprises:
and cleaning the substrate, and coating a photo-thermal conversion coating on the upper surface of the substrate to form the temporary bonding layer for adhering the thin film top cover layer, wherein the substrate is a light-transmitting substrate.
3. The method for encapsulating a chip according to claim 2, wherein the material of the photothermal conversion coating comprises a laser photolysis adhesive material.
4. The method of packaging a chip of claim 1, wherein the thin film cap layer comprises a polymeric material having a tensile strength of 150MPa or greater.
5. The method for packaging a chip according to claim 1, wherein the step of forming a thin film cap layer on the temporary bonding layer comprises:
and attaching a polyimide film or coating a polyimide coating on the temporary bonding layer.
6. The method for packaging a chip according to claim 5, wherein the step of forming a thin film cap layer on the temporary bonding layer further comprises:
heating the polyimide film or the coated polyimide coating to harden the polyimide film or the coated polyimide coating to form the film cap layer.
7. The method for packaging a chip according to any one of claims 5 or 6, wherein the thickness of the polyimide film or the polyimide coating is 10 μm to 20 μm.
8. The method for packaging the chip according to claim 1, wherein a supporting layer is formed on the thin film cap layer, and the step of forming the supporting layer from a photosensitive material comprises:
and attaching a dry film or coating a photoresist coating on the film top cover layer to form the support layer.
9. The method of claim 8, wherein the thickness of the dry film or the photoresist coating is 20 μm to 30 μm.
10. The method for packaging chips according to claim 9, wherein the step of forming a plurality of cavities in the supporting layer in one-to-one correspondence with the plurality of chips to be packaged comprises:
and photoetching the dry film or the photoresist coating according to a preset pattern to form a plurality of cavities corresponding to the plurality of chips to be packaged one by one in the dry film or the photoresist coating.
11. The method for packaging the chip as claimed in claim 10, wherein the step of bonding the side surface of the device wafer provided with the chip to be packaged and the supporting layer comprises:
when the supporting layer is the dry film, bonding the surface of one side of the device wafer, provided with the chip to be packaged, with the upper surface of the dry film;
and when the supporting layer is the photoresist coating, bonding the surface of the side, provided with the chip to be packaged, of the device wafer with the photoresist coating through a bonding adhesive.
12. The method for packaging a chip according to claim 1, further comprising, before the steps of reducing the adhesion of the temporary bonding layer and removing the substrate:
and sequentially carrying out a back thinning process and an electrical interconnection process on one side of the device wafer, which is far away from the chip to be packaged.
13. The method for packaging the chip according to claim 2, wherein in the steps of reducing the viscosity of the temporary bonding layer and removing the substrate, the method comprises:
the photothermal conversion coating is rendered tack-reducing and the substrate is removed by laser irradiation.
14. The method for packaging a chip according to claim 1, further comprising, after the steps of reducing the adhesion of the temporary bonding layer and removing the substrate:
and carrying out a cutting process on the device wafer to form a plurality of packaged chips, wherein each packaged chip comprises the cover body and the chip to be packaged.
15. A chip package structure, comprising: the chip packaging structure comprises a chip to be packaged and a cover body covering the chip to be packaged, wherein the cover body covers an effective functional area of the chip to be packaged and forms a cavity with the upper surface of the chip to be packaged;
the cover body comprises a supporting part and a film top cover, the bottom of the supporting part is bonded with the edge of the chip to be packaged, and the top of the supporting part is bonded with the edge of the film top cover;
the material of the supporting part is photosensitive material.
16. The chip package structure according to claim 15, wherein the material of the film cap comprises polyimide, and the film cap has a thickness of 10 μ ι η to 20 μ ι η.
17. The chip package structure according to claim 15, wherein the supporting portion is made of a dry film or a photoresist, and the thickness of the supporting portion is 20 μm to 30 μm.
18. The chip package structure according to claim 15, wherein a temporary bonding layer is bonded to a surface of the film cover opposite to the bonding surface of the support portion.
CN201911357759.4A 2019-12-25 2019-12-25 Chip packaging method and chip packaging structure Pending CN111081562A (en)

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