CN111078582B

CN111078582B - Memory system based on mode adjustment mapping segment and operation method thereof

Info

Publication number: CN111078582B
Application number: CN201910634998.3A
Authority: CN
Inventors: 边谕俊
Original assignee: SK Hynix Inc
Current assignee: SK Hynix Inc
Priority date: 2018-10-18
Filing date: 2019-07-15
Publication date: 2023-03-24
Anticipated expiration: 2039-07-15
Also published as: US10860231B2; CN111078582A; KR20200043676A; US20200125261A1

Abstract

The present invention provides a method of operating a memory system including a controller including one or more processors and a memory device including a plurality of memory blocks. The operating method includes receiving a first write command; checking whether there is an available storage space in a zeroth mapped segment region using a location of first Logical Block Address (LBA) information written to the zeroth mapped segment region; determining a pattern of first LBA information and second LBA information corresponding to a first write command when there is no available storage space in the zeroth mapped segment region; increasing the order count of the second LBA information when the pattern of the first LBA information and the second LBA information is determined to be the order pattern; a mapping update operation is performed on a memory block of the memory device by variably adjusting the size of the zeroth mapping segment area based on one or more pieces of LBA information.

Description

Memory system based on mode adjustment mapping segment and operation method thereof

Cross Reference to Related Applications

The present application claims priority to korean patent application No. 10-2018-0124324, filed on 2018, 10, 18, and the disclosure of which is incorporated herein by reference in its entirety.

Technical Field

Various embodiments of the present invention generally relate to a memory device. In particular, embodiments relate to a memory system and a method of operating the same.

Background

More recently, computer environment paradigms have turned into pervasive computing that allows computer systems to be used anytime and anywhere. Therefore, the use of portable electronic devices such as mobile phones, digital cameras, and notebook computers has rapidly increased. Typically, these portable electronic devices use memory systems that utilize memory devices, i.e., data storage devices. The data storage device is used as a primary memory device or a secondary memory device of the portable electronic device.

Disclosure of Invention

Embodiments of the present invention relate to a memory system and an operating method of the memory system that reduce the number of map updates by variably adjusting the size of a map segment and performing an update.

According to an embodiment, a memory system may include: a controller comprising one or more processors; and a storage device including a plurality of storage blocks, wherein the controller includes: command receiving circuitry adapted to receive a first write command from a command queue; a storage space check circuit adapted to check whether there is available storage space in a zeroth mapped segment region using a location of first Logical Block Address (LBA) information written to the zeroth mapped segment region; a pattern determination circuit adapted to determine a pattern of the first LBA information and second LBA information corresponding to the first write command when there is no available storage space in the zeroth mapped segment region; a counting circuit adapted to increase the sequence count when the determination result of the mode determination circuit indicates that the mode of the first LBA information and the second LBA information is the sequential mode; an LBA generation circuit adapted to generate one or more pieces of LBA information based on the sequence count; and an update circuit adapted to perform a map update operation on a memory block of the memory device by variably adjusting a size of the zeroth map segment area based on the one or more pieces of LBA information.

According to an embodiment, an operating method of a memory system including a controller and a memory device, the controller including one or more processors and the memory device including a plurality of memory blocks, includes: receiving a first write command; checking whether there is an available storage space in a zeroth mapped segment region using a location of first Logical Block Address (LBA) information written to the zeroth mapped segment region; when no available storage space exists in the zeroth mapping segment region, determining a pattern of the first LBA information and second LBA information corresponding to the first write command; increasing the sequence count of the second LBA information when the mode of the first LBA information and the second LBA information is determined to be the sequence mode; a mapping update operation is performed on a memory block of the memory device by variably adjusting the size of the zeroth mapped segment region based on one or more pieces of LBA information.

According to an embodiment, a method of operating a memory system, the memory system comprising a controller and a memory device, the controller comprising one or more processors; the memory device comprises a plurality of memory blocks, and the operation method comprises the following steps: receiving a first write command; checking whether there is an available storage space in a zeroth mapped segment region using a location of first Logical Block Address (LBA) information written to the zeroth mapped segment region; determining a pattern of first LBA information written to a zeroth mapped segment region and second LBA information corresponding to a first write command when there is no available storage space in the zeroth mapped segment; increasing the sequence count of the second LBA information until the pattern of the first LBA information and the second LBA information is a random pattern; when the mode of the first LBA information and the second LBA information is a random mode, updating the zeroth mapping segment area to the storage block; and changing the zeroth mapping segment area to the first mapping segment area, generating one or more pieces of LBA information based on the order count, and writing the generated one or more pieces of LBA information to the first mapping segment area.

According to an embodiment, a memory system includes: a memory device comprising a plurality of memory blocks; and a controller comprising a memory and a cache controller adapted to store Logical Block Address (LBA) information in the memory and update the LBA information to the memory device; wherein the cache controller is adapted to: receiving a plurality of pieces of LBA information and storing the plurality of pieces of LBA information in a memory; generating a mapping segment including some of the pieces of LBA information; determining a pattern of a last piece of LBA information in the mapped segment in the list and another piece of LBA information received after the last piece of LBA information; and updating the mapped segment or both the mapped segment and the list to a selected block among the plurality of memory blocks based on the determined pattern.

Drawings

FIG. 1 is a block diagram that schematically illustrates a data processing system that includes a memory system in accordance with an embodiment.

Fig. 2 is a diagram showing an exemplary configuration of a memory device employed in the memory system shown in fig. 1.

Fig. 3 is a diagram illustrating a data processing operation with respect to a memory device in the memory system according to the embodiment.

Fig. 4A and 4B are diagrams schematically showing a memory system according to a first embodiment.

Fig. 5 is a diagram schematically showing a memory system according to a second embodiment.

Fig. 6 is a flowchart showing an operation method of the memory system according to the first embodiment.

Fig. 7 is a flowchart showing an operation method of the memory system according to the second embodiment.

Fig. 8 is a diagram illustrating a concept of a super block used in the memory system according to the embodiment.

Detailed Description

Various embodiments of the present invention are described in more detail below with reference to the accompanying drawings. It is noted, however, that the present invention can be embodied in various forms. Moreover, the aspects and features of the invention may be configured or arranged differently than shown in the illustrated embodiments. Accordingly, the present invention should not be construed as limited to the embodiments set forth herein. Rather, the described embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the invention to those skilled in the art. Moreover, references throughout this specification to "an embodiment," "another embodiment," etc., do not necessarily refer to only one embodiment, and different references to any such phrases are not necessarily referring to the same embodiment.

It will be further understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly on, connected or coupled to the other element or one or more intervening elements may be present. In addition, it will also be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or one or more intervening elements may also be present. Communication between two elements, whether directly or indirectly connected/coupled, may be wired or wireless unless otherwise indicated or otherwise indicated by context.

As used herein, the singular form may also include the plural form and vice versa, unless the context clearly dictates otherwise.

It will be further understood that the terms "comprises," "comprising," "includes" and "including," when used in this specification, specify the presence of stated elements and do not preclude the presence or addition of one or more other elements. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

Various embodiments of the present invention are described in detail below with reference to the accompanying drawings.

FIG. 1 is a block diagram illustrating a data processing system 100 including a memory system according to an embodiment.

Referring to FIG. 1, a data processing system 100 may include a host 102 and a memory system 110.

For example, the host 102 may be implemented by any one of portable electronic devices such as a mobile phone, an MP3 player, and a laptop computer, or non-portable electronic devices such as a desktop computer, a game machine, a Television (TV), and a projector, i.e., wired and wireless electronic devices.

Also, the host 102 includes at least one Operating System (OS). The operating system generally manages and controls the functions and operations of host 102, and provides interoperability between host 102 and users using data processing system 100 or memory system 110. The operating system supports functions and operations corresponding to the purpose of use of the user and the purpose of use of the operating system. For example, depending on the mobility of the host 102, the operating system may be a general operating system or a mobile operating system. Depending on the user's environment of use, a typical operating system may be a personal operating system or an enterprise operating system. For example, personal operating systems configured to support service provisioning functionality for general users may include Windows and Chrome, and enterprise operating systems configured to ensure and support high performance may include Windows server, linux, and Unix. The Mobile operating system configured to support a Mobile service providing function and a system power saving function for a user may include Android, iOS, windows Mobile, and the like. The host 102 may include a plurality of operating systems, and executes the operating systems to perform operations corresponding to user requests on the memory system 110. The host 102 transmits a plurality of commands corresponding to the user request to the memory system 110, and thus the memory system 110 performs an operation corresponding to the commands, that is, an operation corresponding to the user request.

The memory system 110 operates in response to requests by the host 102 and, in particular, stores data to be accessed by the host 102. In other words, the memory system 110 may function as a primary or secondary memory device for the host 102. The memory system 110 may be implemented as any of a variety of storage devices, depending on the host interface protocol coupled with the host 102. For example, the memory system 110 may be implemented as any of the following: solid State Drives (SSDs), multimedia cards (e.g., MMC, embedded MMC (eMMC), reduced-size MMC (RS-MMC), and micro MMC), secure digital cards (e.g., SD, mini-SD, and micro-SD), universal Serial Bus (USB) storage devices, universal flash memory (UFS) devices, compact Flash (CF) cards, smart media cards, and memory sticks.

Any of the storage devices implementing memory system 110 may be volatile memory devices such as Dynamic Random Access Memory (DRAM) and/or Static Random Access Memory (SRAM), or non-volatile memory devices such as Read Only Memory (ROM), mask ROM (MROM), programmable ROM (PROM), erasable Programmable ROM (EPROM), electrically Erasable Programmable ROM (EEPROM), ferroelectric Random Access Memory (FRAM), phase change RAM (PRAM), magnetic RAM (MRAM), and/or Resistive RAM (RRAM).

Memory system 110 includes a memory device 150 and a controller 130, memory device 150 storing data to be accessed by host 102, controller 130 controlling the storage of data in memory device 150.

The controller 130 and the memory device 150 may be integrated into one semiconductor device. For example, the controller 130 and the memory device 150 may be integrated into one semiconductor device and configure a Solid State Drive (SSD). In the case where the memory system 110 is used as an SSD, the operation speed of the host 102 coupled to the memory system 110 can be improved. The controller 130 and the memory device 150 may be integrated into one semiconductor device to form a memory card such as the following: personal Computer Memory Card International Association (PCMCIA) cards, standard flash (CF) cards, smart media cards (e.g., SM and SMC), memory sticks, multimedia cards (e.g., MMC, RS-MMC, and micro MMC), secure digital cards (e.g., SD, mini SD, micro SD, and SDHC), and/or Universal Flash (UFS) devices.

In another embodiment, the memory system 110 may be arranged in: a computer, an Ultra Mobile PC (UMPC), a workstation, a netbook, a Personal Digital Assistant (PDA), a portable computer, a network tablet, a wireless phone, a mobile phone, a smart phone, an electronic book, a Portable Multimedia Player (PMP), a portable game machine, a navigation device, a black box, a digital camera, a Digital Multimedia Broadcasting (DMB) player, a three-dimensional television, a smart television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a storage device configuring a data center, a device capable of transmitting and receiving information under a wireless environment, one of various electronic devices configuring a home network, one of various electronic devices configuring a computer network, one of various electronic devices configuring a remote information processing network, a Radio Frequency Identification (RFID) device, or one of various components configuring a computing system.

The memory device 150 may retain stored data even if power is not supplied. In particular, the memory device 150 stores data provided from the host 102 through a write operation, and provides the stored data to the host 102 through a read operation. Memory device 150 includes a plurality of memory dies 1501 to 150n.

Each of the plurality of memory dies 1501 to 150n includes a plurality of memory blocks BLK0 to BLKz-1, each memory block including a plurality of pages. Each of the pages includes a plurality of memory cells coupled to a plurality of Word Lines (WLs). Also, memory device 150 includes multiple planes, each plane including multiple memory blocks, such as blocks BLK0 through BLKz-1. In particular, memory device 150 may include a plurality of memory dies 1501 to 150n, each memory die 1501 to 150n including a plurality of planes. Memory device 150 may be a non-volatile memory device, such as a flash memory. The flash memory may have a three-dimensional (3D) stack structure.

The controller 130 controls the memory device 150 in response to a request from the host 102. For example, the controller 130 provides data read from the memory device 150 to the host 102, and stores data provided from the host 102 in the memory device 150. To this end, the controller 130 controls operations of the memory device 150, such as a read operation, a write operation, a program operation, and an erase operation.

Controller 130 includes host interface (I/F) circuitry 132, processor 134, memory interface (I/F) circuitry 142, memory 144, and cache controller 145.

Host interface circuitry 132 is used to handle commands, data, etc. transmitted from the host 102. By way of example, and not limitation, the host interface circuitry 132 may include a command queue 52. The command queue 52 may sequentially store at least some of the commands, data, etc. transmitted from the host 102 and output them to the cache controller 145 in the order in which they were stored.

The host interface circuitry 132 processes commands and data for the host 102, and may be configured to communicate with the host 102 through at least one of a variety of interface protocols, such as: universal Serial Bus (USB), multi-media card (MMC), peripheral component interconnect express (PCI-e or PCIe), serial SCSI (SAS), serial Advanced Technology Attachment (SATA), parallel Advanced Technology Attachment (PATA), small Computer System Interface (SCSI), enhanced Small Disk Interface (ESDI), electronic Integrated Drive (IDE), and Mobile Industrial Processor Interface (MIPI). The host interface circuitry 132 may be driven by firmware called the Host Interface Layer (HIL), which is a region where data is exchanged with the host 102.

The memory interface circuit 142 serves as a memory interface and/or storage interface that performs an interface connection between the controller 130 and the memory device 150 to allow the controller 130 to control the memory device 150 in response to requests from the host 102. In the case where the memory device 150 is a flash memory, particularly, in the case where the memory device 150 is a NAND flash memory, the memory interface circuit 142 generates a control signal for the memory device 150 and processes data according to the control of the processor 134 which is a NAND Flash Controller (NFC). Memory interface circuitry 142 may support an interface to handle commands and data between controller 130 and memory device 150, such as the operation of a NAND flash interface, and in particular data input/output between controller 130 and memory device 150. The memory interface circuit 142 may be driven by firmware called a Flash Interface Layer (FIL), which is a region that exchanges data with the memory device 150.

The memory 144, which is a working memory of the memory system 110 and the controller 130, stores data for driving the memory system 110 and the controller 130. For example, when the controller 130 controls the memory device 150 in response to a request from the host 102, the controller 130 may provide data read from the memory device 150 to the host 102 and/or store data provided from the host 102 in the memory device 150. To this end, when the controller 130 controls the memory device 150 operations, such as a read operation, a write operation, a program operation, and an erase operation, the memory 144 stores data required by the memory system 110, i.e., between the controller 130 and the memory device 150, to perform these operations.

The memory 144 may be implemented by a volatile memory. For example, the memory 144 may be implemented by Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). Further, as shown in fig. 1, the memory 144 may be provided inside the controller 130. Alternatively, the memory 144 may be external to the controller 130, and in this regard, the memory 144 may be implemented as a separate external volatile memory that communicates with the controller 130 through the memory interface circuit.

As described above, the memory 144 stores data required to perform data read operations and data write operations between the host 102 and the memory device 150. For such data storage, memory 144 includes program memory, data memory, write buffers/caches, read buffers/caches, data buffers/caches, map buffers/caches, and so forth.

Processor 134 controls the overall operation of memory system 110. In particular, the processor 134 controls a programming operation or a read operation of the memory device 150 in response to a write request or a read request from the host 102. The processor 134 drives firmware called a Flash Translation Layer (FTL) to control the general operation of the memory system 110. Processor 134 may be more than one processor, each of which may be implemented by a microprocessor or Central Processing Unit (CPU).

For example, the controller 130 performs an operation requested by the host 102 in the memory device 150, that is, performs a command operation corresponding to a command received from the host 102 on the memory device 150, through the processor 134 implemented by a microprocessor or a central processing unit CPU. The controller 130 may perform a foreground operation as a command operation corresponding to a command received from the host 102. For example, the foreground operation includes a program operation corresponding to a write command, a read operation corresponding to a read command, an erase operation corresponding to an erase command, or a parameter setting operation corresponding to a set parameter command or a set feature command as a set command.

Controller 130 may also perform background operations on memory device 150 through processor 134. The background operation includes an operation of copying data stored in one memory block among the memory blocks BLK0 to BLKz-1 of the memory device 150 to another memory block. Such background operations may be Garbage Collection (GC) operations; an operation of swapping selection memory blocks BLK0 to BLKz-1 or data stored therein, such as a Wear Leveling (WL) operation; an operation of storing the mapping data stored in the controller 130 in the memory blocks BLK0 to BLKz-1, such as a mapping clear operation; or perform a bad block management operation on the memory device 150, such as an operation of identifying and processing a bad block among the memory blocks BLK0 to BLKz-1 in the memory device 150.

Generally, the controller 130 writes information of logical block addresses LBA (i.e., LBA information) included in a command, for example, a write command, transferred from the command queue 52 to an area (or zeroth mapped segment area) corresponding to a specific (e.g., zeroth) mapped segment. When writing LBA information in the size allocated to the zeroth mapped segment (e.g., 18 KB), the controller 130 must update the zeroth mapped segment to the memory device 150. To improve this process, cache controller 145 does not update the zeroth mapped segment. In contrast, when writing a plurality of pieces of LBA information in the size allocated to the zeroth mapped segment, the cache controller 145 determines the patterns of the first LBA information and the second LBA information to be written, which are written to the area corresponding to the last Index Max _ Index of the zeroth mapped segment. The first LBA information includes previous LBA information, and the second LBA information includes current LBA information transferred from the current command queue to be written. When the determination result indicates that the pattern of the first LBA information and the second LBA information is the sequential pattern, the cache controller 145 counts the sequential LBA information until determining that the pattern of the first LBA information and the second LBA information is the random pattern. In other words, the cache controller 145 may increase the sequence count each time it is determined that the pattern of the first LBA information and the second LBA information is a sequence pattern. Cache controller 145 may update memory device 15 by generating one or more pieces of LBA information by sequence counting and additionally merging the generated LBA information into a zeroth mapping segment. In other words, cache controller 145 may update memory device 150 by variably adjusting the size of the zeroth mapped segment. In this regard, the cache controller 145 according to the first embodiment will be described in detail with reference to fig. 4A and 4B.

In another embodiment, when writing a plurality of pieces of LBA information in the size allocated to the zeroth mapped segment, the cache controller 145 determines the pattern of the first LAB information written to the Max _ Index of the zeroth mapped segment area and the second LBA information to be written without updating the zeroth mapped segment. The first LBA information includes previous LBA information and the second LBA information includes current LBA information transferred from the current command queue to be written. When the determination result indicates that the pattern of the first LBA information and the second LBA information is the sequential pattern, the cache controller 145 counts the sequential LBA information until determining that the pattern of the first LBA information and the second LBA information is the random pattern. In other words, cache controller 145 may increase the sequence count each time it is determined that the pattern of the first LBA information and the second LBA information is a sequence pattern. When the determination result indicates that the pattern of the first LBA information and the second LBA information is a random pattern, the cache controller 145 updates the plurality of pieces of LBA information written to the zeroth mapped segment region in the size allocated to the zeroth mapped segment to the memory device 150. Subsequently, after deleting the plurality of pieces of LBA information written to the zeroth mapped segment region, the cache controller 145 changes the zeroth mapped segment to the first mapped segment and generates one or more pieces of LBA information by sequence counting. The cache controller 145 writes the generated LBA information to an area corresponding to the first mapped segment. In this regard, the cache controller 145 according to the second embodiment will be described in detail with reference to fig. 5.

In some embodiments, a memory system is provided that includes one or more storage devices operatively associated with a host and including one or more processors and programming commands. For example, one or more memory devices including one or more processors and programming commands may be implemented with memory 144 and processor 134 included in controller 130.

As used in this disclosure, the term "circuitry" may refer to all of the following: (a) Hardware-only circuit implementations (such as implementations in analog and/or digital circuitry only) and (b) combinations of circuits and software (and/or firmware) such as (where applicable): (i) A combination of processor(s) or (ii) processor (s)/software (including digital signal processors), software, and portions of memory that work together to cause a device, such as a mobile phone or a server, to perform various functions; and (c) circuitry that requires software or firmware for operation (even if such software or firmware is not physically present), such as microprocessor(s) or a portion of microprocessor(s). This definition of "circuitry" applies to all uses of the term in this application, including in any claims. As a further example, as used in this application, the term "circuitry" would also cover an implementation of merely a processor (or multiple processors) or portion of a processor and its (or their) accompanying software and/or firmware. If the term "circuitry" is applied to a particular claim element, then "circuitry" would also encompass, for example, an integrated circuit for a memory device.

Fig. 2 is a diagram illustrating a memory device in a memory system.

Referring to fig. 2, the memory device 150 includes a plurality of memory blocksFor example, the zeroth block BLK0, the first block BLK1, the second block BLK2, and the (z-1) th block BLKz-1. Each of blocks BLK0, BLK1, BLK2, and BLKz-1 includes multiple pages, e.g., 2 ^M Or M pages. Each page includes a plurality of memory cells coupled to a plurality of Word Lines (WLs).

Depending on the number of bits stored or expressed in one memory cell, memory device 150 may include single-level cell (SLC) memory blocks and/or multi-level cell (MLC) memory blocks. The SLC memory block includes a plurality of pages implemented by memory cells each storing 1-bit data, and has high data calculation performance and high endurance. An MLC memory block includes multiple pages implemented by memory cells each storing multiple bits (e.g., 2 or more bits) of data, and has a larger data storage space than an SLC memory block, i.e., can be highly integrated. In particular, the memory device 150 may include, as MLC memory blocks, an MLC memory block including a plurality of pages implemented by memory cells each capable of storing 2-bit data, a triple-layer cell (TLC) memory block including a plurality of pages implemented by memory cells each capable of storing 3-bit data, a quadruple-layer cell (QLC) memory block including a plurality of pages implemented by memory cells each capable of storing 4-bit data, or a multiple-layer cell memory block including a plurality of pages implemented by memory cells each capable of storing 5-bit or more data.

Although the memory device 150 is described as being implemented by a non-volatile memory, for example a flash memory (such as a NAND flash memory), it is noted that the memory device 150 may be implemented as any of a number of types of memory, such as: phase change memory (i.e., phase Change Random Access Memory (PCRAM)), resistive memory (i.e., resistive random access memory (RRAM or ReRAM)), ferroelectric memory (i.e., ferroelectric Random Access Memory (FRAM)), and spin transfer torque magnetic memory (i.e., spin transfer torque magnetic random access memory (STT-RAM or STT-MRAM)).

Each of the memory blocks BLK0, BLK1, BLK2, and BLKz-1 stores data provided from the host 102 of fig. 1 through a write operation, and provides the stored data to the host 102 through a read operation.

Referring to fig. 3, the controller 130 performs a command operation corresponding to a command received from the host 102, for example, a program operation corresponding to a program command. The controller 130 programs and stores user data corresponding to the program command in a plurality of pages in the memory blocks BLK0 to BLKz-1 of the memory device 150.

The controller 130 generates and updates metadata of the user data and programs and stores the metadata in the memory blocks BLK0 to BLKz-1 of the memory device 150. The metadata includes logical-to-physical (logical/physical or L2P) information and physical-to-logical (physical/logical or P2L) information of the user data stored in the memory blocks BLK0 to BLKz-1. Also, the metadata may include information on command data corresponding to a command received from the host 102, information on a command operation corresponding to the command, information on a memory block of the memory device 150 on which the command operation is to be performed, and information on mapping data corresponding to the command operation. In other words, the metadata may include all information corresponding to commands received from the host 102 and data other than user data.

For example, the controller 130 caches and buffers user data corresponding to a program command received from the host 102 in the first buffer 510 of the controller 130. That is, the controller 130 stores the data section 512 of the user data in the first buffer 510 as a data buffer/cache. The first buffer 510 may be included in the memory 144 of the controller 130. Thereafter, the controller 130 programs and stores the data segment 512 stored in the first buffer 510 in the page included in the memory blocks BLK0 to BLKz-1 of the memory device 150.

When the data segment 512 of the user data is programmed and stored in a Page (represented by Page in fig. 3) in the memory blocks BLK0 to BLKz-1, the controller 130 generates the L2P segment 522 and the P2L segment 524 as metadata. The controller 130 then stores the L2P segment 522 and the P2L segment 524 in the second buffer 520 of the controller 130. The second buffer 520 may be included in the memory 144 of the controller 130. The L2P segments 522 and P2L segments 524 may be stored in the second buffer 520 in the form of a list. Controller 130 then programs and stores L2P segment 522 and P2L segment 524 in pages in memory blocks BLK0 through BLKz-1 via a map clear operation.

The controller 130 performs a command operation corresponding to a command received from the host 102. For example, the controller 130 performs a read operation corresponding to the read command. The controller 130 checks the L2P segment 522 and the P2L segment 524 by loading the L2P segment 522 and the P2L segment 524 of the user data corresponding to the read command in the second buffer 520. The controller 130 then reads the data segment 512 of the user data from the memory location known by the check. That is, the controller 130 reads the data section 512 from a specific page of a specific memory block among the memory blocks BLK0 to BLKz-1. The controller 130 then stores the data segment 512 in the first buffer 510 and provides the data segment 512 to the host 102.

Fig. 4A and 4B are diagrams schematically showing a memory system according to a first embodiment. Fig. 4A illustrates a case where the first Logical Block Address (LBA) information and the second LBA information are sequential patterns. Fig. 4B shows a case where the first LBA information and the second LBA information are random patterns.

Referring to fig. 4A and 4B, the memory system 110 may include a controller 130 and a memory device 150.

Controller 130 may include a memory 144 and a cache controller 145. As described above with reference to fig. 1, the controller 130 may include a host interface circuit 132, a processor 134, and a memory interface circuit 142. However, fig. 4A and 4B omit these components for clarity. Cache controller 145 may be driven by processor 134. Cache controller 145 may include a write command receiving circuit 1450, an available space checking circuit 1451, a mode determination circuit 1452, a counting circuit 1453, an LBA generation circuit 1454, and an update circuit 1455.

As used in this disclosure, the term "circuitry" may refer to all of the following: (a) Hardware-only circuit implementations (such as analog-and/or digital-only circuit implementations) and (b) combinations of circuits and software (and/or firmware), such as (where applicable): (i) A combination of processor(s) or (ii) processor (s)/software (including digital signal processors), portions of software and memory that work together to cause a device, such as a mobile phone or server, to perform various functions, and (c) circuitry that requires software or firmware for operation (even if such software or firmware is not physically present), such as microprocessor(s) or a portion of microprocessor(s). This definition of "circuitry" applies to all uses of the term in this application, including in any claims. As a further example, as used in this application, the term "circuitry" would also cover an implementation of merely a processor (or multiple processors) or portion of a processor and its (or their) accompanying software and/or firmware. If the term "circuitry" is applied to a particular claim element, then "circuitry" would also encompass, for example, an integrated circuit for a memory device.

Referring to fig. 4A, the write command receiving circuit 1450 may request command information including a plurality of pieces of command information from the command queue 52 and receive the requested one or more pieces of command information from the command queue. For example, the plurality of pieces of command information may include a write command or a read command. Further, the plurality of pieces of command information may include a write command. Also, the plurality of pieces of command information may include first to fourth write commands. The write command receive circuit 1450 may request a first write command from the command queue and receive the first write command.

In order to write the write LBA information included in the first write command received through the write command reception circuit 1450 to an area (or mapped segment area) corresponding to the zeroth mapped segment S0, the available space check circuit 1451 may check an available space of the mapped segment area corresponding to the zeroth mapped segment S0. The available space checking circuit 1451 may check the available space of the mapped segment area corresponding to the zeroth mapped segment S0 by checking whether LBA information is written to the mapped segment area corresponding to the zeroth mapped segment S0 in the size of the zeroth mapped segment S0. In other words, the available space checking circuit 1451 may check the available space of the mapping segment area corresponding to the zeroth mapping segment S0 by checking whether the location of the first LBA information written before the second LBA information indicates Max _ INDEX (e.g., 1023) allocated to the mapping segment area corresponding to the zeroth mapping segment S0. When the check result shows that the location where the first LBA information is written does not indicate Max _ INDEX of the mapped segment area corresponding to the zeroth mapped segment S0, the second LBA information corresponding to the first write command may be stored in the mapped segment area corresponding to the zeroth mapped segment S0 by the update circuit 1455, which will be described below. On the other hand, when the check result shows that the position where the first LBA information is written indicates Max _ INDEX of the mapped segment area corresponding to the zeroth mapped segment S0, the available space checking circuit 1451 may determine that the mapped segment area corresponding to the zeroth mapped segment S0 has no available space where the second LBA information is written. Here, to reduce the number of operations to update the memory device 150 by the update circuit 1455, the mode determination circuit 1452 determines the mode of the first LBA information and the second LBA information without updating the zeroth mapping segment S0 to the memory device 150.

The mode determination circuit 1452 may determine the mode of the first LBA information written to Max _ INDEX of the mapped segment region corresponding to the zeroth mapped segment S0 and the second LBA information currently to be written corresponding to the first write command.

Since the determination result of the mode determination circuit 1452 indicates that the first LBA information and the second LBA information are sequential, the count circuit 1453 increments the sequence count information and stores the incremented sequence count information in the sequence count list. The sequence COUNT list may include mapping segment information "S", LBA information "LBA" stored in an INDEX Max _ INDEX of a mapping segment area corresponding to the mapping segment, and a sequence LBA COUNT ". For example, as shown in fig. 4A, the sequence COUNT list display mapping segment information "S" may include the zeroth mapping segment (0), the LBA information "LBA" may include the LBA1001, and the sequence LBA COUNT "may be 3.

More specifically, when the first LBA information written to Max _ INDEX of the mapping segment area corresponding to the zeroth mapping segment S0 is LBA1001 and the second LBA information corresponding to the first write command is LBA1002, the mode determination circuit 1452 determines that the modes of the first LBA information and the second LBA information are sequential modes. Also, the sequential LBA COUNT "may be 1 by the counting circuit 1453.

Because the pattern of LBAs 1001 and 1002 is a sequential pattern, the pattern determination circuit 1452 determines the pattern of LBA information included in the second, third, and fourth write commands received from the command queue by the write command receive circuit 1450. For example, the counting circuit 1453 may increase the sequential LBA COUNT "from 1 to 2 when the mode of the first LBA information and the second LBA information is determined to be the sequential mode because the first LBA information included in the first write command is LBA1002 and the second LBA information included in the second write command is LBA 1003. Subsequently, when the mode of the first LBA information and the second LBA information is determined to be the sequential mode because the first LBA information included in the second write command is LBA1003 and the second LBA information included in the third write command is LBA1004, the counting circuit 1453 may increase the sequential LBA COUNT "from 2 to 3.

Subsequently, when the mode of the first LBA information and the second LBA information is determined to be the random mode because the first LBA information included in the third write command is LBA1004 and the second LBA information included in the fourth write command is LBA1030, the counting circuit 1453 does not perform the counting operation, but the LBA generation circuit 1454 and the update circuit 1455 operate.

The LBA generation circuit 1454 generates one or more pieces of LBA information based on the order count list. For example, it can be seen that the sequential LBA COUNT "after LBA1001 is written to Max _ INDEX of the map segment area corresponding to zeroth map segment S0 is 3. In other words, when the size capable of storing one piece of LBA information is 4KB, the LBA generation circuit 1454 may calculate the size of LBA information to be additionally generated as COUNT × 4KB. That is, since the sequential LBA COUNT "is 3, 12KB can be calculated.

The update circuit 1455 variably adjusts the size of the zeroth mapped segment S0 by adding LBA information generated by the LBA generation circuit 1454 to the zeroth mapped segment S0, and updates the zeroth mapped segment S0 to the memory device 150. In other words, the update circuit 1455 may merge the size 12KB of the zeroth mapping segment S0 with the size 12KB of the additionally generated LBA information to update the memory device 150, thereby reducing the number of updates.

In various embodiments, when writing a plurality of pieces of LBA information in a size allocated to the zeroth mapped segment S0 or the mapped segment region corresponding to the zeroth mapped segment S0, the cache controller 145 does not update the zeroth mapped segment S0, but determines a pattern of first LBA information written to Max _ Index of the mapped segment region corresponding to the zeroth mapped segment S0 and second LBA information to be written. The first LBA information includes previous LBA information and the second LBA information includes LBA information transferred from the current command queue to be written. When the determination result indicates that such first LBA information and second LBA information are sequential patterns, the cache controller 145 counts the sequential LBA information until the patterns of the first LBA information and second LBA information are determined to be random patterns. In other words, cache controller 145 may increase the sequence count each time the pattern of the first LBA information and the second LBA information is determined to be a sequential pattern. Cache controller 145 may update memory device 150 by generating one or more pieces of LBA information through sequence counting and additionally incorporating the generated LBA information into a zeroth mapping segment. In other words, cache controller 145 may update memory device 150 by variably adjusting the size of zeroth mapped segment S0.

Referring to fig. 4B, the write command receiving circuit 1450 may request command information including a plurality of pieces of command information from the command queue and receive the requested one or more pieces of command information from the command queue. For example, the plurality of pieces of command information may include a write command or a read command. Further, the plurality of pieces of command information may include a write command. Also, the plurality of pieces of command information may include first to fourth write commands. The write command receive circuit 1450 may request a first write command from the command queue and receive the first write command from the command queue.

To write LBA information included in the first write command received through the write command receiving circuit 1450 to a mapped segment region of the memory 144 corresponding to the zeroth mapped segment S0, the available space checking circuit 1451 may check an available space of the mapped segment region corresponding to the zeroth mapped segment S0. The available space checking circuit 1451 may check the available space of the mapped segment area corresponding to the zeroth mapped segment S0 by checking whether LBA information is written to the mapped segment area corresponding to the zeroth mapped segment S0 in the size of the zeroth mapped segment S0. In other words, the available space check circuit 1451 may check the available space of the zeroth mapped segment S0 by checking whether the location of the first LBA information written before the second LBA information indicates Max _ INDEX (e.g., 1023) allocated to the mapped segment area corresponding to the zeroth mapped segment S0. When the check result shows that the location where the first LBA information is written does not indicate Max _ INDEX of the mapped segment area corresponding to the zeroth mapped segment S0, the second LBA information corresponding to the first write command may be stored in the mapped segment area corresponding to the zeroth mapped segment S0 by the update circuit 1455, which will be described below. On the other hand, when the check result shows that the position where the first LBA information is written indicates Max _ INDEX of the zeroth mapped segment S0, the available space checking circuit 1451 may determine that the mapped segment area corresponding to the zeroth mapped segment S0 has no available space to which the second LBA information may be written. Here, to reduce the number of operations to update the memory device 150 by the update circuit 1455, the mode determination circuit 1452 determines the mode of the first LBA information and the second LBA information without updating the zeroth mapping segment S0 to the memory device 150.

The mode determination circuit 1452 may determine the mode of the first LBA information written to Max _ INDEX of the mapped segment region corresponding to the zeroth mapped segment S0 and the second LBA information currently to be written corresponding to the first write command. For example, when the first LBA information written to Max _ INDEX of the mapping segment area corresponding to the zeroth mapping segment S0 is LBA1001 and the second LBA information corresponding to the first write command is LBA1030, the pattern determination circuit 1452 determines that the patterns of the first LBA information and the second LBA information are random patterns.

The update circuit 1455 may update the plurality of pieces of LBA information included in the zeroth mapping segment S0 to the memory device 150, and the LBA1030 corresponding to the first write command may be written to the first mapping segment.

Referring to fig. 5, the memory system 110 may include a controller 130 and a memory device 150.

Controller 130 may include a memory 144 and a cache controller 145. As described above with reference to fig. 1, the controller 130 may include a host interface circuit 132, a processor 134, and a memory interface circuit 142. However, these components are omitted from FIG. 5 for clarity. Cache controller 145 may be driven by processor 134. The cache controller 145 may include a write command receiving circuit 1450, an available space checking circuit 1451, a mode determining circuit 1452, a counting circuit 1453, and first and

second update circuits

1455 and 1455.

Referring to fig. 5, since the write command receiving circuit 1450, the available space checking circuit 1451, the mode determining circuit 1452, and the counting circuit 1453 are the same as those described above according to the first embodiment, a description thereof is omitted. The first update circuit 1455\ u 1 and the second update circuit 1455_2 are described below.

After the mode determination circuit 1452 determines that the first LBA information and the second LBA information are sequential modes, when the LBA information received from the command queue by the write command reception circuit 1450 is random LBA information, the first update circuit 1455\u1 updates only the plurality of pieces of LBA information included in the zeroth mapping segment S0 to the memory device 150. In other words, the first update circuit 1455_1 updates only LBA information that is the size of the zeroth mapped segment S0 (e.g., 18 KB) to the memory device 150. Subsequently, the first update circuit 1455\ u 1 changes the zeroth mapped segment S0 to the first mapped segment S1 by deleting information of the zeroth mapped segment S0. In other words, the zeroth mapped segment S0 and the first mapped segment S1 are the same region.

The second update circuit 1455\ u 2 may perform updating by generating LBA information corresponding to the LBA count based on the order count list stored in the count circuit 1453 and writing the generated LBA information to a mapped segment area corresponding to the first mapped segment S1.

Fig. 6 is a flowchart for describing an operation method of the memory system 110 according to the first embodiment. The method of operation of fig. 6 may be performed by a memory system 110 including the cache controller 145 of fig. 1 and 4A-4B.

Referring to fig. 6, the cache controller 145 may request command information including a plurality of pieces of command information from the command queue and receive the requested one or more pieces of command information from the command queue in step S601. For example, the plurality of pieces of command information may include a write command or a read command. Further, the plurality of pieces of command information may include a write command. Also, the plurality of pieces of command information may include first to fourth write commands. Cache controller 145 may request and sequentially receive write commands from the command queue.

In steps S603 and S605, in order to write the LBA information included in the first write command to the mapped segment region corresponding to the zeroth mapped segment S0, the cache controller 145 may check an available space of a region corresponding to the zeroth mapped segment S0 (i.e., a mapped segment region). Cache controller 145 may check the available space of the mapped segment area corresponding to zeroth mapped segment S0 by checking whether LBA information is written to the mapped segment area corresponding to zeroth mapped segment S0 in the size of zeroth mapped segment S0. In other words, the cache controller 145 may check the available space of the mapped segment region corresponding to the zeroth mapped segment S0 by checking whether the location of the first LBA information written before the second LBA information indicates Max _ INDEX allocated to the mapped segment region corresponding to the zeroth mapped segment S0.

When the check result shows that the location where the first LBA information is written does not indicate Max _ INDEX of the mapped segment area corresponding to the zeroth mapped segment S0 (i.e., no in step S605), the cache controller 145 may write the second LBA information corresponding to the first write command to the mapped segment area corresponding to the zeroth mapped segment S0 in step S607. On the other hand, when the check result shows that the position where the first LBA information is written indicates Max _ INDEX of the mapped segment region corresponding to the zeroth mapped segment S0 (i.e., yes in step S605), the cache controller 145 may determine the patterns of the first LBA information written to Max _ INDEX of the mapped segment region corresponding to the zeroth mapped segment S0 and the second LBA information currently to be written corresponding to the first write command in steps S609 and S611.

When the determination result indicates that the mode of the first LBA information and the second LBA information is the sequential mode (i.e., yes in step S611), the cache controller 145 may increase the sequence count in step S613. For example, as shown in fig. 4A, when the first LBA information written to Max _ INDEX of the mapping segment region corresponding to the zeroth mapping segment S0 is LBA1001 and the second LBA information corresponding to the first write command is LBA1002, the cache controller 145 may determine that the patterns of the first LBA information and the second LBA information are sequential patterns and increase the sequential count. When the steps S601 to S609 are repeatedly performed a set or predetermined number of times until the patterns of the first LBA information and the second LBA information become random patterns, the order count may be increased at each iteration.

On the other hand, as shown in fig. 4B, when the determination result indicates that the patterns of the first LBA information and the second LBA information are random patterns (i.e., no in step S611), the cache controller 145 may check the order count list in step S617, and then update only the plurality of pieces of LBA information written to the mapping segment area corresponding to the zeroth mapping segment into the memory device 150 in a case where the order count list has no count information.

In step S617, when the check result of the order count list shows that the order count list has count information, the cache controller 145 may generate one or more pieces of LBA information consecutive to the LBA information written to Max _ INDEX of the mapped segment area corresponding to the zeroth mapped segment S0 based on the count information. Subsequently, cache controller 145 may merge the generated one or more pieces of LBA information with zeroth mapped segment S0, thereby updating memory device 150.

Fig. 7 is a flowchart showing an operation method of the memory system according to the second embodiment. The method of operation of fig. 7 may be performed by a memory system 110 that includes the cache controller 145 of fig. 1 and 5.

Referring to fig. 7, since steps S701 to S713 are the same as steps S601 to S613 described above with reference to fig. 6, a description thereof is omitted.

In step S717, when the determination result of step S711 indicates that the pattern of the first LBA information and the second LBA information is the random pattern, the cache controller 145 may check the order count list. When the order count list has no count information, the cache controller 145 may update only the plurality of pieces of LBA information written to the mapped segment area corresponding to the zeroth mapped segment to the memory device 150. On the other hand, when the order count list has the count information, the cache controller 145 may update only the plurality of pieces of LBA information written to the mapped segment area corresponding to the zeroth mapped segment to the memory device 150 and then delete the plurality of pieces of LBA information written to the mapped segment area corresponding to the zeroth mapped segment in step S719. In step S721, the cache controller 145 may change the zeroth mapped segment to the first mapped segment. In step S723, the cache controller 145 may generate one or more pieces of LBA information consecutive to the LBA information written to Max _ INDEX of the mapped segment region corresponding to the zeroth mapped segment S0 based on the count information, and write the generated LBA information into the first mapped segment.

Fig. 8 illustrates a plurality of memory dies 1501 to 150n included in the memory device 150 of fig. 1 among components of the memory system 110 according to an embodiment. For example, memory device 150 may include a first memory die 1501 and a second memory die 1502.

Each of the first memory die 1501 and the second memory die 1502 may include multiple planes. For example, the first memory die 1501 may include a first PLANE plan 00 and a second PLANE plan 01, and the second memory die 1502 may include a third PLANE plan 10 and a fourth PLANE plan 11. Each of the planes may include a plurality of blocks. For example, the first PLANE plan 00 may include first to nth memory BLOCKs BLOCK000 to BLOCK 00N, and the second PLANE plan 01 may include first to nth memory BLOCKs BLOCK010 to BLOCK 01N. The third PLANE plan 10 may include first to nth memory BLOCKs BLOCK100 to BLOCK 10N, and the fourth PLANE plan 11 may include first to nth memory BLOCKs BLOCK110 to BLOCK 11N.

The first memory die 1501 can input/output data through the zeroth channel CH0, and the second memory die 1502 can input/output data through the first channel CH 1. The zeroth channel CH0 and the first channel CH1 may input/output data in an interleaving scheme.

The first memory die 1501 includes a plurality of PLANEs planet 00 and planet 01 corresponding to a plurality of lanes WAY0 and WAY1, respectively, which lanes WAY0 and WAY1 are capable of inputting/outputting data in an interleaving scheme by sharing a zeroth channel CH 0.

The second memory die 1502 includes a plurality of planar planet 10 and planet 11 corresponding to a plurality of lanes WAY2 and WAY3, respectively, the lanes WAY2 and WAY3 being capable of inputting/outputting data in an interleaving scheme by sharing the first channel CH 1.

The multiple memory blocks in memory device 150 may be divided into groups based on physical location using the same way or channel.

Although the embodiment of fig. 8 shows a configuration in which there are two dies, each die having two planes of memory devices 150, the invention is not limited to this configuration. Any suitable die and plane configuration may be used based on system design considerations. The number of memory blocks in each plane may also vary.

The controller 130 may group a plurality of memory blocks that can be simultaneously selected among the plurality of memory blocks in different dies or different planes based on physical locations of the memory blocks, and manage the group of memory blocks as a super memory block.

The scheme of the controller 130 grouping the memory blocks into the super memory blocks and managing the super memory blocks may be performed in various ways according to the designer's selection. Three exemplary schemes are described below.

The first scheme is that the controller 130 groups an arbitrary BLOCK000 of the first PLANE plan 00 and an arbitrary BLOCK010 of the second PLANE plan 01 of the first memory die 1501 of the plurality of memory dies 1501 and 1502 in the memory device 150, and manages the grouped BLOCKs BLOCK000 and BLOCK010 as a single super BLOCK A1. When the first scheme is applied to the second memory die 1502 in the memory device 150, the controller 130 may group the arbitrary memory BLOCK100 of the first PLANE plan 10 and the arbitrary memory BLOCK110 of the second PLANE plan 11 of the second memory die 1502, and manage the grouped memory BLOCKs BLOCK100 and BLOCK110 as a single super memory BLOCK A2.

The second scheme is that the controller 130 groups the arbitrary BLOCK002 of the first PLANE plan 00 of the first memory die 1501 and the arbitrary BLOCK102 of the first PLANE plan 10 of the second memory die 1502, and manages the grouped BLOCKs BLOCK002 and BLOCK102 as a single super BLOCK B1. In addition, according to the second scheme, the controller 130 groups the arbitrary BLOCK012 of the second PLANE plan 01 of the first memory die 1501 and the arbitrary BLOCK112 of the second PLANE plan 11 of the second memory die 1502, and manages the grouped BLOCKs BLOCK012 and BLOCK112 as the single super BLOCK B2

The third scheme is that controller 130 groups any memory BLOCK001 of first PLANE plan 00 of first memory die 1501, any memory BLOCK011 of second PLANE plan 01 of first memory die 1501, any memory BLOCK101 of first PLANE plan 10 of second memory die 1502, and any memory BLOCK111 of second PLANE plan 11 of second memory die 1502, and manages the grouped memory BLOCKs BLOCK001, BLOCK011, BLOCK101, and BLOCK111 as a single super memory BLOCK C.

Thus, the simultaneously selectable memory blocks included in each of the super memory blocks may be selected substantially simultaneously by an interleaving scheme, such as a channel interleaving scheme, a memory die interleaving scheme, a memory chip interleaving scheme, or a lane interleaving scheme.

According to an embodiment of the present invention, the size of the mapped segment may be variably adjusted and updated to the memory device based on the patterns of the first and second LBA information, thereby reducing the number of updates to the memory device.

While the invention has been illustrated and described with respect to specific embodiments, it will be apparent from the foregoing to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention as defined in the following claims.

Claims

1. A memory system, comprising:

a controller comprising one or more processors; and

a storage device comprising a plurality of storage blocks,

wherein the controller comprises:

a command receiving circuit that receives a first write command from a command queue;

a storage space check circuit that checks whether there is an available storage space in a zeroth mapped segment region using the location of first logical block address information, i.e., first LBA information, written to the zeroth mapped segment region;

a pattern determination circuit that determines a pattern of the first LBA information and second LBA information corresponding to the first write command when the available storage space does not exist in the zeroth mapped segment region;

a counting circuit that increases a sequence count when a determination result of the mode determination circuit indicates that the mode of the first LBA information and the second LBA information is a sequential mode;

an LBA generation circuit that generates one or more pieces of LBA information based on the sequence count; and

an update circuit that performs a mapping update operation on a memory block of the memory device by variably adjusting a size of the zeroth mapped segment region based on the one or more pieces of LBA information.

2. The memory system of claim 1, wherein the first LBA information includes previous LBA information of LBA information currently to be written, and the second LBA information includes LBA information currently to be written.

3. The memory system of claim 1, wherein the storage space checking circuit determines that the available storage space is not present in the zeroth mapped segment region when the location of the first LBA information written to the zeroth mapped segment region corresponds to a last index of the zeroth mapped segment region, and determines that the available storage space is present in the zeroth mapped segment region when the location of the first LBA information written to the zeroth mapped segment region does not correspond to the last index.

4. The memory system according to claim 1, wherein when a check result of the storage space check circuit indicates that the available storage space exists in the zeroth mapped segment region, the update circuit updates the zeroth mapped segment region by writing the second LBA information corresponding to the first write command to the zeroth mapped segment region.

5. The memory system of claim 1, wherein the update circuit updates the zeroth mapped segment region to a storage block of the memory device when the mode determination circuit determines that a mode of the first LBA information written to the zeroth mapped segment region and the second LBA information corresponding to the first write command is a random mode.

6. The memory system of claim 1, wherein the pattern determination circuit determines a pattern of the first LBA information and the second LBA information until the first LBA information and the second LBA information are random patterns.

7. The memory system according to claim 6, wherein when the mode determination circuit determines that the mode of the first LBA information and the second LBA information is a random mode, the update circuit performs the map update operation on the memory block by variably adjusting a size of the zeroth map segment region based on the one or more pieces of LBA information.

8. The memory system according to claim 1, wherein the variably adjusted size of the zeroth mapped segment region is obtained by merging the zeroth mapped segment region with the one or more pieces of LBA information generated based on the order count.

9. A method of operation of a memory system, the memory system including a controller and a memory device, the controller including one or more processors and the memory device including a plurality of memory blocks, the method of operation comprising:

receiving a first write command;

checking whether there is an available storage space in a zeroth mapped segment region using first logical block address information, i.e., a location of first LBA information, written to the zeroth mapped segment region;

determining a pattern of the first LBA information and second LBA information corresponding to the first write command when the available storage space does not exist in the zeroth mapped segment region;

increasing a sequence count of the second LBA information when the mode of the first LBA information and the second LBA information is determined to be a sequential mode;

performing a mapping update operation on a memory block of the memory device by variably adjusting a size of the zeroth mapping segment area based on one or more pieces of LBA information.

10. The operating method according to claim 9, wherein the first LBA information includes previous LBA information of LBA information to be currently written, and the second LBA information includes LBA information to be currently written.

11. The method of operation of claim 9, wherein checking whether the available storage space exists in the zeroth mapped segment region comprises:

determining that the available storage space does not exist in the zeroth mapped segment region when the location of the first LBA information written to the zeroth mapped segment region corresponds to the last index of the zeroth mapped segment region; and is provided with

Determining that the available storage space exists in the zeroth mapped segment region when the location of the first LBA information written to the zeroth mapped segment region does not correspond to the last index.

12. The operating method according to claim 9, wherein when a result of checking the available storage space of the zeroth mapped segment region indicates that the available storage space exists in the zeroth mapped segment region, the controller updates the zeroth mapped segment region by writing the second LBA information corresponding to the first write command to the zeroth mapped segment region.

13. The operation method according to claim 9, wherein the zeroth mapped segment region is updated to a storage block of the memory device when the pattern of the first LBA information written to the zeroth mapped segment region and the second LBA information corresponding to the first write command is determined to be a random pattern.

14. The method of operation of claim 9, wherein the controller determines a pattern of the first LBA information and the second LBA information until the first LBA information and the second LBA information are a random pattern.

15. The operating method according to claim 14, wherein when the pattern of the first LBA information and the second LBA information is a random pattern, the controller performs the map update operation on the storage block by variably adjusting the size of the zeroth map segment region based on the one or more pieces of LBA information.

16. The operating method according to claim 9, wherein during the map update operation, the zeroth mapped segment region is variably sized by merging the zeroth mapped segment region with the one or more pieces of LBA information generated based on the order count.

17. A method of operation of a memory system, the memory system comprising a controller and a memory device, the controller comprising one or more processors; the memory device includes a plurality of memory blocks, the method of operation including:

receiving a first write command;

determining a pattern of the first LBA information written to the zeroth mapped segment region and second LBA information corresponding to the first write command when the available storage space does not exist in the zeroth mapped segment region;

increasing the sequence count of the second LBA information until the pattern of the first LBA information and the second LBA information is a random pattern;

updating the zeroth mapping segment area to a storage block when the pattern of the first LBA information and the second LBA information is a random pattern; and

changing the zeroth mapped segment area to a first mapped segment area, generating one or more pieces of LBA information based on the order count, and writing the generated one or more pieces of LBA information to the first mapped segment area.

18. The operating method of claim 17, wherein the first LBA information includes previous LBA information of LBA information currently to be written, and the second LBA information includes LBA information currently to be written.

19. A memory system, comprising:

a memory device comprising a plurality of memory blocks; and

a controller including a memory and a cache controller that stores logical block address information, i.e., LBA information, in the memory and updates the LBA information to the memory device;

wherein the cache controller:

receiving a plurality of pieces of LBA information and storing the plurality of pieces of LBA information in the memory;

generating a mapping segment including some of the pieces of LBA information;

determining a pattern of a last piece of LBA information in the mapped segment in the list and another piece of LBA information received after the last piece of LBA information; and

updating the mapped segment or both the mapped segment and the list to a selected block among the plurality of storage blocks based on the determined pattern.