CN111064493A - Output peak value bit synchronization processing method under low SNR high dynamic environment - Google Patents
Output peak value bit synchronization processing method under low SNR high dynamic environment Download PDFInfo
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Abstract
The invention belongs to the technical field of spread spectrum communication, and discloses an output peak value bit synchronization processing method under a low SNR high dynamic environment. Frame existence detection adopts a secondary FFT accumulation mode, and FFT is carried out by backward sliding at intervals of integral multiples of the length of the non-spread spectrum code; and setting a decision threshold to carry out capture decision, wherein if the maximum value of the FFT output is greater than the threshold, the capture is successful. The bit synchronization adopts a method of finding the maximum peak value by a sliding window, namely FFT is carried out at two phase points before and after the capture position at intervals, 1 FFT is carried out in each sliding, and then the maximum value of the 4 FFT output peak values and the corresponding position thereof are solved, thereby determining the bit synchronization position. The synchronization method realized by adopting the optimized quadratic FFT accumulation technology not only can adapt to the low SNR high dynamic environment, but also greatly reduces the operation complexity.
Description
Technical Field
The invention belongs to the technical field of spread spectrum communication, and particularly relates to a method for synchronously processing output peak values in a low-SNR high-dynamic environment.
Background
Currently, the closest prior art: spread Spectrum Communication (Spread Spectrum Communication) is a Communication technology developed in 40 to 50 years of the 20 th century, and Spread Spectrum Communication overcomes the defects in the conventional Communication transmission technology in a unique signal transmission mode, so that the Spread Spectrum Communication occupies an important position in the Communication field. The synchronization technology of spread spectrum communication is one of the most important technologies of a spread spectrum receiver, and the synchronization of spread spectrum signals is generally divided into two processes of coarse synchronization and fine synchronization. Coarse synchronization is referred to as acquisition of a spread spectrum signal and aims to quickly detect the presence of the signal and find the correct phase and frequency with minimal hardware. Fine synchronization is referred to as frame synchronization and tracking of spread spectrum signals, i.e., after the acquisition process is completed, the start position of the frame is determined and the frequency and phase of the change are tracked. In a low snr environment, the synchronization process often consumes a lot of hardware resources and time. Therefore, a reliable synchronization algorithm is of great significance for improving the performance of the spread spectrum system.
The traditional spread spectrum signal acquisition adopts a serial-parallel combination mode, and most of the traditional spread spectrum signal acquisition methods adopt a serial/parallel search method. Chawla and d.v.sargate propose pseudo code parallel acquisition schemes with baseband signal processing in Direct Sequence Spread Spectrum (DSSS) systems. With the continuous development of software radio, people are focusing on the FFT-based code acquisition method. It was first proposed to use FFT for code acquisition, specifically using serial/parallel FFT correlators. The latter scholars propose a code capture method of segment correlation, and pay the cost of sacrificing the signal-to-noise ratio output by a correlator to well adapt to a high-dynamic environment. In recent years, the technology of acquiring pseudo codes based on FFT frequency domain correlation is also a hot point of research. Some researchers also propose to use wavelet transform, adaptive filtering and other methods to realize code capture, but the method is only limited to theoretical research and is not realized yet. In the field of code tracking technology, early studies were performed by spiker and Magill, which propose to obtain an error signal of a tracking loop from a correlation operation of a received signal at a receiving end and a first derivative of a spread spectrum signal. Subsequent researchers have conducted more detailed studies on the work of spiker and Magill, and have presented various tracking loops currently in use, wherein the Delay Locked Loop (DLL) technology is currently the most mature, but has a certain circuit complexity, and particularly, the leading and lagging associated branches in the discriminator must be precisely balanced.
Regarding the acquisition of spread spectrum signals, some documents also propose a quadratic FFT accumulation method, which can obtain better accumulation effect and can be more suitable for the environment with low signal-to-noise ratio and large doppler shift compared with the traditional acquisition method. However, if the FFT is performed continuously, i.e. the FFT is performed point by point, the FFT is performed once when one sampling point slides, and each FFT operation is time-consuming and cannot be completed within the time of one sampling point, so that the requirement of synchronization instantaneity cannot be met. The requirement of the computation time is limited, a plurality of FFTs are needed to be computed in parallel, however, the computation complexity of parallel FFT is multiplied, and more hardware resources are occupied, which will have a serious influence on the performance of the synchronous system. Therefore, how to redesign a synchronization head structure, optimize and improve the method, and greatly reduce the complexity is a main problem of the invention.
In summary, the problems of the prior art are as follows: the existing secondary FFT accumulation method for continuously sliding FFT takes long time and cannot meet the real-time requirement; the parallel FFT operation occupies more hardware resources, and the complexity is relatively high.
The difficulty of solving the technical problems is as follows: because the principle of the existing quadratic FFT accumulation method is to take the FFT of the correlation value and find the maximum value, it is not practical to reduce the computation complexity of the FFT itself, but the higher computation complexity caused by parallel FFT is not easy to reduce. Therefore, how to avoid using parallel FFT operation under the requirement of synchronization real-time property is satisfied, and the purpose of reducing the complexity of the whole operation is achieved, which becomes the difficult point to be solved by the invention.
The significance of solving the technical problems is as follows: the design of a wireless communication system needs to consider a lot of factors, wherein the real-time performance of the algorithm and the operation complexity of the algorithm are two important factors, and if the real-time performance of the algorithm does not meet the requirement, the system cannot work normally; if the arithmetic complexity of the algorithm is too high, the system is difficult to realize. Therefore, the existing synchronization technology and algorithm are improved and optimized, so that the complexity is greatly reduced on the premise of meeting the real-time requirement, the practical value of the method is improved, and the method has great significance.
Disclosure of Invention
Aiming at the problems in the prior art, the invention provides an output peak value bit synchronization processing method under a low SNR high dynamic environment.
The invention is realized in such a way that the output peak bit synchronization processing method under the low SNR high dynamic environment comprises the following steps:
firstly, frame existence detection adopts a secondary FFT accumulation mode, and FFT is carried out by backward sliding at intervals of integral multiples of the length of a non-spread spectrum code; and setting a decision threshold to carry out capture decision, wherein if the maximum value of the FFT output is greater than the threshold, the capture is successful.
And secondly, the bit synchronization adopts a method of finding the maximum peak value by a sliding window, FFT is performed at two phase points before and after the capture position in an interval sliding mode, 1 FFT is performed in each sliding mode, the maximum value of the 4 FFT output peak values and the corresponding position of the 4 FFT output peak values are solved, and the bit synchronization position is determined.
Further, the first-step frame presence detection specifically includes:
(1) the receiving end carries out 8-phase quantization on the received spread spectrum signals, namely, the signals in different angle ranges are respectively mapped to 8 phases, and then the quantized signals are despread to obtain correlation values; the correlation value is obtained by the following formula:
wherein corr (j) represents the correlation value after despreading, and R represents the correlation value after 8 phasesBit-quantized spread spectrum signal, PPNRepresenting a spread spectrum code, wherein P is an upsampling multiple, i is a sampling point position for receiving a spread spectrum signal R, and j is a despreading sliding position;
(2) for the despread correlation value, a quadratic FFT accumulation mode is adopted; the FFT window takes L multiplied by P +1 sampling points as intervals, the sampling points sequentially slide backwards, and 1 FFT is carried out during each sliding;
(3) setting a decision threshold sigma according to the peak value size of the FFT output sequence0And makes an acquisition decision.
Further, in the secondary FFT accumulation mode, L × P sampling points are used as intervals (L is the length of the spreading code, and P is an upsampling multiple), and M correlation values are taken as M-point FFTs and the maximum value is calculated.
Further, the method for capturing the decision comprises: when the accumulated peak value is larger than the judgment threshold sigma0When the acquisition is successful, recording the acquisition position; otherwise, the FFT window slides backwards once to repeat the steps.
Further, the second bit synchronization specifically includes:
(1) searching 4 spreading codes backward from the capture position, namely sliding the FFT window backward for 4 times from the capture position, performing 1 FFT for each time, and respectively setting the starting points of 4 times as the front and rear phase points of the capture position;
(2) taking numbers at intervals of L multiplied by P sampling points for each sliding to perform M-point FFT and solve the maximum value, selecting the maximum value max _ v (n) for 4 times, and recording the maximum value position max _ n (n), wherein the position synchronization position is
At this point, bit synchronization is complete.
Furthermore, the starting points of the 4-time sliding of the FFT window are two phase points before and after the capture position, respectively, that is, the interval of the 1 st sliding of the FFT window is L × P-2, the interval of the 2 nd sliding is L × P +1, the interval of the 3 rd sliding is L × P +2, and the interval of the 4 th sliding is L × P + 1.
Another object of the present invention is to provide an output peak bit synchronization processing system under a low SNR high dynamic environment, in which the output peak bit synchronization processing method under a low SNR high dynamic environment according to an embodiment of the present invention includes:
the frame existence detection module is used for sliding backwards at intervals of integral multiples of the length of the non-spread spectrum code to perform FFT in a secondary FFT accumulation mode; setting a decision threshold to carry out capture decision, and if the maximum value of the FFT output is greater than the threshold, the capture is successful;
and the bit synchronization module is used for adopting a method of finding the maximum peak value by a sliding window, starting to perform FFT at two phase points before and after the capturing position at intervals, performing 1 FFT in each sliding, solving the maximum value of the 4 FFT output peak values and the corresponding position thereof, and determining the bit synchronization position.
Another objective of the present invention is to provide an application of the output peak bit synchronization processing method in the positioning spread spectrum communication under the low SNR high dynamic environment.
Another objective of the present invention is to provide an application of the output peak bit synchronization processing method in the ranging spread spectrum communication under the low SNR high dynamic environment.
Another object of the present invention is to provide a wireless communication system of an output peak bit synchronization processing method in a low SNR high dynamic environment.
In summary, the advantages and positive effects of the invention are: the invention adopts the frequency domain FFT capturing algorithm, has better peak accumulation effect and capturing performance than the traditional time domain capturing algorithm, and can adapt to the environment with low signal-to-noise ratio and large Doppler frequency shift. Compared with the existing continuous sliding quadratic FFT accumulation algorithm, the invention adopts the quadratic FFT accumulation algorithm of non-spread spectrum code length integral multiple interval sliding, effectively reduces the complexity of the synchronization process, improves the synchronization efficiency and has better synchronization performance.
Drawings
Fig. 1 is a flowchart of an output peak bit synchronization processing method under a low SNR high dynamic environment according to an embodiment of the present invention.
Fig. 2 is a flow chart of a frame presence detection process provided by an embodiment of the present invention.
Fig. 3 is a schematic diagram of 8-phase quantization according to an embodiment of the present invention.
Fig. 4 is a flow chart of a bit synchronization process provided by an embodiment of the invention.
Fig. 5 is a schematic diagram of a synchronization frame structure according to an embodiment of the present invention.
Fig. 6 is a schematic drawing of the acquisition algorithm provided in the embodiment of the present invention.
Fig. 7 is a schematic diagram of FFT window sliding of the acquisition algorithm provided by the embodiment of the present invention.
Fig. 8 is a schematic diagram of the fetching and FFT window sliding of the bit synchronization algorithm according to the embodiment of the present invention.
FIG. 9 is a graph of accumulated peak contrast using the continuous sliding method and the acquisition method of the present invention, respectively, as provided by an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail with reference to the following embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
In view of the problems in the prior art, the present invention provides a method for processing output peak bits in a low SNR high dynamic environment, which is described in detail below with reference to the accompanying drawings.
As shown in fig. 1, the method for processing output peak bits in a low SNR high dynamic environment according to an embodiment of the present invention includes the following steps:
s101: frame existence detection adopts a secondary FFT accumulation mode, and FFT is carried out by backward sliding at intervals of integral multiples of the length of the non-spread spectrum code; and setting a decision threshold to carry out capture decision, wherein if the maximum value of the FFT output is greater than the threshold, the capture is successful.
S102: and the bit synchronization adopts a method of finding the maximum peak value by a sliding window, FFT is performed at two phase points before and after the capture position at intervals in a sliding manner, 1 FFT is performed in each sliding manner, the maximum value of the 4 FFT output peak values and the corresponding position of the maximum value are solved, and the bit synchronization position is determined.
The technical solution of the present invention is further described below with reference to the accompanying drawings.
The method for synchronously processing the output peak value bits in the low-SNR high-dynamic environment comprises the following steps:
first step, frame presence detection (fig. 2):
1. the receiving end performs 8-phase quantization on the received spread spectrum signal, that is, the signals in different angle ranges are mapped to 8 phases (fig. 3) respectively, and then despreads the quantized signal to obtain a correlation value. The correlation value is obtained by the following formula:
wherein corr (j) represents a despread correlation value, R represents a spread spectrum signal subjected to 8-phase quantization, and PPNRepresenting a spread spectrum code, wherein P is an upsampling multiple, i is a sampling point position for receiving a spread spectrum signal R, and j is a despreading sliding position;
2. and for the despread correlation values, a quadratic FFT accumulation mode is adopted, and L multiplied by P sampling points are taken as intervals (L is the length of the spreading code, and P is an upsampling multiple), M correlation values are taken as M-point FFT, and the maximum value is calculated. The FFT window takes LxP +1 (integral multiple of the length of the non-spread spectrum code) sampling points as intervals, and slides backwards in sequence, and each sliding is performed with 1 FFT.
3. Setting a decision threshold sigma according to the peak value size of the FFT output sequence0And performing acquisition judgment: when the accumulated peak value is larger than the judgment threshold sigma0When the acquisition is successful, recording the acquisition position; otherwise, the FFT window slides backwards once to repeat the steps.
Second, bit synchronization (fig. 4):
1. and searching 4 spreading codes backward from the acquisition position, namely sliding the FFT window backward for 4 times from the acquisition position, performing 1 FFT for each time, wherein the starting points of the 4 times are two phase points before and after the acquisition position respectively. Thus, the FFT window has a 1 st sliding interval of L × P-2, a 2 nd sliding interval of L × P +1, a 3 rd sliding interval of L × P +2, and a 4 th sliding interval of L × P + 1.
2. Taking numbers at intervals of L multiplied by P sampling points for each sliding to perform M-point FFT and solving the maximumSelecting the maximum value max _ v (n) for 4 times, and recording the maximum value position max _ n (n), namely the position synchronous position
At this point, bit synchronization is complete.
The technical effects of the present invention will be described in detail with reference to simulations.
The synchronous frame structure in the simulation test is shown in fig. 5, and in consideration of the influence of frequency offset, a spreading code with a length of 16 is selected, and in order to ensure the accumulation performance, the window length of the secondary FFT accumulation is 256, that is, 256 segments of spreading codes are accumulated. Thus, the synchronization header consists of 256+64 in-phase PN codes (16 bits) for acquisition and bit synchronization, followed by a data segment, i.e., the useful spread spectrum signal.
The system simulation parameters are as follows:
the spreading code length L is 16, the upsampling multiple P is 4, the FFT point number M is 256, and the reserved spreading code number N' is 64.
Fig. 6 shows a schematic diagram of the fetching of the capturing algorithm in the embodiment of the present invention, as can be seen from fig. 6, the correlation values are fetched at intervals of 16 symbols (i.e. 64 lengths), 256 FFT points are performed for 256 correlation values each time, and the maximum value is obtained, and the thick vertical line at the same height in the diagram represents a single fetching; unlike the continuous sliding method, in the embodiment of the present invention, the FFT window is slid backward at intervals of 16 × 4+1 to 65 samples, and one FFT is performed for each sliding. The FFT window sliding diagram is shown in fig. 7.
The search range for bit synchronization is 4 spreading codes. The FFT window slides backwards 4 times from the capture position, 1 FFT is carried out in each sliding, and the starting points of the 4 times are two phase points before and after the capture position respectively. As shown in fig. 8, in the embodiment of the present invention, the FFT window of the bit synchronization has an interval of 62 for the 1 st sliding, an interval of 65 for the 2 nd sliding, an interval of 66 for the 3 rd sliding, and an interval of 65 for the 4 th sliding; each sliding is counted at intervals of 64 samples to perform a 256-point FFT and maximize the value. The thick vertical lines in fig. 8 with different numbers and their corresponding different heights represent different phase points: -2 denotes that the capture position leads by 2 phase points, -1 denotes that the capture position leads by 1 phase point,0 represents the capture position, 1 represents the capture position lagging by 1 phase position, and 2 represents the capture position lagging by 2 phase positions. Then, the maximum value max _ v (n) is selected 4 times, and the maximum value position max _ n (n) is recorded, and the bit synchronization position can be represented by the formula
And (4) determining.
FIG. 9 shows a comparison of accumulated peaks for an embodiment of the present invention using a continuous sliding method and an embodiment of the present invention using a capture method. As can be clearly seen from the simulation diagram, the method of the present invention can be regarded as equal-interval sampling of the continuous sliding output peak value, and thus, the operation complexity is greatly reduced. The embodiment of the invention has higher capturing probability through multiple times of simulation under the conditions of low SNR and large Doppler frequency shift, the bit synchronization position is basically stabilized at a fixed value, and from the simulation result, the capturing algorithm adopted by the invention has better accumulation effect and relatively lower operation complexity.
In summary, the low complexity synchronization method under the low SNR high dynamic environment provided by the present invention effectively reduces the complexity of the synchronization process by adopting the quadratic FFT accumulation algorithm of non-spreading code length integral multiple interval sliding; the bit synchronization adopts a method of finding the maximum peak value by a sliding window, improves the synchronization precision, has better synchronization performance, and provides an efficient and reliable solution for the application of the method.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.
Claims (10)
1. An output peak bit synchronization processing method under a low SNR high dynamic environment is characterized by comprising the following steps:
firstly, frame existence detection adopts a secondary FFT accumulation mode, and FFT is carried out by backward sliding at intervals of integral multiples of the length of a non-spread spectrum code; setting a decision threshold to carry out capture decision, and if the maximum value of the FFT output is greater than the threshold, the capture is successful;
secondly, the maximum peak value is found by adopting a sliding window method in the bit synchronization, FFT is performed at two phase points before and after the capture position in an interval sliding mode, and 1 FFT is performed in each sliding mode; and then solving the maximum value and the corresponding position of the 4 FFT output peak values to determine the bit synchronization position.
2. The method according to claim 1, wherein the detecting the existence of the first frame step specifically comprises:
(1) the receiving end carries out 8-phase quantization on the received spread spectrum signals, namely, the signals in different angle ranges are respectively mapped to 8 phases, and then the quantized signals are despread to obtain correlation values; the correlation value is obtained by the following formula:
wherein corr (j) represents a despread correlation value, R represents a spread spectrum signal subjected to 8-phase quantization, and PPNRepresenting a spread spectrum code, wherein P is an upsampling multiple, i is a sampling point position for receiving a spread spectrum signal R, and j is a despreading sliding position;
(2) for the despread correlation value, a quadratic FFT accumulation mode is adopted; the FFT window takes L multiplied by P +1 sampling points as intervals, the sampling points sequentially slide backwards, and 1 FFT is carried out during each sliding;
(3) setting a decision threshold sigma according to the peak value size of the FFT output sequence0And makes an acquisition decision.
3. The method as claimed in claim 2, wherein the quadratic FFT accumulation method takes L × P samples as intervals (L is the length of the spreading code, and P is an upsampling multiple), and takes M correlation values as M-point FFT to obtain the maximum value.
4. As claimed in claim2, the output peak bit synchronization processing method under the low SNR high dynamic environment is characterized in that the method for capturing the decision is as follows: when the accumulated peak value is larger than the judgment threshold sigma0When the acquisition is successful, recording the acquisition position; otherwise, the FFT window slides backwards once to repeat the steps.
5. The method according to claim 1, wherein the second bit synchronization step specifically comprises:
(1) searching 4 spreading codes backward from the capture position, namely sliding the FFT window backward for 4 times from the capture position, performing 1 FFT for each time, and respectively setting the starting points of 4 times as the front and rear phase points of the capture position;
(2) taking numbers at intervals of L multiplied by P sampling points for each sliding to perform M-point FFT and solve the maximum value, selecting the maximum value max _ v (n) for 4 times, and recording the maximum value position max _ n (n), wherein the position synchronization position is
At this point, bit synchronization is complete.
6. The method according to claim 5, wherein the starting points of the 4 sliding in the FFT window are two phase points before and after the capture position, respectively, i.e. the interval of the FFT window for the 1 st sliding is lxp-2, the interval of the FFT window for the 2 nd sliding is lxp +1, the interval of the FFT window for the 3 rd sliding is lxp +2, and the interval of the FFT window for the 4 th sliding is lxp + 1.
7. An output peak bit synchronization processing system under a low SNR high dynamic environment, for implementing the output peak bit synchronization processing method under a low SNR high dynamic environment according to any one of claims 1 to 6, wherein the output peak bit synchronization processing system under a low SNR high dynamic environment comprises:
the frame existence detection module is used for sliding backwards at intervals of integral multiples of the length of the non-spread spectrum code to perform FFT in a secondary FFT accumulation mode; setting a decision threshold to carry out capture decision, and if the maximum value of the FFT output is greater than the threshold, the capture is successful;
and the bit synchronization module is used for adopting a method of finding the maximum peak value by a sliding window, starting to perform FFT at two phase points before and after the capturing position at intervals, performing 1 FFT in each sliding, solving the maximum value of the 4 FFT output peak values and the corresponding position thereof, and determining the bit synchronization position.
8. An application of the output peak bit synchronization processing method in the low SNR high dynamic environment according to any one of claims 1 to 6 in the positioning spread spectrum communication.
9. Use of the output peak bit synchronization processing method according to any of claims 1 to 6 in a low SNR high dynamic environment for ranging spread spectrum communication.
10. A wireless communication system according to any one of claims 1 to 6, wherein the method for processing output peak bit synchronization under a low SNR high dynamic environment.
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