CN111046573A - Single-particle transient effect modeling method based on pulse transmission characteristics - Google Patents
Single-particle transient effect modeling method based on pulse transmission characteristics Download PDFInfo
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Abstract
The invention discloses a single-event transient effect modeling method based on pulse transmission characteristics, which considers the electrical masking effect and pulse widening effect of pulses in circuit transmission, models the pulses into a physical delay information representation formula of a circuit gate circuit, and adopts a quantization method to model the single-event transient effect, thereby establishing a single-event transient injection model suitable for hardware simulation and a single-event soft error rate analysis model facing a large-scale integrated circuit. The method can be used for evaluating the influence of the single-particle transient effect on a full circuit, carrying out single-particle transient effect analysis aiming at a large-scale integrated circuit and quickly and accurately evaluating the SER of the circuit.
Description
Technical Field
The invention belongs to the field of integrated circuit design of circuit fault injection and microelectronics, relates to an anti-irradiation reinforcement technology in avionics, and particularly relates to a design method of an integrated circuit special for aviation.
Background
Under the large-size process, soft errors caused by Single Event Transients (SETs) can be almost ignored due to the high working voltage, large device size and low working frequency of the circuit. However, as the process advances, the node capacitance of the device continues to decrease, the clock frequency increases, and so on, so that the propagation of the error pulse is easily latched by the sequential device to generate an error. Under the nanometer level process, the error pulse width caused by the single-particle transient effect can reach hundreds of picoseconds, and the clock cycles of circuits such as high-performance CPUs and the like are also in the same order of magnitude, so that the error pulse is easily captured by a storage device to form Soft Errors (SEs).
Aiming at large-scale integrated circuits, the international researchers provide a SET injection analysis method based on hardware simulation (Emulation), and the basic idea of the method is to realize a target Gate-level circuit in an FPGA (field Programmable Gate array), add a testable idea into a scan chain to perform SET injection on a full circuit and count the failure number of a final system, thereby measuring the reliability of the whole system.
Effective hardware simulation is generally achieved by using a quantitative characterization method of delay information of SETs and gates, which is proposed in the literature "L.Entrena, M.G.Valderas, R.F.Cardinal, et al.SETEmulation communication electronic mass Effects [ J ]. IEEE Trans.Sci., 2009,56(4): 2021-2025". However, the pulse Propagation process may generate phenomena of electrical masking, attenuation and broadening (PIPB), and the occurrence of the phenomena puts new requirements on a hardware simulation method, and characteristics of pulse transmission need to be accurately characterized in circuit simulation so as to be close to a real physical process. Therefore, developing an accurate and effective simulation method based on the transmission characteristics of the single-particle transient pulse becomes a key problem for reliability evaluation of deep submicron integrated circuits.
Disclosure of Invention
The invention aims to solve the problem that the existing single-event transient effect simulation model does not completely consider pulse transmission characteristics, and provides a single-event transient effect modeling method based on the pulse transmission characteristics.
The technical scheme of the invention is as follows: a single-particle transient effect modeling method based on pulse transmission characteristics comprises the following specific steps:
s1, determining delay information of each gate circuit according to process library information of a target circuit;
s2, selecting a time scale delta t as unit time, and then transmitting delay information t of any logic gatepCan use n
s3, characterizing Δ T in step S2 as Δ T in an amplification manner, where Δ T is m/f, m is 1,2,3, and f is an operating frequency of the FPGA hardware simulation system, and then the delay information of any logic gate in S2 can be quantized to n;
s4, establishing transmission characteristics between the SET pulse width and the transmission delay of the logic gate to represent electrical masking, attenuation and broadening characteristics in the pulse transmission process;
s5, delaying transmission by tpHLAnd tpLHRespectively carrying out quantization processing with the quantization clock period of delta T, namely the working clock of the hardware injection model, and summing the two transmission delays, wherein the summation result is TmaxWill [0, Tmax]Mapping to [0,2 ]n-1]When the rising edge of the input arrives, the counting is increased upwards from 0 until the full scale value and is kept unchanged; when a falling edge occurs, counting down from the existing value to the minimum value and keeping unchanged; when the count value is greater than the threshold value, a high level is output, and when the count value is less than the threshold value, a low level is output.
Further, the three transmission characteristics of electrical masking, attenuation, and broadening characteristics described in step S4 are specifically characterized as follows:
wherein, WinIs the SET pulse width, the maximum time required from the input signal crossing 50% VDD to the output signal crossing 50% VDD is the falling delay tpHL(ii) a Defining the change of output signal from 0 to 1In the process, 50% V is spanned from the input signalDDThe maximum time required for the output signal to cross 50% VDD is the rise delay tpLH，tpIndicating a change in the pulse, the propagation delay of the first edge, i.e. the output changing from 1 to 0, tp＝tpHL(ii) a Otherwise, t isp＝tpLH。
The invention has the beneficial effects that: the invention provides a quantitative model based on single event transient effect characteristics according to the transmission characteristics of SET pulses in an integrated circuit, constructs a hardware-implementable injection model for electrical masking and broadening effects in single event transient effect transmission, and provides a SET injection method suitable for hardware simulation.
Drawings
Fig. 1 is a diagram illustrating quantization of transmission delay according to an embodiment of the present invention.
Fig. 2 is a schematic diagram of three cases of single-event transient pulse transmission according to an embodiment of the present invention.
Fig. 3 is a flow chart of the hardware simulation implementation of the pulse transmission characteristics according to the embodiment of the present invention.
Fig. 4 is a schematic diagram of an application process of the embodiment of the present invention.
Detailed Description
The foregoing summary of the invention is described in further detail below with reference to specific embodiments.
It should not be understood that the scope of the above-described subject matter of the present invention is limited to the following examples. Various substitutions and alterations can be made without departing from the technical idea of the invention as described above, according to the common technical knowledge and conventional means in the field, and the scope of the invention is covered.
The modeling method of the single-event transient effect based on the pulse transmission characteristics comprises the following specific steps:
s1, determining delay information of each gate circuit according to process library information of a target circuit;
s2, selecting oneThe time scale Δ t is taken as unit time, the transmission delay information t of any logic gatepCan use n
s3, because the transmission delay is picosecond, the transmission delay is difficult to implement in hardware simulation, f is the operating frequency of the FPGA hardware simulation system, Δ T is m/f, m is 1,2,3, where Δ T is represented as Δ T in an amplification manner, and then the delay information quantization of any logic gate in S2 is also quantized to n;
s4, establishing transmission characteristics between the SET pulse width and the transmission delay of the logic gate to represent electrical masking, attenuation and broadening characteristics in the pulse transmission process;
s5, delaying transmission by tpHLAnd tpLHRespectively carrying out quantization processing with the quantization clock period of delta T, namely the working clock of the hardware injection model, and summing the two transmission delays, wherein the summation result is TmaxWill [0, Tmax]Mapping to [0,2 ]n-1]When the rising edge of the input arrives, the counting is increased upwards from 0 until the full scale value and is kept unchanged; when a falling edge occurs, counting down from the existing value to the minimum value and keeping unchanged; when the count value is greater than the threshold value, a high level is output, and when the count value is less than the threshold value, a low level is output.
Here, the transmission characteristic described in step S4 is specifically characterized as:
wherein, WinIs the SET pulse width, the maximum time required from the input signal crossing 50% VDD to the output signal crossing 50% VDD is the falling delay tpHL(ii) a In defining the change of the output signal from 0 to 1, the crossing of 50% V from the input signalDDThe maximum time required for the output signal to cross 50% VDD is the rise delay tpLH，tpIndicating the delay of the transmission of the first edge when the pulse changes, i.e. the output from1 to 0, tp＝tpHL(ii) a Otherwise, t isp＝tpLH。
The concrete description is as follows:
(1) first, the rising and falling edge delays of all logic gates in a circuit are summed to obtain the maximum tp,max；
tgate＝tpHL+tpLH(1)
tp,max＝MAX{tgate} (2)
(2) Once t is selectedp,maxThe next step is to determine the quantization clock period. To avoid overflow, the quantization period must be equal to the quotient of the sum of the maximum gate delays and the number of counter bits, i.e.:
Δt＝tp,max/2n(3)
(3) finally, the threshold of the comparator and the maximum value of the count for each gate are calculated, the threshold value judge being defined as the propagation delay t for any given logic gatepAnd the quantization period, and the maximum count result m of each gate is the sum of the delays of each gate divided by the quantization period:
(4) the manner in which a high level is output when the count value is greater than a certain value judge and a low level is output when the count value is less than a certain value judge can be shown in fig. 3.
According to the invention, through the research on SET transmission characteristics, a theoretical basis is established for the electric masking and broadening effects in single-event transient effect transmission, and a simulated fault injection method suitable for hardware simulation is developed on the basis. The method is characterized in that physical delay information of logic gates is normalized by a quantification method, and a maximum delay injection model is provided, wherein the model represents the real physical delay information by an up-down counter and a comparator, and simultaneously sets a comparator threshold value and a counter maximum value aiming at each gate to represent the propagation characteristics.
The application of the model is illustrated below as a specific application example:
as shown in fig. 4, a two-input nand hardware injection model of an embedded model is provided. The hardware injection model is constructed by adopting basic logic gates, can sequentially Inject all combined logic gates to be tested in a circuit, further realize the hardware simulation of the single-particle transient state of the whole circuit, replaces all the logic gates with an SET injection model in the circuit realization process, serially connects Mask _ in and Mask _ out of all nodes to be injected, and connects all Injects, thus realizing serial shift input. When pulse injection is carried out, after an injection vector moves into a trigger through a Mask _ en port, pulse injection can be carried out on a logic gate by controlling the pulse width of an Inject signal.
The specific application process is as follows:
(1) calculating according to formulas (1) - (5) and characterizing the transmission characteristics according to the flow shown in fig. 3;
(2) simulations were performed and the SER introduced by the SET injection into all gates was observed.
The method provided by the invention considers the electric masking effect and the pulse broadening effect of the pulse in the circuit transmission, models the electric masking effect and the pulse broadening effect as the physical delay information representation formula of the circuit gate circuit, and adopts a quantitative method to model the single-event transient effect, and establishes a single-event transient injection model suitable for hardware simulation and a single-event soft error rate analysis method facing a large-scale integrated circuit.
It will be appreciated by those of ordinary skill in the art that the embodiments described herein are intended to assist the reader in understanding the principles of the invention and are to be construed as being without limitation to such specifically recited embodiments and examples. Those skilled in the art can make various other specific changes and combinations based on the teachings of the present invention without departing from the spirit of the invention, and these changes and combinations are within the scope of the invention.
Claims (2)
1. A single-particle transient effect modeling method based on pulse transmission characteristics comprises the following specific steps:
s1, determining delay information of each gate circuit according to process library information of a target circuit;
s2, selecting a time scale delta t as unit time, and then transmitting delay information t of any logic gatepCan use
Δ t represents;
s3, characterizing Δ T in step S2 as Δ T in an amplification manner, where Δ T is m/f, m is 1,2,3, and f is an operating frequency of the FPGA hardware simulation system, and then the delay information of any logic gate in S2 can be quantized to n;
s4, establishing transmission characteristics between the SET pulse width and the transmission delay of the logic gate to represent electrical masking, attenuation and broadening characteristics in the pulse transmission process;
s5, delaying transmission by tpHLAnd tpLHRespectively carrying out quantization processing with the quantization clock period of delta T, namely the working clock of the hardware injection model, and summing the two transmission delays, wherein the summation result is TmaxWill [0, Tmax]Mapping to [0,2 ]n -1]When the rising edge of the input arrives, the counting is increased upwards from 0 until the full scale value and is kept unchanged; when a falling edge occurs, counting down from the existing value to the minimum value and keeping unchanged; when the count value is greater than the threshold value, a high level is output, and when the count value is less than the threshold value, a low level is output.
2. The method for modeling the single-particle transient effect based on the pulse transmission characteristics according to claim 1, wherein the three transmission characteristics of the electrical masking, attenuation and broadening characteristics in step S4 are specifically characterized as follows:
wherein, WinIs the SET pulse width, the maximum time required from the input signal crossing 50% VDD to the output signal crossing 50% VDD is the falling delay tpHL(ii) a In defining the change of the output signal from 0 to 1, the crossing of 50% V from the input signalDDThe maximum time required for the output signal to cross 50% VDD is the rise delay tpLH，tpIndicating a change in the pulse, the propagation delay of the first edge, i.e. the output changing from 1 to 0, tp＝tpHL(ii) a Otherwise, t isp＝tpLH。
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